COLLECTION OF VHDL LAB EXPERIMENTS PART - I

COMBINATIONAL CIRCUITS 1 a. b. 2 a. b. c. LOGIC GATES DATA FLOW BEHAVIORAL HALF ADDER DATA FLOW BEHAVIORAL STRUCTURAL Page No. 1 1 2 4 4 5 5

PART - II SEQUENTIAL CIRCUITS FLIP FLOPS 3. 4. 5. 6. 7. SR JK D T 4 BIT COUNTER 6 6 6 7 7 7

PART I : COMBINATIONAL CIRCUITS VHDL DATA FLOW MODEL FOR LOGIC GATES
library IEEE; use IEEE.STD_LOGIC_1164.ALL; --DATA FLOW --This program contains the code for all gates, but only one --gate is made active at a time and all others are commented --Remove comments for a specific gate and run simulation --ALL gates are simulated successfully on XILINX 13.2 entity dfrntgates is Port ( a : in bit; b : in bit; y : out bit); end dfrntgates; --architecture andgat of dfrntgates is --begin --y <= a and b; --end andgat; --architecture orgat of dfrntgates is --begin --y <= a or b; --end orgat; ---architecture nandgat of dfrntgates is --begin --y <= a nand b; --end nandgat; -architecture exorgat of dfrntgates is begin y <= a xor b; end exorgat; ---architecture norgat of dfrntgates is --begin --y <= a nor b; --end norgat; ---architecture notgat of dfrntgates is --begin --y <= not a; --end notgat;

VHDL BEHAVIORAL MODEL FOR LOGIC GATES

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --BEHAVIORAL --This program contains the code for all gates, but only one --gate is made active at a time and all others are commented --Remove comments for a specific gate and run simulation --ALL gates are simulated successfully on XILINX 13.2 entity dfrntgates is Port ( a : in bit; b : in bit; y : out bit); end dfrntgates; architecture andgat of dfrntgates is begin process (a,b) begin if a & b = "00" then y<='0'; elsif a & b ="01" then y<='0'; elsif a & b ="10" then y<='0'; elsif a & b ="11" then y<='1'; end if; end process; end andgat; --architecture orgat of dfrntgates is --begin --process (a,b) --begin --if a & b = "00" --then y<='0'; --elsif a & b ="01" --then y<='1'; --elsif a & b ="10" --then y<='1'; --elsif a & b ="11" --then y<='1'; --end if; --end process; --end orgat; -2

--architecture nandgat of dfrntgates is --begin --process (a,b) --begin --if a & b = "00" --then y<='1'; --elsif a & b ="01" --then y<='1'; --elsif a & b ="10" --then y<='1'; --elsif a & b ="11" --then y<='0'; --end if; --end process; --end nandgat; ---architecture exorgat of dfrntgates is --begin --process (a,b) --begin --if a & b = "00" --then y<='0'; --elsif a & b ="01" --then y<='1'; --elsif a & b ="10" --then y<='1'; --elsif a & b ="11" --then y<='0'; --end if; --end process; --end exorgat; ---architecture norgat of dfrntgates is --begin --process (a,b) --begin --if a & b = "00" --then y<='1'; --elsif a & b ="01" --then y<='0'; --elsif a & b ="10" --then y<='0'; --elsif a & b ="11" --then y<='0'; --end if; --end process; --end norgat; -3

--architecture notgat of dfrntgates is --begin --process(a) --begin --if a='0' --then y<='1'; --elsif a='1' --then y<='0'; --end if; --end process; --end notgat;

HALF ADDER : ALL MODELS

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --This program contains the code for all models of Half Adder, but --only one model is made active at a time and all others are commented --Remove comments for a specific model and run simulation --ALL models are simulated successfully on XILINX 13.2 entity hadrtyps is Port ( a : in BIT; b : in BIT; sum : out BIT; carry : out BIT); end hadrtyps;

--DATA FLOW MODEL OF HALF ADDER

--architecture Dataflow of hadrtyps is --begin --sum<=a xor b; --carry<=a and b; --end Dataflow;

--BEHAVIORAL MODEL OF HALF ADDER

--architecture Behavioral of hadrtyps is ---begin --process(a,b) ---begin --if a & b ="00" --then sum<='0'; carry<='0'; --elsif a & b ="01" --then sum<='1'; carry<='0'; --elsif a & b ="10" --then sum<='1'; carry<='0'; --else sum<='0'; carry<='1'; --end if; --end process; --end Behavioral;

--STRUCTURAL MODEL OF HALF ADDER entity andg is port(a,b:in bit; z:out bit); end andg; architecture e1 of andg is begin z<= a and b; end e1; entity xorg is port(a,b:in bit; z:out bit); end xorg; architecture e2 of xorg is begin z<= a xor b; end e2; architecture structmdl of hadrtyps is component andg port(a,b:in bit; z:out bit); end component; component xorg port(a,b:in bit; z:out bit); end component; begin a1 : xorg port map(a,b,sum); a2 : andg port map(a,b,carry); end structmdl;

PART II : SEQUENTIAL CIRCUITS VHDL CODE FOR FLIP FLOPS

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --Please Uncomment the required variables for --each flip flop section before simulation --All flip flops verified on Xilinx 13.2 entity fftypcal is Port ( clk : in STD_LOGIC; -d : in STD_LOGIC; t : in STD_LOGIC; -j : in BIT; -k : in BIT; -s : in BIT; -r : in BIT; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end fftypcal; --architecture SRFF of fftypcal is --begin --process(s,r,clk) --variable g: bit_vector(0 to 1); --begin --g:= s & r; --if clk='1' and clk' event --then --case g is --when "00"=> null; --when "01"=> q<='0'; qbar<='1'; --when "10"=> q<='1'; qbar<='0'; --when "11"=> q<='X'; qbar<='X'; --end case; --end if; --end process; --end SRFF; --architecture JKFF of fftypcal is --begin --process(j,k,clk) --variable s: bit_vector(0 to 1); --begin --s:= j & k; --if clk='1' and clk' event --then --case s is --when "00"=> null; --when "01"=> q<='0'; qbar<='1'; --when "10"=> q<='1'; qbar<='0'; --when "11"=> q<= not q; qbar<= q; --end case; --end if; --end process; --end JKFF;

--architecture DFF of fftypcal is --begin --process(d,clk) --begin --if clk='1' and clk' event --then --q<= d; --qbar<= not d; --end if; --end process; --end DFF; architecture TFF of fftypcal is begin process(t,clk) begin if clk='1' and clk' event then q<=not t; qbar<=t; end if; end process; end TFF;

FOUR BIT COUNTER WITH RESET

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fourbitcntr is port( clk, reset:in bit; count:out std_logic_vector( 0 to 2)); end fourbitcntr; architecture archi of fourbitcntr is signal temp: std_logic_vector( 0 to 2):="000"; BEGIN process ( clk, reset) begin if reset='1' then temp<="000"; else if clk='1' and clk'event then temp<= temp+ 1; end if; end if; end process; count<= temp; end archi;