LIC Manual

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DEPARTMENT OF EEE LAB MANUAL

CLASS SEMESTER SUBJECT CODE SUBJECT : II YEAR EEE : IV SEM : : LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY
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SYLLABUS
EE2258 AIM:
LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY
To study various digital & linear integrated circuits used in simple system configuration. LIST OF EXPERIMENTS: 1.
2. 3a) 3(b) 4. 5 6 7
Implementation of Boolean Functions, Adder/ Subtractor circuits. Code converters, Parity generator and parity checking, Excess-3, 2s Complement, Binary to Gray code using suitable ICs . Encoders and Decoders: Decimal and Implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable ICs.
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Timer IC application: Study of NE/SE 555 timer in Astable, Monostable operation. Application of Op-Amp: Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrator and Differentiator. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated ICs. Study of VCO and PLL ICs: i. Voltage to frequency characteristics of NE/ SE 566 IC. ii. Frequency multiplication using NE/SE 565 PLL IC. P = 45 Total = 45 2
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Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable ICs. Multiplex/ De-multiplex: Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer
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Counters: Design and implementation of 4-bit modulo counters as synchronous and Asynchronous types using FF ICs and specific counter IC.
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Study of Basic Digital ICs. (Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF, D FF)
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Detailed Syllabus 1.
Study of Basic Digital ICs. (Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF, D FF) Aim To test of ICs by using verification of truth table of basic ICs.
Exercise Breadboard connection of ICs with truth table verification using LEDs. 2.
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3b)
4.
Exercise 1 Conversion Binary to Grey, Grey to Binary; 1s. 2s complement of numbers addition, subtraction, 2. Parity checking of numbers using Gates and with dedicated ICs
Encoders and Decoders: Decimal and Implementation of 4-bit shift registers in SISO, SIPO,PISO,PIPO modes using suitable ICs. Exercise 1. Decimal to binary Conversion using dedicated ICs. 2. BCD 7 Segment display decoder using dedicated decoder IC& display. Counters: Design and implementation of 4-bit modulo counters as synchronous and asynchronous types using FF ICs and specific counter IC. Aim Design and implementation of 4 bit modulo counters. 3
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Aim Realizing code conversion of numbers of different bar.
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3a)
Code converters, Parity genertor and parity checking, Excess 3, 2s Complement, Binary to grey code using suitable ICs .
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Exercise 1. Realization of functions using SOP, POS, form. 2. Addition, Subtraction of atleast 3 bit binary number using basic gate IC s.
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Aim Minimization of functions using K-map implementation and combination Circuit.
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Implementation of Boolean Functions, Adder/ Subtractor circuits. [Minimizations using K-map and implementing the same in POS, SOP from using basic gates]
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Exercise 1. Using flipflop for up-down count synchronous count. 2. Realization of counter function using dedicated ICs. 5.
Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable ICs. Aim Design and implementation of shift register.
6.
Multiplex/ De-multiplex. Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer Aim To demonstrate the addressing way of data channel selection for multiplex Demultiplex operation. Exercise 1. Realization of mux-demux functions using direct ICs. 2. Realization of mux-demux using dedicated ICs for 4:1, 8:1, and vice versa.
7.
Timer IC application. Study of NE/SE 555 timer in Astable, Monostable operation. Aim To design a multi vibrater circuit for square wave and pulse generation. Exercise 1. Realization of Astable multivibrater & monostable multivibrater circuit using Timer IC. 2. Variation of R, C, to vary the frequency, duty cycle for signal generator. Application of Op-Amp-I Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrater and Differentiator. Aim Design and Realization of Op-Amp application. Exercise 1. Verification of Op-Amp IC characteristics. 2. Op-Amp IC application for simple arithmetic circuit. 3. Op-Amp IC application for voltage comparator wave generator and wave shifting circuits. 4
8.
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Exercise 1. Shift Register function realization of the above using dedicated ICs For SISO, SIPO, PISO, PIPO, modes of atleast 3 bit binary word. 2. Realization of the above using dedicated ICs.
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Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated ICs. Aim Realization of circuit for digital conversions.
10.
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Exercise 1. To realize V/F conversion using dedicated ICs vary the frequency of the generated signal. 2. To realize PLL IC based circuit for frequency multiplier, divider.
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Aim Demonstration of circuit for communication application
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Study of VCO and PLL ICs i) Voltage to frequency characteristics of NE/ SE 566 IC. ii) Frequency multiplication using NE/SE 565 PLL IC.
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Exercise 1. Design of circuit for analog to digital signal conversion using dedicated ICs. 2. Realization of circuit using dedicated IC for digital analog conversion.
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CYCLE I
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LIST OF EXPERIMENTS
1.
3.
5. Study of basic Digital ICs. 6. Implementation of Boolean functions. 7. Implementation of Half Adder & Full Adder.
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4.
Timer IC Applications II. ( Monostable Multivibrator)
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Timer IC Applications I. ( Astable Multivibrator)
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Applications of Op-Amp II. ( Differentiator and Integrator)
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Applications of Op-Amp - I. ( Inverting and Non Inverting Amplifier)
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CYCLE I :
Expt. No.1
APPLICATIONS OF OP-AMP - I ( INVERTING AND NON INVERTING AMPLIFIER) 1. a. INVERTING AMPLIFIER
To design an Inverting Amplifier for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741
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Vo = - ACL Vi Here the negative sign indicates that the output voltage is 180 input signal.
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The input signal Vi is applied to the inverting input terminal through R1 and the noninverting input terminal of the op-amp is grounded. The output voltage Vo is fed back to the inverting input terminal through the R f - R1 network, where Rf is the feedback resistor. The output voltage is given as,
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THEORY:
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1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the OpAmp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.
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PROCEDURE:
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out of phase with the
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Quantity 1 1 1 1 1
AIM:
PIN DIAGRAM:
DESIGN:
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We know for an inverting Amplifier ACL = RF / R1 Assume R1 ( approx. 10 K ) and find Rf Hence Vo = - ACL Vi OBSERVATIONS: Input Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) 9 Output Practical Theoretical
S.No 1. 2.
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CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:
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MODEL GRAPH:
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The design and testing of the inverting amplifier is done and the input and output waveforms were drawn.
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RESULT:
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1. b. NON - INVERTING AMPLIFIER
AIM: To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741 As required As required
Here the output voltage is in phase with the input signal. PROCEDURE:
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1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the non - inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.
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Vo = ACL Vi
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The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies the signal without inverting the input signal. It is also called negative feedback system since the output is feedback to the inverting input terminals. The differential voltage Vd at the inverting input terminal of the op-amp is zero ideally and the output voltage is given as,
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THEORY:
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Quantity 1 1 1 1 1
PIN DIAGRAM:
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We know for a Non-inverting Amplifier ACL = 1 + ( RF / R1) Assume R1 ( approx. 10 K ) and find Rf Hence Vo = ACL Vi OBSERVATIONS: Input Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) 12 Output Practical Theoretical
S.No 1. 2.
DESIGN:
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CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:
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MODEL GRAPH:
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The design and testing of the Non-inverting amplifier is done and the input and output waveforms were drawn.
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RESULT:
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Expt. No.2
APPLICATIONS OF OP-AMP - II
(DIFFERENTIATOR AND INTEGRATOR) 2. a. DIFFERENTIATOR AIM:
To design a Differentiator circuit for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Capacitors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741
As required
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1. Select fa equal to the highest frequency of the input signal to be differentiated. Then, assuming a value of C1 < 1 F, calculate the value of Rf. 2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.
The differentiator is most commonly used in waveshaping circuits to detect high frequency components in an input signal and also as a rateofchange detector in FM modulators.
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Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for the input bias current. A workable differentiator can be designed by implementing the following steps:
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The differentiator circuit performs the mathematical operation of differentiation; that is, the output waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor C1 . The expression for the output voltage is given as, Vo = - Rf C1 ( dVi /dt )
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THEORY:
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Quantity 1 1 1 1 1
PIN DIAGRAM:
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[ To design a differentiator circuit to differentiate an input signal that varies in frequency from 10 Hz to about 1 KHz. If a sine wave of 1 V peak at 1000Hz is applied to the differentiator , draw its output waveform.] Given fa = 1 KHz We know the frequency at which the gain is 0 dB, fa = 1 / (2 Rf C1) Let us assume C1 = 0.1 F ; then Rf = _________ Since fb = 20 fa , fb = 20 KHz We know that the gain limiting frequency fb = 1 / (2 R1 C1) Hence R1 = _________ Also since R1C1 = Rf Cf ; Cf = _________ 15
DESIGN :
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CIRCUIT DIAGRAM OF DIFFERENTIATOR:
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Given Vp = 1 V and f = 1000 Hz, the input voltage is Vi = Vp sin t We know = 2f Hence Vo = - Rf C1 ( dVi /dt ) = - 0.94 cos t PROCEDURE:
OBSERVATIONS: S.No 1. 2. Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) Input
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Output
MODEL GRAPH:
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RESULT: The design of the Differentiator circuit was done and the input and output waveforms were obtained.
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www.eeecube.blogspot.com 2. b. INTEGRATOR
AIM: To design an Integrator circuit for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Capacitors Connecting wires and probes 3 MHz 30 MHz 0 30 V IC 741
As required
Vo = - (1/Rf C1 ) Vi dt Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < fb . The input signal will be integrated properly if the Time period T of the signal is larger than or equal to Rf Cf . That is,
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The integrator is most commonly used in analog computers and ADC and signal-wave shaping circuits.
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A circuit in which the output voltage waveform is the integral of the input voltage waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the output voltage is given as,
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THEORY:
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Range
Quantity 1 1 1 1 1
PIN DIAGRAM:
CIRCUIT DIAGRAM OF INTEGRATOR:
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DESIGN: [ To obtain the output of an Integrator circuit with component values R 1Cf = 0.1ms , Rf = 10 R1 and Cf = 0.01 F and also if 1 V peak square wave at 1000Hz is applied as input.] We know the frequency at which the gain is 0 dB, fb = 1 / (2 R1 Cf) Therefore fb = _____ Since fb = 10 fa , and also the gain limiting frequency fa = 1 / (2 Rf Cf) We get , R1 = _______ and hence Rf = __________
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PROCEDURE:
OBSERVATIONS: S.No 1. 2. Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) Input
MODEL GRAPH:
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RESULT: The design of the Integrator circuit was done and the input and output waveforms were obtained.
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Output
Expt. No.3
TIMER IC APPLICATIONS - I ( ASTABLE MULTIVIBRATOR)
AIM: To design an Astable multivibrator circuit for the given specifications using 555 Timer IC.
THEORY:
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Similarly the time during which the capacitor discharges from 2/3 V cc to 1/3 Vcc is equal to the time the output is low and is given by, td = 0.69 (R2) C
Thus the total time period of the output waveform is,
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The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time t c during which the output is high to the total time period T. It is generally expressed in percentage. In equation form, % duty cycle = [( R1 + R2) / (R1 + 2 R2)] x 100
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An Astable multivibrator, often called a free-running multivibrator, is a rectangularwave-generating circuit. This circuit do not require an external trigger to change the state of the output. The time during which the output is either high or low is determined by two resistors and a capacitor, which are connected externally to the 555 timer. The time during which the capacitor charges from 1/3 V cc to 2/3 Vcc is equal to the time the output is high and is given by, tc = 0.69 (R1 + R2) C
T = tc + td = 0.69 (R1 + 2 R2) C
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S.No 1. 2. 3. 4. 5. 6. 7. 8.
Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes
Range 3 MHz 30 MHz 0 30 V IC 555
As required
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Quantity 1 1 1 1 1
APPARATUS REQUIRED:
PIN DIAGRAM:
CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR
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DESIGN:
[ To design an astable multivibrator with 65% duty cycle at 4 KHz frequency, assume C= 0.01 F] Given f= 4 KHz, Therefore, Total time period, T = 1/f = ____________
PROCEDURE:
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OBSERVATIONS:
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1. Connections are given as per the circuit diagram. 2. + 5V supply is given to the + Vcc terminal of the timer IC. 3. At pin 3 the output waveform is observed with the help of a CRO 4. At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage waveforms are plotted in a graph sheet.
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Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) tc td 22
tc = 0.69 (R1 + R2) C Therefore, R1 = _____________
S.No
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1. 2.
Output Voltage , Vo Capacitor voltage , Vc
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We also know for an astable multivibrator td = 0.69 (R2) C Therefore, R2 = _____________
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We know, duty cycle = tc / T Therefore, tc = -----------------------and td = ____________
MODEL GRAPH:
RESULT:
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The design of the Astable multivibrator circuit was done and the output voltage and capacitor voltage waveforms were obtained.
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Expt. No.4 AIM:
TIMER IC APPLICATIONS -II ( MONOSTABLE MULTIVIBRATOR)
To design a monostable multivibrator for the given specifications using 555 Timer IC.
THEORY:
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At the end of the timing interval, the output automatically reverts back to its logic low state. The output stays low until a trigger pulse is applied again. Then the cycle repeats. Thus the monostable state has only one stable state hence the name monostable.
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A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand-by state the output of the circuit is approximately zero or at logic low level. When an external trigger pulse is applied, the output is forced to go high (approx. Vcc). The time during which the output remains high is given by, tp = 1.1 R1 C
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S.No 1. 2. 3. 4. 5. 6. 7. 8.
Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes
As required
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Range 3 MHz, Analog 30 MHz 0 30 V IC 555
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Quantity 1 1 1 1 1
APPARATUS REQUIRED:
PIN DIAGRAM:
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CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:
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DESIGN:
[ To design a monostable multivibrator with tp = 0.616 ms , assume C = 0.01 F ] Given tp = 0.616 ms = 1.1 R1 C Therefore, R1 = _____________ PROCEDURE: 1. 2. 3. 4. 5.
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OBSERVATIONS:
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Connections are given as per the circuit diagram. + 5V supply is given to the + Vcc terminal of the timer IC. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC At pin 3 the output waveform is observed with the help of a CRO At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage waveforms are plotted in a graph sheet.
S.No
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Amplitude ( No. of div x Volts per div )
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Trigger input Output Voltage , Vo
Capacitor voltage , Vc
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Time period ( No. of div x Time per div ) toff
MODEL GRAPH:
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The design of the Monostable multivibrator circuit was done and the input and output waveforms were obtained.
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RESULT:
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Expt. No.5
STUDY OF BASIC DIGITAL ICS
AIM: To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 As required
a. AND gate:
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c. NOT gate: A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input.
An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of 1 if any of the input signal is 1.
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b. OR gate:
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An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of 1 only if all the input signals are 1.
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THEORY:
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Quantity 1 1 1 1 1 1 1
AND GATE LOGIC DIAGRAM:
PIN DIAGRAM OF IC 7408 :
CIRCUIT DIAGRAM:
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TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A.B 0 0 0 1
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OR GATE LOGIC DIAGRAM:
TRUTH TABLE:
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CIRCUIT DIAGRAM:
S.No 1. 2. 3. 4.
INPUT A 0 0 1 1 B 0 1 0 1
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OUTPUT Y=A+B 0 1 1 1 30
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NOT GATE LOGIC DIAGRAM:
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TRUTH TABLE: S.No 1. 2. INPUT A 0 1 OUTPUT Y = A 1 0
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CIRCUIT DIAGRAM:
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NAND GATE LOGIC DIAGRAM:
CIRCUIT DIARAM:
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TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A . B) 1 1 1 0
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S.No 1. 2. 3. 4.
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NOR GATE LOGIC DIAGRAM:
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TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A + B) 1 0 0 0
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S.No 1. 2. 3. 4.
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CIRCUIT DIAGRAM:
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EX-OR GATE LOGIC DIAGRAM
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TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A B 0 1 1 0
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CIRCUIT DIAGRAM:
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d. NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate will be 0 if all the input signals are 1 and will be 1 if any one of the input signal is 0. e. NOR gate: A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if all the inputs are 0 and will be 0 if any one of the input signal is 1. f. EX-OR gate: An Ex-OR gate performs the following Boolean function, A B = ( A . B ) + ( A . B )
PROCEDURE:
The truth table of all the basic digital ICs were verified.
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RESULT:
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1. Connections are given as per the circuit diagram 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for all gates.
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It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal 0 when the two input signals are equal either 0 or 1.
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Expt. No.6 AIM:
IMPLEMENTATION OF BOOLEAN FUNCTIONS
To design the logic circuit and verify the truth table of the given Boolean expression, F (A,B,C,D) = (0,1,2,5,8,9,10) APPARATUS REQUIRED: S.No Name of the Apparatus 1. Digital IC trainer kit 2. AND gate 3. OR gate 4. NOT gate 5. NAND gate 6. NOR gate 7. EX-OR gate 8. Connecting wires DESIGN: Given , F (A,B,C,D) = (0,1,2,5,8,9,10) Range IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486
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The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a simplified expression for the output as shown,
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From the K-Map, F = B C + D B + A C D Since we are using only two input logic gates the above expression can be re-written as, F = C (B + A D) + D B Now the logic circuit for the above equation can be drawn. 36
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As required
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Quantity 1
CIRCUIT DIAGRAM:
TRUTH TABLE: S.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
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A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
INPUT B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
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D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT F=DB+C(B+AD) 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 37
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PROCEDURE: 1. Connections are given as per the circuit diagram 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the given Boolean expression. RESULT: The truth table of the given Boolean expression was verified.
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Expt. No. 8
IMPLEMENTATION OF HALF ADDER & FULL ADDER
AIM: To design and verify the truth table of the Half Adder & Full Adder circuits. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7486 As required
THEORY:
HALF ADDER:
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A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits. FULL ADDER: A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate.
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The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum.
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0+0=0 0+1=1 1+0=1 1 + 1 = 102
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The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely,
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Quantity 1
HALF ADDER TRUTH TABLE: S.No 1. 2. 3. 4. DESIGN: INPUT A 0 0 1 1 B 0 1 0 1
OUTPUT S 0 1 1 0 C 0 0 0 1
CIRCUIT DIAGRAM:
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TRUTH TABLE:
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S.No 1. 2. 3. 4. 5. 6. 7. 8.
A 0 0 0 0 1 1 1 1
INPUT B 0 0 1 1 0 0 1 1
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FULL ADDER C 0 1 0 1 0 1 0 1 40 OUTPUT SUM CARRY 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1
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From the truth table the expression for sum and carry bits of the output can be obtained as, Sum, S = A B Carry, C = A . B
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DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained as, SUM = ABC + ABC + ABC + ABC CARRY = ABC + ABC + ABC +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as, SUM
SUM = ABC + ABC + ABC + ABC = A
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B C CIRCUIT DIAGRAM:
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CARRY = AB + AC + BC
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CARRY
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PROCEDURE:
1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half adder and full adder circuits. RESULT:
The design of the half adder and full adder circuits was done and their truth tables were verified.
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CYCLE II
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LIST OF EXPERIMENTS
CYCLE II :
11. Multiplexer / Demultiplexer 12. Study of Flip-Flops.
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14. Shift Register.
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13. Asynchronous Decade counter
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10. Parity Generator & Checker.
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9. Code converters.
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8.
Implementation of Half Subtractor & Full Subtractor.
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Expt. No. 8
IMPLEMENTATION OF HALF SUBTRACTOR & FULL SUBTRACTOR
AIM: To design and verify the truth table of the Half Subtractor & Full Subtractor circuits. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7486 As required
THEORY:
HALF SUBTRACTOR:
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A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. FULL SUBTRACTOR: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.
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In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.
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0-0=0 0 - 1 = 1 with 1 borrow 1-0=1 1-1=0
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The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely,
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Quantity 1
HALF SUBTRACTOR www.eeecube.blogspot.com TRUTH TABLE: S.No 1. 2. 3. 4. DESIGN: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT DIFF BORR 0 0 1 1 1 0 0 0
CIRCUIT DIAGRAM:
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Difference, DIFF = A B Borrow, BORR = A . B
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From the truth table the expression for difference and borrow bits of the output can be obtained as,
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FULL SUBTRACTOR TRUTH TABLE: S.No 1. 2. 3. 4. 5. 6. 7. 8. DESIGN: INPUT B 0 0 1 1 0 0 1 1
From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF= ABC + ABC + ABC + ABC Borrow, BORR = ABC + ABC + ABC +ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as, DIFFERENCE
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DIFF = ABC + ABC + ABC + ABC = A
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B C BORR = AB + AC + BC 47
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BORROW
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A 0 0 0 0 1 1 1 1
C 0 1 0 1 0 1 0 1
OUTPUT DIFF BORR 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 1
CIRCUIT DIAGRAM:
PROCEDURE:
RESULT:
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The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.
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1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half subtractor and full subtractor circuits.
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Expt. No. 9
CODE CONVERTERS
AIM: To design and verify the truth table of a three bit binary to gray code converter. APPARATUS REQUIRED: S.No 1. 2. 3. Name of the Apparatus Digital IC trainer kit EX-OR gate Connecting wires Range IC 7486
DESIGN:
TRUTH TABLE:
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The Gray code is also called as reflective code. The gray coded number corresponding to the decimal number 2n 1, for any n, differs from gray coded 0 (0000) in one bit position only.
S.No 1. 2. 3. 4. 5. 6. 7. 8.
INPUT - BINARY A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
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A combinational circuit performs the transformation of a three bit binary to gray code converter by means of logic gates. The input variables are binary bits named as A,B,C with A as the MSB and C as the LSB. The Gray code output bits are termed as X,Y,Z with X as the MSB and Z as the LSB.
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Code converter is a circuit that makes two systems compatible even though each uses different binary codes. There is a wide variety of binary codes used in digital systems. Some of these codes are Binary Coded Decimal, Gray code, Excess- 3 code , ASCII code, etc.
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OUTPUT-GRAY X Y Z 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0
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THEORY:
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Quantity 1 As required
From the truth table the expression for the output gray bits are, X (A, B, C) = (4, 5, 6, 7) Y (A, B, C) = (2, 3, 4, 5) Z (A, B, C) = (1, 2, 5, 6)
Hence obtain the reduced SOP expression using Karnaugh maps as follows, For X:
X=A For Y:
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Y=A B
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For Z:
Z=B
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CIRCUIT DIAGRAM:
3 BIT BINARY TO GRAY CODE CONVERTER
PROCEDURE:
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The design of the three bit Binary to Gray code converter circuit was done and its truth table was verified.
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RESULT:
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1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the three bit binary to gray code converter.
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Expt. No. 10
PARITY GENERATOR & CHECKER
AIM: To design and verify the truth table of a three bit Odd Parity generator and checker. APPARATUS REQUIRED: S.No 1. 2. 3. 4. Name of the Apparatus Digital IC trainer kit EX-OR gate NOT gate Connecting wires Range IC 7486 IC 7404
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Since the information was transmitted with odd parity the four bits received must have an odd number of 1s. An error occurs during the transmission if the four bits received have an even number of 1s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1s.
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In even parity the added parity bit will make the total number of 1s an even amount and in odd parity the added parity bit will make the total number of 1s an odd amount. In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission.
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A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker.
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THEORY:
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www.eeecube.blogspot.com ODD PARITY GENERATOR

TRUTH TABLE: INPUT ( Three bit message) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT ( Odd Parity bit) P 1 0 0 1 0 1 1 0
S.No 1. 2. 3. 4. 5. 6. 7. 8.
From the truth table the expression for the output parity bit is, P( A, B, C) = (0, 3, 5, 6) Also written as,
P = ABC + ABC + ABC + ABC = (A
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B C)
CIRCUIT DIAGRAM:
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ODD PARITY GENERATOR
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ODD PARITY CHECKER TRUTH TABLE: INPUT ( four bit message Received ) A B C P 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
OUTPUT (Parity error check) X 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1
S.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
X (A, B, C, P) = (0, 3, 5, 6, 9, 10, 12, 15) The above expression is reduced as,
CIRCUIT DIAGRAM:
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X = (A
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ODD PARITY CHECKER
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From the truth table the expression for the output parity checker bit is,
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P) 54
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PROCEDURE:
1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the Parity generator and checker. RESULT: The design of the three bit odd Parity generator and checker circuits was done and their truth tables were verified.
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Expt. No. 11 AIM:
MULTIPLEXER & DEMULTIPLEXER
To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. Name of the Apparatus Digital IC trainer kit OR gate NOT gate AND gate ( three input ) Connecting wires Range IC 7432 IC 7404 IC 7411
THEORY:
DESIGN: LOGIC SYMBOL:
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A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines.
4 X 1 MULTIPLEXER
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Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine which input is selected. Therefore, multiplexer is many into one and it provides the digital equivalent of an analog selector switch.
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TRUTH TABLE: SELECTION INPUT S1 S2 0 0 0 1 1 0 1 1
OUTPUT Y I0 I1 I2 I3
S.No 1. 2. 3. 4.
PIN DIAGRAM OF IC 7411:
CIRCUIT DIAGRAM:
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1X4 DEMULTIPLEXER
LOGIC SYMBOL:
TRUTH TABLE: INPUT S1 S2 Din 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
S.No 1. 2. 3. 4. 5. 6. 7. 8.
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OUTPUT Y0 Y1 Y2 Y3 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1
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CIRCUIT DIAGRAM:
PROCEDURE:
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RESULT:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables were verified.
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1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer.
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Expt. No. 12 AIM:
www.eeecube.blogspot.com STUDY OF FLIP FLOPS
To verify the characteristic table of RS, D, JK, and T Flip flops . APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit NOR gate NOT gate AND gate ( three input ) NAND gate Connecting wires Range IC 7402 IC 7404 IC 7411 IC 7400
THEORY:
RS FLIP FLOP:
D FLIP FLOP:
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To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other. JK FLIP FLOP: The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock pulse, similarly the output Q is ANDed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided. 60
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The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate state.
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A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states.
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T FLIP FLOP:
This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop. RS FLIP FLOP LOGIC SYMBOL:
CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE:
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CLOCK PULSE 1 2 3 4 5 6 7 8
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INPUT S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1
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PRESENT STATE (Q) 0 1 0 1 0 1 0 1 61 NEXT STATE(Q+1) 0 1 0 0 1 1 X X
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STATUS
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D FLIP FLOP LOGIC SYMBOL:
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CLOCK PULSE 1 2 3 4
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INPUT D 0 0 1 1
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PRESENT STATE (Q) 0 1 0 1
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NEXT STATE(Q+1) 0 0 1 1 STATUS 62
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CIRCUIT DIAGRAM:
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JK FLIP FLOP LOGIC SYMBOL:
CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE: CLOCK PULSE 1 2 3 4 5 6 7 8
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INPUT J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1
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PRESENT STATE (Q) 0 1 0 1 0 1 0 1 NEXT STATE(Q+1) 0 1 0 0 1 1 1 0
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STATUS
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T FLIP FLOP LOGIC SYMBOL:
CIRCUIT DIAGRAM:
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CLOCK PULSE 1 2 3 4
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INPUT T 0 0 1 1
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PRESENT STATE (Q) 0 1 0 1
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NEXT STATE(Q+1) 0 0 1 0 STATUS 64
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PROCEDURE:
1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and observe the status of all the flip flops. RESULT: The Characteristic tables of RS, D, JK, T flip flops were verified.
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Expt. No. 13 AIM: To implement and verify the truth table of an asynchronous decade counter. APPARATUS REQUIRED: S.No 1. 2. 4. 5. Name of the Apparatus Digital IC trainer kit JK Flip Flop NAND gate Connecting wires Range IC 7473 IC 7400 ASYNCHRONOUS DECADE COUNTER
THEORY:
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Asynchronous decade counter is also called as ripple counter. In a ripple counter the flip flop output transition serves as a source for triggering other flip flops. In other words the clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the transition that occurs in other flip flops. The term asynchronous refers to the events that do not occur at the same time. With respect to the counter operation, asynchronous means that the flip flop within the counter are not made to change states at exactly the same time, they do not because the clock pulses are not connected directly to the clock input of each flip flop in the counter.
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Quantity 1 2 1 As required
CIRCUIT DIAGRAM:
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PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter.
RESULT: The truth table of the Asynchronous decade counter was hence verified.
1 2 3 4 5 6 7 8 9 10 11
D(MSB) 0 0 0 0 0 0 0 0 1 1 0
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S.No
CLOCK PULSE 1 2 3 4 5 6 7 8 9 10
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C 0 0 0 0 1 1 1 1 0 0 0
TRUTH TABLE:
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OUTPUT B 0 0 1 1 0 0 1 1 0 1 0 A(LSB) 0 1 0 1 0 1 0 1 0 0 0
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Expt. No. 14 AIM:
IMPLEMENTATION OF SHIFT REGISTERS
To implement and verify the truth table of a serial in serial out shift register. APPARATUS REQUIRED: S.No 1. 2. 3. Name of the Apparatus Digital IC trainer kit D Flip Flop Connecting wires Range IC 7474
THEORY:
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The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines, what goes into the right most flip flop during the shift. The serial output is taken from the output of the left most flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift register can function either as a shift right or a shift left register.
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A register capable of shifting its binary information either to the left or to the right is called a shift register. The logical configuration of a shift register consists of a chain of flip flops connected in cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse which causes the shift from one stage to the next.
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Quantity 1 2 As required
CIRCUIT DIAGRAM:
TRUTH TABLE: For a serial data input of 1101, S.NO 1 2 3 4 5 6 7 8 CLOCK PULSE 1 2 3 4 5 6 7 8 D1 1 1 0 1 X X X X
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PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter.
RESULT: The truth table of a serial in serial out left shift register was hence verified.
INPUTS D2 D3 X X 1 X 1 1 0 1 1 0 X 1 X X X X
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D4 X X X 1 1 0 1 X Q1 1 1 0 1 X 1 0 X OUTPUTS Q2 Q3 X X 1 X 1 1 0 1 1 0 X 1 X X X X
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Q4 X X X 1 1 0 1 X
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www.eeecube.blogspot.

DEPARTMENT OF EEE LAB MANUAL

LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

Aim Realizing code conversion of numbers of different bar.

Aim Minimization of functions using K-map implementation and combination Circuit.

Aim Demonstration of circuit for communication application

Timer IC Applications II. ( Monostable Multivibrator)

Timer IC Applications I. ( Astable Multivibrator)

Applications of Op-Amp II. ( Differentiator and Integrator)

Applications of Op-Amp - I. ( Inverting and Non Inverting Amplifier)

APPLICATIONS OF OP-AMP - I ( INVERTING AND NON INVERTING AMPLIFIER) 1. a. INVERTING AMPLIFIER

out of phase with the

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

1. b. NON - INVERTING AMPLIFIER

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

(DIFFERENTIATOR AND INTEGRATOR) 2. a. DIFFERENTIATOR AIM:

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

CIRCUIT DIAGRAM OF INTEGRATOR:

TIMER IC APPLICATIONS - I ( ASTABLE MULTIVIBRATOR)

Thus the total time period of the output waveform is,

T = tc + td = 0.69 (R1 + 2 R2) C

Range 3 MHz 30 MHz 0 30 V IC 555

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR

tc = 0.69 (R1 + R2) C Therefore, R1 = _____________

Output Voltage , Vo Capacitor voltage , Vc

We also know for an astable multivibrator td = 0.69 (R2) C Therefore, R2 = _____________

We know, duty cycle = tc / T Therefore, tc = -----------------------and td = ____________

Expt. No.4 AIM:

TIMER IC APPLICATIONS -II ( MONOSTABLE MULTIVIBRATOR)

Range 3 MHz, Analog 30 MHz 0 30 V IC 555

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

Amplitude ( No. of div x Volts per div )

Trigger input Output Voltage , Vo

STUDY OF BASIC DIGITAL ICS

AND GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408 :

TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A.B 0 0 0 1

OR GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7432 :

NOT GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7404 :

TRUTH TABLE: S.No 1. 2. INPUT A 0 1 OUTPUT Y = A 1 0

NAND GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7400 :

TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A . B) 1 1 1 0

NOR GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7402 :

TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A + B) 1 0 0 0

EX-OR GATE LOGIC DIAGRAM

PIN DIAGRAM OF IC 7486 :

TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A B 0 1 1 0

Expt. No.6 AIM:

IMPLEMENTATION OF BOOLEAN FUNCTIONS

IMPLEMENTATION OF HALF ADDER & FULL ADDER

0+0=0 0+1=1 1+0=1 1 + 1 = 102

HALF ADDER TRUTH TABLE: S.No 1. 2. 3. 4. DESIGN: INPUT A 0 0 1 1 B 0 1 0 1

SUM = ABC + ABC + ABC + ABC = A

11. Multiplexer / Demultiplexer 12. Study of Flip-Flops.

14. Shift Register.

13. Asynchronous Decade counter

10. Parity Generator & Checker.

Implementation of Half Subtractor & Full Subtractor.

IMPLEMENTATION OF HALF SUBTRACTOR & FULL SUBTRACTOR

0-0=0 0 - 1 = 1 with 1 borrow 1-0=1 1-1=0