Chip level timing

Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly about timing with flip-flops; i.e.,
Data input must be stable before active clock edge (setup time). Data input must be stable after active clock edge (hold time). Data output doesnt change immediately after the active clock edge (clock-tooutput time).

When we build an entire circuit (one with both flip-flops and combinational logic), there are other important timing concepts to understand.

ECE124 Digital Circuits and Systems

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Cycle times (1)

Consider flip-flop outputs begin used to generate flip-flop inputs:

Tco

Tdata combinatorial logic (and delay)

Tsu

clk Tclk1

Tclk2

It takes time for signals to arrive where they need to be

ECE124 Digital Circuits and Systems

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Cycle times (2)

Sequence of events in transfer of data between flip-flops: Takes time for active clock edge to arrive at first FF (Tclk1). Once active clock edge arrives, takes time for output of first FF to change (+Tco). Takes time for output of first FF to cause changes in the input value to the second FF due to combinatorial logic between FF (+Tdata). Input at second FF must be present prior to active clock edge at second FF (Tsu). Takes time for clock to arrive at second FF (Tclk2). Must be some limit of how fast we can clock the circuit (i.e., the frequency of clock signal): Data output from first FF must get to data input of second FF prior to the next active clock edge.

ECE124 Digital Circuits and Systems

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Cycle times (3)

For the data output of the first FF to get to the data input of the second FF in sufficient time, the following must be true:

The minimum period (maximum frequency) of the circuit is:

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Cycle times (4)

Tco Tdata combinatorial logic (and delay) Tsu

clk Tclk1

Tclk2

The equation for Tcycle tells us a minimum clock period (or maximum frequency) at which our circuit can operate without violating the setup time at the second FF input.

ECE124 Digital Circuits and Systems

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Cycle times (5)

Tclk1 CLK FF1 CLK FF2 CLK FF1 Q FF2 D Tclk1 Tcycle Tdata

Tco

Tsu

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Clock skew
If we look at our equation for maximum frequency:

The term (Tclk1 Tclk2) that measures the difference in time between the arrival of the active clock edge at the two flip-flops. This difference is called clock skew and it can be positive or negative. In general, clock skew is a big hassle, and we would like to avoid it if possible.

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Inverted clocks (1)

Sometimes we might have flip-flops clocked on different edges of the clock; some flipflops trigger on the rising edge and others on the falling edge. This can limit the maximum frequency of the circuit too since we have less time to get data to where it needs to be!
Tco Tdata combinatorial logic (and delay) Tsu

clk Tclk1

Tclk2

Rising edge
ECE124 Digital Circuits and Systems

Falling edge
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Inverted clocks (2)

Tclk1 CLK FF1 CLK FF2 CLK FF1 Q FF2 D Tclk1 Tcycle Tco Tdata Tsu

Since the second FF is triggered on the falling edge, either Tdata must be short enough, or the cycle time for the clock needs to be lengthened (lower frequency) to allow the data to get to the second FF.
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ECE124 Digital Circuits and Systems

Duty cycles
Sometimes the clock signal is not symmetric; It has a non-uniform duty cycle. If we use both rising and falling edge triggering, this can also affect the clock frequency.
2/3 high (66% duty cycle) CLK 1/3 low

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Setup and hold times at the pins of a chip (1)

Say we have a circuit implemented inside of an integrated circuit (IC) chip. The circuit and IC now looks like a black-box. Timing at the pins of the chip are now important. Suppose you have a data present at at input pin on the IC. The signal might go through some logic inside the IC prior to reaching a flipflop input inside of the IC. The flip-flop inside of the IC is clocked by another clock signal applied at another pin of the IC.

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Setup and hold times at the pins of a chip (2)

There is a setup and hold time at the flip-flop inside of the IC and a relationship between the FF-D input and the FF-CLK input. Therefore, there must be a relationship between the data input and the clock input at the chip pins.
Tdata data Tsu combinatorial logic (and delay) Tsu/Th
D Q

clk Tclk

pins at IC boundary

logic inside IC

flip-flop inside IC

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Setup and hold times at the pins of a chip (3)

Let:

cf cc df dc

- time when active clock edge arrives at FF CLK INPUT. - time when active clock edge arrives at CLK PIN. - time when data input at FF D INPUT makes a transition. - time when data input at DATA PIN makes a transition.

Let: Tsu Th Let: Tsetup Thold

- the setup time of the FF D input w.r.t. the FF CLK input. - the hold time of the FF D input w.r.t. the FF CLK input.

- the setup time of the DATA PIN input w.r.t. the CLK PIN. - the hold time of the DATA PIN input w.r.t. the CLK PIN.

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Setup and hold times at the pins of a chip (4)

The following must be true at the flip-flop: df not in [cf-Tsu,cf+th] otherwise the flipflop might not work correctly (data must be stable around the active clock edge). Two inequalities:
df not in [cf-Tsu,cf+Th] df < cf Tsu dc+Tdata = df cc + Tclk = cf dc+Tdata < cc+Tclk-Tsu implies: but: and: so: and: df not in [cf-Tsu,cf+Th] df > cf + Th dc+Tdata = df cc + Tclk = cf dc+Tdata > cc+Tclk+Th implies: but: and: so: and:

dc < cc (Tsu-Tclk+Tdata).

dc > cc + (Th+Tclk-Tdata).

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Setup and hold times at the pins of a chip (5)

We find a relationship between the data input and clock input at the IC PINS due to the relationship at the FF inputs inside the chip:
dc < cc (Tsu-Tclk+Tdata). dc > cc + (Th+Tclk-Tdata).

So, we have the relationship: dc not in [cc-Tsetup,cc+Thold] There are setup and hold times at the IC inputs. When we use an IC, we must pay attention to these times to make sure that the IC will work correctly.

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Setup and hold times at the pins of a chip (6)

Tdata data Tsu combinatorial logic (and delay) Tsu/Th
D Q

clk Tclk

Tseup

Thold Tclk

pins at IC boundary

logic inside IC

flip-flop inside IC

Tsu

Th

CLK FF CLK FF D DATA Tdata Tdata

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Setup and hold times at the pins of a chip (7)

When active clock edge arrives at a FF CLK input, the FF Q output changes after Tco. Consider that the FF Q output drives OUTPUT PIN of IC. Output will not appear for an amount of time called CLOCK-TO-OUTPUT TIME.
Tdata Tco
D Q

clk Tclk pins at IC boundary flip-flop inside IC

combinatorial logic (and delay)

data

logic inside IC

Tclock_to_output = Tclk + Tco + Tdata

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Setup and hold times at the pins of a chip (8)

Tdata Tco
D Q

clk
Tclk Tco Tdata

combinatorial logic (and delay)

data

Tclk pins at IC boundary flip-flop inside IC logic inside IC

CLK FF CLK FF D FF Q DATA

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