Cache Jargon

CS220: Introduction to Computer Organization 2011-12 Ist Semester

Block: A set of contiguous address locations of some size.

A cache block is also called cache line.

Memory - IV
Amey Karkare karkare@cse.iitk.ac.in
Department of CSE, IIT Kanpur

Replacement policy
Rules for creating space for a new block in cache. LRU, FIFO, LFU, random . . .

Cache Hit/Cache Miss

Hit: If the requested address exists in cache. Miss: Otherwise.

Associativity
Number of possible tags where a physical block may be found Fully associative, k-way associative

Write Policy
Write through, Write back

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Cache Mapping Algorithms: Example

Direct Mapping

Block B of main memory mapped to block B %128 of cache.

Blocks 0, 128, 256, . . . mapped to cache location 0. Blocks 1, 129, 259, . . . mapped to cache location 1, and so on. Total 32 memory blocks mapped per cache location. Contention may occur even if the cache is not full. Trivial replacement algorithm: replace the existing block.

Main Memory
16-bit address. 4K blocks of 16 bytes each. Total 64K bytes.

Cache
128 blocks of 16 bytes each. Total 2048 (2K) bytes.

16-bit memory address divided in three parts. Tag Location # Offset 5 7 4

Lower 4 bits of address are the offset within the block (24 = 16). Middle 7 bits of address point to a particular location in the cache (27 = 128) Upper 5 bits of address are compared with tag (25 = 32).

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Direct Mapping: Hardware Implementation

Fully Associative Mapping

A memory block can be placed into any cache block location.

Space in the cache can be utilized efciently. A new block replaces an old block only when the cache is full. All the tags are searched parallely for the desired block. Very high hardware cost for search.

16-bit memory address divided in two parts. Tag Offset 12 4

Lower 4 bits of address are the offset within the block (24 = 16). Upper 12 bits of address are compared with tag (212 = 4096 = 4K ).

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Set Associative Mapping

Set Associative Mapping

A combination of direct- and fully associative- mapping Blocks in cache are grouped into sets.
k-way associative: Each set contains k blocks. k = 1 direct mapping. k = # of cache blocks fully associative.

16-bit memory address divided in three parts. Example: 2-way set associative.
Total 128/2 = 64 sets. Total 64 blocks mapped per set. Tag Set # 6 6

A block in main memory can be placed in any block of a specic set.

Contention is reduced w.r.t. direct mapping. Hardware cost is reduced w.r.t. fully associative mapping.

Offset 4

Lower 4 bits of address are the offset within the block (24 = 16). Middle 6 bits of address specify the set (26 = 64). Upper 6 bits of address are compared with tag (26 = 64).

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Set Associative Mapping: Hardware Implementation

Replacement Policies

Cache controller need to implement policies about:

When do we replace? (easy to answer!) How do we replace?

Replacement: at the time of conict.

All k blocks in the target set are full.

Which of the k blocks to replace?

FIFO, LRU, random. May require extra information in the tag. Schemes are easier for small k (1 or 2)

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Extra Information in TAG

Other Issues

For FIFO scheme, we need counters.

When a block is replaced, counter for all other blocks in the same set are incremented. For the block brought in, counter is set to 0.

What do we do if the cache block is not in sync with memory? Cache block is more current. Need to store this information. Dirty (D) bit per block.
Set when a write occurs in the block. Reset when a new block is brought it. If dirty bit is set, write the block in memory before reading another block.

For LRU scheme, we need reference registers.

When a block is referred to, a 1 is inserted in the ref bits of the referred block and 0 in all other blocks.

In case of FIFO, replacement candidate is selected with highest counter value. In case of LRU, replacement candidate is chosen using ref bits with most zeros at the end. For k = 2, we need just one bit of history/reference information per block. For k = 1 (direct mapping) we need no extra information.
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Valid (V) bit

Whether the contents of a cache block or valid or not.

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