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Avago LTE PA
Avago LTE PA
Data Sheet
Description
The ACPM-5017 is a fully matched 10-pin surface mount module developed for LTE Band12 and Band 17. This power amplifier module operates in the 698-716MHz bandwidth. The ACPM-5017 meets stringent LTE (MPR=0dB) linearity requirements up to 27.5 dBm output power. The 3 x 3 mm form factor package is self contained, incorporating 50 ohm input and output matching networks. The ACPM-5017 features 5th generation of CoolPAM circuit technology which supports 3 power modes bypass, mid and high power modes. The CoolPAM is stage bypass technology enhancing PAE (power added efficiency) at low and medium power range. Active bypass feature is added to 5th generation to enhance PAE further at low output range and it enables the PA to have exceptionally low quiescent current. Without a DC-DC converter, it dramatically saves the CDG and DG09 average power consumption and accordingly extends the talk time of mobiles and prolongs a battery life. It can be used with APT (Average Power Tracking) operation to reduce the power consumption when Vcc1 is connected to the battery and Vcc2 is connected to a DC-DC converter, which adjusts the Vcc2 voltage according to the output power level. A directional coupler is integrated into the module and both coupling and isolation ports are available externally, supporting daisy chain. The integrated coupler has excellent coupler directivity, which minimizes the coupled output power variation or delivered power variation caused by the load mismatch from the antenna. The coupler directivity, or the output power variation into the mismatched load, is critical to the TRP and SAR performance of the mobile phones in real field operations as well as compliance tests for the system specifications. The ACPM-5017 has integrated on-chip Vref and on-module bias switch as the one of the key features of the CoolPAM-5, so an external constant voltage source is not required, eliminating the external LDO regulators and switches from circuit boards of mobile devices. It also makes the PA fully digital-controllable by the Ven pin that
Features
Thin Package (0.9 mm typ.) Excellent Linearity 3-mode power control with Vbp and Vmode Bypass / Mid Power Mode / High Power Mode High Efficiency at max output power 10-pin surface mounting package Internal 50 ohm matching networks for both RF input and output Integrated coupler Coupler and Isolation ports for daisy chain Green - Lead-free and RoHS compliant Compatible with APT application
Applications
LTE Band12, Band 17 Handset, Datacard
Ordering Information
Part Number
ACPM-5017-TR1 ACPM-5017-BLK
Number of Devices
1000 100
Container
178 mm (7) Tape/Reel Bulk
Description (Cont.)
simply turns the PA on and off from the digital control logic input from baseband chipsets. All of the digital control input pins such as the Ven, Vmode and Vbp are fully CMOS compatible and can operate down to the 1.35 V logic. The current consumption by digital control pins is negligible. The power amplifier is manufactured on an advanced InGaP HBT (hetero-junction Bipolar Transistor) MMIC (microwave monolithic integrated circuit) technology offering state-of-the-art reliability, temperature stability and ruggedness.
Min.
Typ.
0 3.4 2.6 2.6 2.6 25
Max.
10.0 5.0 3.3 3.3 3.3 +125
Unit
dBm V V V V C
Min.
3.2 0.5 Low High Low High Low High 0 1.35 0 1.35 0 1.35 697 -20
Typ.
3.4 0 2.6 0 2.6 0 2.6 25
Max.
4.2 3.4 0.5 3.1 0.5 3.1 0.5 3.1 716 90
Unit
V V V V V V V V MHz C
Ven
High High High Low
Vmode
Low High High Low
Vbp
Low Low High Low
Electrical Characteristics
Conditions: Vcc = 3.4 V, Ven = 2.6 V, Ta = 25 C, Zin/Zout = 50 ohm
Characteristics
Operating Frequency Range Maximum Output Power (High Power Mode) Gain
Condition
LTE MPR = 0 dB High Power Mode, Pout = 27.5 dBm Mid Power Mode, Pout = 16 dBm Bypass Mode, Pout = 6.5 dBm Bypass Mode, Pout -10 dBm
Min.
698 27.5 29 20 12
Typ.
Max.
716
Unit
MHz dBm
35 26 17 16
dB dB dB % % %
High Power Mode, Pout = 27.5 dBm Mid Power Mode, Pout = 16 dBm Bypass Mode, Pout = 6.5 dBm
High Power Mode, Pout = 27.5 dBm Mid Power Mode, Pout = 16 dBm Bypass Mode, Pout = 6.5 dBm
410 50 8 80 10 2
445 64 13 105 17 3
Quiescent Current
Enable Current
Mode Control Current Bypass Control Current Total Current in Power-down mode LTE Adjacent Channel Leakage Ratio Harmonics Suppression Input VSWR Stability (Spurious Output) Rx band Noise Power GPS Band Noise Power ISM Band Noise Power Phase Discontinuity E-UTRAACLR UTRAACLR1 UTRAACLR2 2 fo 3 fo
Mid Power Mode Bypass Mode Bypass Ven = 0 V, Vmode = 0 V, Vbp = 0 V Pout < (maximum power MPR) Pout < (maximum power MPR) Pout < (maximum power MPR) High Power Mode, Pout = 27.5 dBm VSWR 5:1, All phase 10 MHz LTE, +30 MHz offset from Tx, average +/-4.5 MHz , 20RB High Power Mode, Pout = 27.5 dBm High Power Mode, Pout = 27.5 dBm By pass mode mid power mode, at Pout = 6.5 dBm mid power mode high power mode, at Pout = 16 dBm Pout < 27.5 dBm, Pin < 10 dBm, All phase High Power Mode RF Out to CPL port ISO port to CPL port, Ven = Low 698 ~ 2620 MHz, -18 +14 -9 10:1 -20 0.3 -36 -39 -41 -39 -54 2:1 -70 -123
-22
dB dB
Footprint
All dimensions are in millimeter
0.10
1.50
Pin 1
RFOUT
ISO
VMODE
GND
VEN
CPL
Pin Description
Pin #
1 2 3 4 5
Name
Vcc1 RFin Vbp Vmode Ven
Description
DC Supply Voltage RF Input Bypass Control Mode Control PA Enable
Pin #
6 7 8 9 10
Name
CPL GND ISO RFOut Vcc2
Description
Coupling port of Coupler Ground Isolation port of Coupler RF Out DC Supply Voltage
Package Dimensions
Pin 1 Mark 1 2 3 4 5 10 9 8 7 6 0.9 0.1 3 0.1 0.5
3 0.1
All dimensions are in millimeter
Marking Specification
Pin 1 Mark
Manufacturing Part Number Lot Number P Manufacturing Info YY Manufacturing Year WW Work Week AAAAA Assemby Lot Number
Metallization
on 0.5 mm pitch 0.3 mm 0.45 0.30
0.60
0.60 0.475 0.35 0.55 0.475 connected to a inner layer through a via hole for a better isolation between CPL_IN(ISO) and RFout 1.10
C5
C7
C4
C6
C2
Dimension List
Annote
A0 B0 K0 D0 D1 P0 P1
Millimeter
3.400.10 3.400.10 1.350.10 1.550.05 1.600.10 4.000.10 8.000.10
Annote
P2 P10 E F W T
Millimeter
2.000.05 40.000.20 1.750.10 5.500.05 12.000.30 0.300.05
Reel Drawing
BACK VIEW Shading indicates thru slots 18.4 max.
178 +0.4 -0.2 25 min wide (ref) Slot for carrier tape insertion for attachment to reel hub (2 places 180 apart)
50 min.
FRONT VIEW
NOTES: 1. Reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. Avago Technologies part number c. purchase order number d. date code e. quantity of units 2. A certicate of compliance (c of c) shall be issued and accompany each shipment of product. 3. Reel must not be made with or contain ozone depleting materials. 4. All dimensions in millimeters (mm)
Note: 1. The MSL Level is marked on the MSL Label on each shipping bag.
10
25
t 25 C to Peak
Time
Sn-Pb Solder
3 C/sec max 100 C 150 C 60-120 sec
Pb-Free Solder
3 C/sec max 150 C 200 C 60-180 sec 3 C/sec max 217 C 60-150 sec 260 +0/-5 C 20-40 sec 6 C/sec max 8 min max
11
Storage Condition
Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at < 40 C and 90% relative humidity (RH) J-STD-033 p.7.
Baking
It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125 C for 12 hours J-STD-033 p.8.
CAUTION
Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking).
12
5%
10%
3 5 6 8 2 4 5 7 1 2 3 5 5 7 9 11 3 4 5 6 1 2 2 3 7 10 13 18
20%
94 124 167 231 8 10 13 17 3 4 5 7 2 3 5 7 1 1 2 4 12 19 25 32 4 5 7 9 2 3 4 5 1 1 2 2 7 13 18 26 2 3 5 6
30%
44 60 78 103 7 9 11 14 3 4 5 7 2 3 4 6 1 1 2 3 9 12 15 19 3 4 5 7 2 3 3 5 1 1 2 2 7 9 12 17 3 5 6 8 1 2 3 4
40%
32 41 53 69 6 8 10 13 2 4 5 7 2 2 4 5 1 1 2 3 58 86 148 7 9 12 15 3 4 5 6 2 2 3 4 1 1 2 2 4 5 7 9 2 3 4 6 1 1 2 3
50%
26 33 42 57 6 7 9 12 2 3 5 7 1 2 3 5 1 1 2 3 30 39 51 69 6 8 10 13 2 3 4 6 2 2 3 4 1 1 2 2 8 11 14 20 3 4 5 7 2 2 3 5 1 1 2 2
60%
16 28 36 47 6 7 9 12 2 3 4 6 1 2 3 4 1 1 2 2 22 28 37 49 5 7 9 12 2 3 4 5 1 2 3 4 1 1 2 2 17 28 5 7 10 13 2 3 4 6 1 2 3 4 1 1 2 2
70%
7 10 14 19 4 5 7 10 2 3 3 5 1 2 2 3 1 1 1 2 3 4 6 8 2 3 5 7 1 2 3 4 1 1 2 3 1 1 1 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2
80%
5 7 10 13 3 4 6 8 1 2 3 4 1 1 2 3 1 1 1 2 2 3 4 5 2 2 3 5 1 2 2 3 1 1 1 3 0.5 0.5 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2
90%
4 6 8 10 3 4 5 7 1 2 3 4 1 1 2 3 1 1 1 2 1 2 3 4 1 2 3 4 1 1 2 3 1 1 1 2 0.5 0.5 1 1 0.5 1 1 1 0.5 1 1 1 0.5 1 1 1 0.5 1 1 1 0.5 0.5 1 1
Level 3
Level 4
Level 5
Level 5a
Body 2.1 mm Thickness <3.1 mm including PLCCs (rectangular) 18-32 pin SOICs (wide body) SOICs 20 pins, PQFPs 80 pins
Level 2a
Level 3
Level 4
Level 5
Level 5a
Body Thickness <2.1 mm including SOICs <18 pin All TQFPs, TSOPs or All BGAs <1 mm body thickness
Level 2a
Level 3
Level 4
Level 5
Level 5a
35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C 35 C 30 C 25 C 20 C
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2005-2011 Avago Technologies. All rights reserved. AV02-3006EN - August 31, 2011