Latchup

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Latchup is a term used in the realm of integrated circuits (ICs) to describe a particular type of short circuit which can occur in an improperly designed circuit. More specifically it is the inadvertent creation of a lowimpedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation. The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. During a latchup when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates. The latchup does not have to happen between the power rails; it can happen at any place where the required parasitic structure exists. A spike of positive or negative voltage on an input or output pin of a digital chip, exceeding the rail voltage by more than a diode drop, is a common cause of latchup. Another cause is the supply voltage exceeding the absolute maximum rating, often from a transient spike in the power supply, leading to a breakdown of some internal junction. This frequently happens in circuits which use multiple supply voltages that do not come up in the proper order after a power-up, leading to voltages on data lines exceeding the input rating of parts that have not yet reached a nominal supply voltage.

Intrinsic BJTs in the CMOS technology

Yet another common cause of latchups is ionizing radiation which makes this a significant issue in electronic products designed for space (or very high-altitude) applications.

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1 CMOS latchup 2 Latchup prevention 3 Testing for latchup 4 See also 5 References 6 External links

[edit]CMOS

latchup

Equivalent circuit of CMOS latchup

In CMOS Technology there are a number of intrinsic Bipolar Junction transistors. In CMOS processes these transistors create problems sometimes,when the combination of n-well/p-well and substrates results in the formation of parasitic n-p-n-p structures.Triggering these thyristor-like devices leads to a shorting of the Vdd and gnd lines, usually resulting in destruction of the chip, or a system failure that can only be resolved by power-down. [1] Consider the n-well structure in the first figure. The n-p-n-p structure is formed by the source of the NMOS, the p-substrate, the n-well and the source of the PMOS. A circuit equivalent is also shown. When one of the two bipolar transistors gets forward biased (due to current flowing through the well, or substrate), it feeds the base of the other transistor. This positive feedback increases the current until the circuit fails or burns out.

[edit]Latchup

prevention

It is possible to design chips that are latchup-resistant, where a layer of insulating oxide (called a trench) surrounds both the NMOS and the PMOS transistors. This breaks the parasitic SCR structure between these

transistors. Such parts are important in the cases where the proper sequencing of power and signals cannot be guaranteed (e.g., in hot swap devices). Devices fabricated in lightly doped epitaxial layers grown on heavily doped substrates are also less susceptible to latchup. The heavily doped layer acts as a current sink where excess minority carriers can quickly recombine.[2] Another possibility for a latchup prevention is the Latchup Protection Technology circuit. When a latchup is detected, the LPT circuit shuts down the chip and holds it powered-down for a preset time. Most silicon-on-insulator devices are inherently latchup-resistant. Latchup is the low resistance connection between tub and power supply rails. Also to avoid the latch, we have to put separate tap connection for each transistor. But this will increase the size of device so fabs give a minimum space to put a tap, for example, 10u in 130nm technology.

A.2.3.3 Pseudo-NMOS Logic

Using a PMOS transistor simply as a pull-up device for an n-block as shown in Fig. A.13(c) is called pseudo-NMOS logic. A.3 Note, that this type of logic is no longer ratio-less, i.e., the transistor widths must be chosen properly, i.e., The pull-up transistor must be chosen wide enough to conduct a multiple of the n-block's leakage and narrow enough so that the n-block can still pull down the output safely: (A.21)

The advantage of pseudo-NMOS logic are its high speed (especially, in large-fan-in NOR gates) and low transistor count. On the negative side is the static power consumption of the pull-up transistor as well as the reduced output voltage swing and gain, which makes the gate more susceptible to noise. At a second glance, when pseudo-NMOS logic is combined with static CMOS in time critical signal paths only, the overall speed improvement can be substantial at the cost of only a slight increase of static-power consumption. Furthermore, when the gate of the pull-up transistor is connected to a appropriate control signal it can be turned off, i.e., pseudo-NMOS supports a power-down mode at no extra cost.