Intel® IXB8055 UTOPIA/POS

Reference Design
Hardware Validation

April 2001

Order Number: 278379-002

Revision History

Date Revision Description

3/19/01 001 First release.

4/13/01 002 Update trademark and copyright usage. No technical changes.

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ii Hardware Validation
Contents
1.0 Introduction...................................................................................................................................... 5
2.0 Validation......................................................................................................................................... 5

3.0 IX Bus Modes and Parameters........................................................................................................6

Tables
1 UTOPIA Transmit and Receive Modes and Associated Parameters ..............................................6

2 IX Bus Modes and Parameters........................................................................................................6

Hardware Validation iii

 Intel® IXB8055 UTOPIA/POS Reference Design

1.0 Introduction
This document describes the validation effort, to date, of the Intel® IXB8055 UTOPIA/POS
Reference Design RTL code package.The reference design is an RTL code package targeted for a
Xilinx* FPGA device. The reference design RTL and Xilinx silicon combination create a bridge
device that allows the connection of a single, or multiple, UTOPIA I, II or III ATM PHY device(s)
to the IXP12x0 family of network processors.

The reference design validation effort was performed on an IXP1200 evaluation board equipped
with an ATM evaluation daughter board.

The evaluation module is a single board network computer that uses a single IXP1200 Network
Processor. The evaluation module also has an onboard IXF440 Octal 10/100 Ethernet MAC. A pair
of high-speed connectors on the evaluation module allow the addition of multiple, external IX Bus
compatible MAC devices on ‘daughter board’ expansion modules. In its ‘standard issue’
configuration, the evaluation module’s IX Bus runs at 66 MHz in the 32 bit unidirectional mode.

The ATM evaluation module is a dual channel OC3/12 SONET interface card designed to enhance
the functionality of the IXP1200 evaluation module. The board was designed around the Intel®
IXB8055 UTOPIA/POS Reference Design (Xilinx) FPGA and the Intel® IXF6012/6048 ATM
Cell/Packet Interface IC, and was used as a validation vehicle for both devices.

The ATM evaluation module can be configured to allow the use of a single ATM channel at the 622
Mbps OC-12 rate or two ATM channels at the 155Mbps OC-3 rate. In its standard configuration,
the ATM evaluation module’s UTOPIA interface is clocked at a 25 MHz rate.

2.0 Validation
By using the ATM evaluation board and IXP1200 evaluation module combination, we were able to
validate many aspects of the functionality of the Intel® IXB8055 UTOPIA/POS Reference Design
RTL code. It was not the intent of the validation team to verify all of the unique modes of operation
supported by the reference design RTL code. This would require a number of different hardware
configurations that do not presently exist.

Table 1 and Table 2 list all the possible Intel® IXB8055 UTOPIA/POS Reference Design operating
modes and their validation status. As described above, there are some reference design functions
and modes of operation for which there is no current plan for validation. In Table 1and Table 2, this
is indicated by the words ‘not planned’. For some operating modes, there is a validation plan, but
they have not yet been tested. These items are indicated by the word ‘future’ in the tables.

Hardware Validation 5
Intel® IXB8055 UTOPIA/POS Reference Design

Table 1. UTOPIA Transmit and Receive Modes and Associated Parameters

Parameter Variations Validation Status

DSI (Direct Ports:

Status Indication) 1x32 mode Not Planned
mode
2x16 mode Not Planned
4x8 mode Complete
1x16+2x8 mode Not Planned
MPHY Mode 32-bit-wide Not Planned
Ports 16-bit-wide Not Planned
8-bit-wide Not Planned
Cell Size 8-bit-mode: 52 & 53 bytes Complete
16-bit-mode: 52 & 54 bytes Not Planned
32-bit-mode: 52 & 56 bytes Not Planned
Packet Size Minimum packet size: 1 byte Complete
Maximum packet size: 64KB Complete
Decode 1 cycle Complete
Response Time 2 cycles Future
Parity No parity Complete
Dual parity (odd) (2x16 or 1x16+2x8) Not Planned
Single parity; odd Complete
Single parity; even Not Planned

3.0 IX Bus Modes and Parameters

Modes and parameters on the IX Bus interface are listed in Table 2.

Table 2. IX Bus Modes and Parameters

Validation Date
Mode Variations

Cell Size 8-bit-mode: 52 & 53 bytes Complete

16-bit-mode: 52 & 54 bytes Not Planned
32-bit-mode: 52 & 56 bytes Not Planned
Packet Size Minimum packet size: 1 byte Complete
Maximum packet size: 64 KB Complete

6 Hardware Validation