Edi WN111

EDI System What's New 11.
1
Product Version 11.1 April 2012
2011-2012 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadences trademarks, contact the corporate legal department at the address shown above or call 1-800-862-4522. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. This statement grants you permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used solely for personal, informational, and noncommercial purposes; 2. The publication may not be modified in any way; 3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement; and 4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be discontinued immediately upon written notice from Cadence. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadences customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.
Contents
About This Manual

How This Document Is Organized Related Documents
EDI System Product Documentation
4
4 4
4
Release Overview
New Text Commands and Global Variables New Command Parameters Obsolete Text Commands and Global Variables
Supported in this Release
6
6 7 10
10
Obsolete Command Parameters

Supported in this Release Removed from the Software
10
11 11
Default Behavior Changes Support to On-Chip Thermal Analysis Solution is Withdrawn New and Revamped Documentation
11 12 12
New Chapter on Clock Concurrent Optimization Commands 12 New Section on Post-Mask ECO Changes from a New Verilog Netlist (Using Spare Cells Flow) 12
Foundation Flows
Defining ccoptDesign for Clock Tree Construction Defining ccopt Top and Bottom Layers Script changes for Hier Two-pass Flow
13
13 13 14
EDI System Display and Tools
15
New Buttons in the Design Browser 15 Option for Reading Net Names File in the Select/Delete/Deselect Routes Form 15 Option for Saving Highlight Settings 16 Option To Specify Stream Map File in Verify Litho Form 17 Enhanced Snapping Capability in the Ruler 17 Option for Customizing DPT Colors 17 Support for Net Name Display 18 Save Foundation Flow Files 19
Importing and Exporting the Design

Technology Section Ignored for Subsequent LEF File
20
20
LEF-DEF Properties
21
LEF 5.8 Properties for Creating New DRC Rules for 32-28 nm and Smaller
Nodes
Cut Layer Enhancements Routing Layer Enhancements Macro Enhancements
21
21 22 24
Flip Chip
25
Bump Placement Enhanced To Check Overlapping Based on Real Geometry 25 findPinPortNumber Enhanced To Report Port Number for IO Cells 26 viewBumpConnection Enhanced To Automatically Redraw Flightlines after Bump Manipulation 27
Netlist Verilog
28
New Global Variable To Ignore Non-fatal Verilog Netlist Errors 28 setDoAssign Exclusion File Enhanced To Support Bus Names without Qualifiers 28
Netlist-to-Netlist
runN2NOpt Enhanced To Support Semiauto Mode
29
29
Partitioning
DPT Colorizer Support editPin Command Enhanced Enhanced Pin QoR for Multi-Partition Nets Incremental assembleDesign Capability Enhanced insertPtnFeedthrough Command Enhanced New Clone Place Menu Command New Commands for Setting Pin Assignment Mode Support for Wildcards in Net Name
30
30 30 31 31 31 32 32 32
Floorplanning
createPlaceBlockage Command Enhanced Enhanced Support for High Effort planDesign flipOrRotateObject Command Enhanced Floorplan Toolbox Enhanced Plan Design GUI Form Enhanced Specify Floorplan GUI Form Enhanced Support for Adding Named Prefixes to Blockages Support for Aligning Objects of Mixed Type Support for Shifting SDP Groups
34
34 34 35 35 36 37 38 39 39
Multiple Supply Voltage (MSV)

New Option for addPowerSwitch
40
40
NanoRoute Router
Enhanced NanoRoute Reporting
41
41
Metal Fill and Via Fill

New trimMetalFill Parameter To Support Non-Default Spacing
42
42
Metal Fill Enhanced To Honor Non-default Rule Hardspacing trimMetalFillNearNet -createFillBlockage Now Supports Custom Names New trimMetalFillNearNet Parameter To Remove Metal Fill Near Critical Nets addMetalFill Now Supports Check Board Vias addMetalFill Enhanced To Allow User-specified List of Critical Nets in Timing-aware Mode setMetalFill -diagOffset Now Supports 0 Value
42 42 42 42 43 43
Timing Budgeting
45
Added Global Variables 45 justifyBudget Enhanced to Honor report_timing_format Global Variable 45 New Command to Reset Modified Budget 45
RC Extraction
47
preRoute Extraction Enhanced to Support height_over Construct in the ICT or QRC Technology File 47 RC Extraction Mode GUI Enhanced for Specifying Standalone Signoff QRC Settings 47 Support for Selecting SPEF par_value Triplet Field and Assigning to Corresponding RC Corner 48
Timing
Reporting Enhancements
report_property/get_property Supports Power and Ground Pins Added New Global to Report Constant Mismatch
50
50
50 50
Timing Library Enhancements

Added New Command to Check Library Database Version Added New Global to Derive Capacitance Range Ability to Read Library Without ECSM Data Added New Global to Disable ECSM Sensitivity Data
50
50 51 51 51
SSTA Enhancements
Ability to Report Sensitivity Details of Process Parameters
51
51
Other Enhancements
Added New Parameters to MMMC RC Corner Commands Added New Global to Use Clock Slew for Check Arcs Ability to Reset/Update MMMC Data By Default Added New write_sdf Parameters
51
51 51 52 52
Default Behavior Changes in Timing

report_timing -not_through Parameter Default Behavior Change
52
52
Timing Debug
Timing Debug Paths Now Nested Trees
54
54
Verification
Enhanced Verify AC Limit Form Enhanced Verify Cut Density Form Enhanced Verify Metal Density Form
55
55 56 57
Enhanced Verify Power Via Form 58 Enhanced Verify Routing Constraints Form 59 New Verify Geometry Option To Report Out-of-die Objects 60 Support for Rectangular Edges 60 Enhanced Verify Geometry Support for LEF Properties 61 verifyGeometry -noMinSpacing Enhanced To Ignore All Spacing Rule Checks 61 verifyACLimit Enhanced To Perform Peak and Average Current Analysis Yield Analysis 6361
Power Calculation
Annotation Summary Reporting Enhancements Enhanced Register Gating Efficiency Reporting New Parameter to Control Output of Clock Gates Previously Supported but not Documented Parameter Added to Documentation
64
64 65 65 65
Rail Analysis
auto_fetch_dc_sources Command Enhanced New Parameter to Support User-Specified Technology File Resistance Extraction for T/L Junctions set_power_data -instance Command Parameter Enhanced to Honor format ascii Parameter set_rail_analysis_mode -power_up_fast_mode Parameter Default Behavior Changed Support for Decoupling Capacitance Static Violation GIF Plot Support for Embedded Bumps in Hierarchical TSV Designs
67
67 67 68 68 68 68 68
Early Rail Analysis

Auto Trace Function for Switched Nets Supported New Parameters to Control Virtual Followpin Generation
70
70 70
Mixed-Signal Interoperability
GUI Updates New Commands Added
71
71 71
Clock Concurrent Optimization Clock Tree Synthesis
73 74
New Parameter Added to Size Up Gating Components to Maximum 74 setCTSmode -routeClkNet Enhanced to Route Clock Nets after Synthesis or Optimization 74
OpenAccess
New Beta Control Variable New Global to Specify a Constraint Group Name
75
75 75
TSV
76
New Option Added to the Create TSV/Bump Form New Options Added to the Assign TSV/Bump Form
76 76
Power Planning
New Option for setAddStripeMode
77
77
ECO Flows
New Flow Added to Make Late Logic Changes
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78
EDI System What's New 11.1, 11.1
1
About This Manual
This manual provides information about Product Version 11 the Cadence Encounter Digital Implementation System family of products. The Encounter Digital Implementation System (EDI System) family encompasses the following products: Encounter Digital Implementation System L Encounter Digital Implementation System XL NanoRoute Ultra SoC Routing Solution Virtuoso Digital Implementation Encounter Timing System L Encounter Timing System XL Encounter Power System L Encounter Power System XL First Encounter L First Encounter XL First Encounter GXL
How This Document Is Organized

This What's New manual is organized into chapters that cover broad areas of EDI System software functionality. Each chapter contains topics that may address one or more of the following areas: New functionality in the EDI System software and enhancements made to existing forms and commands to support a new feature. Changes in default behavior, name changes to existing commands and forms, and syntax changes. Features that were removed since version 10 of the software. Major documentation changes, such as a new chapter or substantial reorganization.
Related Documents
For more information about the EDI System family of products, see the following documents. You can access these and other Cadence documents with the Cadence Help documentation system.
EDI System Product Documentation

EDI System Known Problems and Solutions Describes important Cadence Change Requests (CCRs) for the EDI System family of products, including solutions for working around known problems. EDI System User Guide Describes how to install and configure the EDI System software, and provides strategies for implementing digital integrated circuits.
April 2012 8 Product Version 11.1
EDI System Text Command Reference Describes the EDI System text commands, including syntax and examples. EDI System Menu Reference Provides information specific to the forms and commands available from the EDI System graphical user interface. EDI System Database Access Command Reference Lists all of the EDI System database access commands and provides a brief description of syntax and usage. EDI System Foundation Flows User Guide Describes how to use the scripts that represent the recommended implementation flows for digital timing closure with the EDI System software. EDI System Library Development Guide Describes library development guidelines for the independent tools that make up the EDI System family of products. README file Contains installation, compatibility, and other prerequisite information, including a list of Cadence Change Requests (CCRs) that were resolved in this release. You can read this file online at downloads.cadence.com.
April 2012
Product Version 11.1
2
Release Overview
New Text Commands and Global Variables New Command Parameters Obsolete Text Commands and Global Variables Obsolete Command Parameters Default Behavior Changes Support to On-Chip Thermal Analysis Solution is Withdrawn New and Revamped Documentation
New Text Commands and Global Variables

The following table lists the commands that were added to the EDI System software. The second column identifies the chapter of the EDI System Text Command Reference where the command is documented. New Commands and Globals ccoptDesign check_ldb_version fpgDefaultBlockageNamePrefix generateCCOptRCFactor getCCOptMode getPinAssignMode init_oa_default_rule resetModifiedBudget setCCOptMode setPinAssignMode spgM3StripePushDown spgM3StripeShrink
April 2012 10
Chapter Clock Concurrent Optimization Commands Timing Analysis Commands Floorplan Commands and Global Variables Clock Concurrent Optimization Commands Clock Concurrent Optimization Commands Partition Commands and Global Variables Import and Export Commands and Global Variables Timing Budgeting Commands and Global Variables Clock Concurrent Optimization Commands Partition Commands and Global Variables Placement Commands and Global Variables Placement Commands and Global
Variables tbgConsolidateTrialNoTrialIPO tbgCorrelateMaxTranWithActualTran timing_enable_case_analysis_conflict_warning timing_library_infer_cap_range_from_ccs_receiver_model timing_path_based_use_min_max_clock_slew_for_check timing_read_library_without_ecsm timing_read_library_without_sensitivity timing_ssta_report_endpoint_description vl_tolerate_illegal_syntax Timing Budgeting Commands and Global Variables Timing Budgeting Commands and Global Variables Timing Global Variables Timing Global Variables Timing Global Variables Timing Global Variables Timing Global Variables Timing Global Variables Import and Export Commands and Global Variables
New Command Parameters

The following table lists the parameters that were added to the EDI System software. The second column identifies the chapter of the EDI System Text Command Reference where the command is documented. New Parameters addPowerSwitch -netPrefix auto_fetch_dc_sources -region -region_pitch -layer ckSynthesis -substituteValidCell create_delay_corner -early_rc_corner -late_rc_corner
Chapter Low Power Commands
Rail Analysis Commands
Clock Tree Synthesis Commands
Timing Analysis Commands
createPlaceBlockage -noCoreByCut -prefixOn createRouteBlk -prefixOn findPinPortNumber -cellName run_vsr -share_shields
Floorplan Commands and Global Variables
Floorplan Commands and Global Variables
Flip Chip Commands and Global Variables
Mixed-Signal Commands
-no_taper_to_pinwidth runN2NOpt -floorplanOnly setAddStripeMode -stripe_min_width -trim_stripe setVerifyGeometryMode -boundaryHalo setCTSMode -synthUpsizeClockGate set_default_switching_activity -clock_gates_output_ratio set_power_analysis_mode -compatible_internal_power
Netlist-to-Netlist Command
Power Planning
Verify Commands
Clock Tree Synthesis Commands
Power Calculation Commands
Power Calculation Commands
setPlaceMode -groupFlopToMacroLevel -groupFlopToMacroList set_rail_analysis_mode -extraction_tech_file setIntegRouteConstraint -shieldWidth
Placement Commands and Global Variables
Rail Analysis Commands
Mixed-Signal Commands
-shieldGap
-tandemWidth
-groupToOutsideSpacing spefIn -early_rc_corner -early_spef_field -late_rc_corner -late_spef_field -spef_field streamOut -attachNetProp trimMetalFill -useNonDefaultSpacing
RC Extraction Commands
Import and Export Commands and Global Variables
Metal and Via Fill Commands and Global Variables
trimMetalFillNearNet -remove update_delay_corner -early_rc_corner -late_rc_corner verifyACLimit -avgRecovery -deltaTemp -method -minPeakDutyRatio -minPeakFreq -useQrcTech -scaleCurrent verifyPowerVia -stackedVia writeDieAbstract -noFilter write_sdf -exclude_whatif_arcs -target_application
Metal and Via Fill Commands and Global Variables
Verify Commands
Verify Commands
TSV Commands
Obsolete Text Commands and Global Variables

The following obsolete text commands and global variables will continue to be supported in this release, but will be removed in the next major release of the software. reportYield This command is not being replaced.
Obsolete Command Parameters


The following obsolete text command parameters will continue to be supported in this release, but will be removed in the next major release of the software. -lowest_layer The -lowest_layer parameter of the auto_fetch_dc_sources command has been replaced by layer. -clock_gates_output The -clock_gates_output parameter of the set_default_switching_activity command has been replaced by -clock_gates_output_ratio.
Removed from the Software

The following obsolete text command parameters have been removed from the software. getPlanDesignMode and setPlanDesignMode -abSpacingX -abSpacingY -exclusiveSpacing -maxDistToGuide -spacingX -spacingY These parameters are not being replaced.
Default Behavior Changes

The following list briefly describes changes in default behavior that take effect in this release. Note: Each description in this list is also the section in the What's New where you can find more detailed information on the specific behavior change. Chapter Verification Clock Tree Synthesis Timing Analysis
April 2012
Default Behavior Change verifyGeometry -noMinSpacing Enhanced To Ignore All Spacing Rule Checks setCTSmode -routeClkNet Enhanced to Route Clock Nets after Synthesis or Optimization report_timing -not_through Parameter Default Behavior Change
15 Product Version 11.1
Commands Rail Analysis Resistance Extraction for T/L Junctions
Support to On-Chip Thermal Analysis Solution is Withdrawn

With this release, the support to on-chip thermal analysis solution is being withdrawn.
New and Revamped Documentation
New Chapter on Clock Concurrent Optimization Commands

The EDI System Text Command Reference now contains a new chapter on Clock Concurrent Optimization (CCOpt). This chapter describes the CCOpt commands used to run this flow. For more information, see the Clock Concurrent Optimization Commands chapter of the Text Command Reference.
New Section on Post-Mask ECO Changes from a New Verilog Netlist (Using Spare Cells Flow)
The ECO Flows appendix of EDI System User Guide now contains a new section on post-mask ECO changes from a new Verilog netlist, using spare cells flow. For more information, see Post-Mask ECO Changes from a New Verilog Netlist (Using Spare Cells Flow).
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3
Foundation Flows
Defining ccoptDesign for Clock Tree Construction Defining ccopt Top and Bottom Layers Script changes for Hier Two-pass Flow
Defining ccoptDesign for Clock Tree Construction

The following vars are used for defining ccoptDesign for Clock Tree Construction.
Variable Name cts_inverter_cells cts_buffer_cells clock_gate_cells cts_use_inverters update_io_latency cts_target_skew cts_target_slew cts_io_opt cts_effort
Value Type list list list boolean boolean float float enum enum
Usage Description Specify the CTS inverter cells Specify the CTS buffer cells Specify the clock gate cells Specify true or false Specify true or false Specify the skew Specify the slew Specify on | off | secondary Specify low | medium | high
Defining ccopt Top and Bottom Layers

The following vars define top and bottom layers for clock tree and leaf nets, non default rules, and clock shielding net (ccopt only).
Variable Name clk_tree_top_layer

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Value Type string
Usage Description Specify setCTSMode | setCCoptMode

17 Product Version 11.1
clk_tree_bottom_layer clk_leaf_top_layer clk_leaf_bottom_layer clk_tree_ndr clk_leaf_ndr clk_tree_shield_net
string string string string string string
Specify setCTSMode | setCCoptMode Specify setCTSMode | setCCoptMode Specify setCTSMode | setCCoptMode Specify setCTSMode | setCCoptMode Specify setCTSMode | setCCoptMode Specify setCTSMode | setCCoptMode
Script changes for Hier Two-pass Flow

The Hierarchical Two Pass flow can now be enabled using: set vars(hier_flow_type) 2pass For execution, It produces two makefiles: For partition-CTS: Makefile.pass1 For rebudget-assembly: Makefile.pass2 Note: For simpler inter-partition timing flows, you can use the hierarchical one-pass flow, which utilizes a single iteration of top-level budgeting.
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4
EDI System Display and Tools
New Buttons in the Design Browser Option for Reading Net Names File in the Select/Delete/Deselect Routes Form Option for Saving Highlight Settings Option To Specify Stream Map File in Verify Litho Form Enhanced Snapping Capability in the Ruler Option for Customizing DPT Colors Support for Net Name Display Save Foundation Flow Files
New Buttons in the Design Browser

The following buttons have been added to the Design Browser to improve usability: Clear : Use the Clear button to clear any existing text string in the text input field. Top Page : Use the new Top Page button in the Design Browser to return to the top of the design quickly. In previous releases, you had to click the Previous Page button several times or restart the browser to return to the top of the design.
Option for Reading Net Names File in the Select/Delete/Deselect Routes Form

This release makes it easier for you to specify net names in the Select/Delete/Deselect Routes form. Earlier, you had to enter net names in the Nets input box on the form manually. This was quite tedious if you wanted to specify several nets. Now, you can use the new Read Nets button on the form to read in an ASCII file, which comprises a list of net names, as the input.
Option for Saving Highlight Settings

The following buttons have been added to the Edit Highlight Color form to enable you to save and reload custom highlight settings: Save : Saves highlight settings. Use this button after you have customized the highlight sets in some way. Load : Loads highlight settings that have been previously saved in a file. Default : Reverts to the default settings for all highlight sets.
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Option To Specify Stream Map File in Verify Litho Form

To improve usability, the GUI equivalent of an additional verifyLitho parameter has been added to the Routing Layers page on the Verify Litho form: Stream Map : Specifies the name and path of the stream out map file, which maps the GDS stream to the layers in the EDI System database. This option is equivalent to using verifyLitho mapFile filename.
Note: The GDS layer numbers in the stream out layer map should match the numbers in the LPA layer map.
Enhanced Snapping Capability in the Ruler

In this release, the ruler in EDI System has been enhanced to snap to any type of edge, not just horizontal or vertical edges. This enhancement makes it easier for you to measure the diagonal distance between octagonal bumps in flip chip designs as the ruler can now snap to 45-degree edges as well.
Option for Customizing DPT Colors

In this release, Double Pattern Technology (DPT) display has been enhanced to show different boundary
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patterns for different colors. In addition, you can now customize the DPT colors by using the Double Pattern option on the View-Only page of the Color Preferences form.
Support for Net Name Display

In this release, the tool has been enhanced to support the display of net names in the design area.
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Save Foundation Flow Files

The Save Testcase form provides a new Check-box to save Foundation Flow Files. The form can be accessed from the EDI System graphical user interface File - Save - Testcase. Check the box to save foundation flow files.
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5
Importing and Exporting the Design

In previous releases, when a LEF file was read during the design import process, the EDI system showed an error if some of the layers were not defined in the first technology LEF file. In this release, the system ignores definitions of new LEF LAYERs after the first technology file is read for the design. Now, by default the EDI system issues a warning and ignores the layers that are not defined in the first technology LEF file.
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6
LEF-DEF Properties
LEF 5.8 Properties for Creating New DRC Rules for 32-28 nm and Smaller Nodes
LEF 5.8 Properties for Creating New DRC Rules for 32-28 nm and Smaller Nodes
Cut Layer Enhancements
You can define new CUT LAYER properties to create rules for cut layers that: Add FORBIDDENSPACING rule, to indicate that if the spacing between two cuts belonging to a class name is greater than or equal to the specified minimum spacing and less than or equal to the specified maximum spacing, then there will be a violation.
Add PARALLEL to cut layer ENCLOSURE rules, to indicate that the enclosure values must be fulfilled, but not other ENCLOSURE statements, if the wire containing a cut has a neighbor wire less the defined parallel within value and has a common parallel run length to the cut greater than or equal to the specified parallel length on only one side.
Add MINSUM in cut layer ENCLOSURETABLE rules, to indicate that it is legal if two opposite sides have overhang values greater than or equal to the sum of the specified overhangs, and the smaller overhang value is greater than or equal to the specified smaller overhangs.
Add NONZEROENCLOSURE to CUTCLASS SPACINGTABLE rules, to indicate that the inter-layer cut spacing between cuts in the current layer to cuts in the specified second layer only applies to cut edges with enclosure on the above metal layer of the cuts in the current layer greater than zero and have parallel run length greater than 0 with the cuts in the second layer.
Add EOLMINLENGTH to ENCLOSURETOJOINT rules, to indicate that the joint must not be a EOL edge with length greater than or equal to the specified minimum length along both sides, and the length of the EOL edge is no longer necessarily equal to the wire width.
Add the following keywords in cut layer SPACING rules: EXTENSION: Specifies that the given extension should be extended on the cut edges, that do not fulfill the overhang value defined in the ENCLOSUREEDGE OPPOSITE rule, before the specified cut spacing is applied between the extended edges to a metal in the second layer.
NONEOLCONVEXCORNER: Specifies the spacing of a cut to a convex corner that does not touch a EOL edge with width less than the specified EOL width of a metal shape containing the cut in the form of a triangle formed by the smaller edge length or the specified cut spacing. ABOVEWIDTH: Specifies that the cut to different-net metal spacing only applies on the above metal layer wire with width greater than or equal to the specified width. MASKOVERLAP: Specifies the cut to metal containing the cut spacing on the overlap area of two different masks.
Add the following in cut layer EOLENCLOSURE rules: ABOVE/BELOW: Specifies that the EOL enclosure rule only applies on the above or below routing layer. PARALLELEDGE: Indicates that the EOL enclosure rule only applies if there is a parallel edge on one side that is less than the specified parallel space length. MINLENGTH: Indicates that the EOL enclosure only applies if EOL edge has length greater than or equal to the specified minimum length along both sides.
Other cut layer enhancements include: Enhanced CUTCLASS SPACINGTABLE Rule The number of possible inter-layer CUTCLASS SPACINGTABLE rules has been increased from two to three. Now you can specify up to three additional tables for intercut layer spacing - one with SAMENET, one with SAMEMETAL, and one with neither of them. Earlier, you could specify up to two cut class SPACINGTABLE rules. For more information, see Defining Cut Layer Properties to Create 32/28 nm and Smaller Nodes Rules in the "LEF Syntax" chapter of the LEF/DEF Language Reference Guide.
Routing Layer Enhancements

You can define new ROUTING LAYER properties to create rules for routing layers that: Add FORBIDDENSPACING rule: To indicate that if the spacing between the right/left or top/bottom edge of a wire with width less than the specified maximum width to the right/left or top/bottom of another wire is greater than or equal to the specified minimum spacing and less than or equal to the specified maximum spacing with parallel run length greater than the specified PRL value, then it will be a violation if there is a different-metal polygon wire between the two wires. To indicate that it will be a violation if two wires are at a certain distance apart that is greater than or equal to the specified minimum spacing and less than or equal to the maximum spacing and are within a specified distance from a wire having a width greater than or equal to the specified minimum width and has a parallel run length greater than the PRL value.
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Add WIDTH in routing layer FORBIDDENSPACING rule, to indicate that it will be a violation if two wires are at a certain distance apart that is greater than or equal to the specified minimum spacing and less than or equal to the maximum spacing and are within a specified distance from a wire having a width greater than or equal to the specified minimum width and has a parallel run length greater than the PRL value.
Add NONEOLCORNERONLY in PARALLELEDGE in routing layer SPACING ENDOFLINE rule, to indicate that the parallel edge neighbor wire must contain a corner that does not belong to another EOL edge.
Add WIDTH in SPACING NOTCHLENGTH to routing layer SPACING rules, to indicate that the minimum notch length spacing only applies if the width of a single side of the notch is greater than or equal to the specified notch width of the side.
Add CONCAVECORNER in MINADJACENTLENGTH in routing layer MINSTEP rules, to indicate that if a concave corner is between two convex corners, and if one of the length of the edges to form the concave corner is less than the specified minimum adjacent length, then the length of the other edge must be greater than or equal to the specified minimum step length.
Add the following keywords to routing layer SPACINGTABLE rules: SAMEMASK: Specifies that the spacing(s) only apply to objects that belong to the same mask. EXCEPTWITHIN in WIDTH: Specifies that any wire that is at a distance greater than or equal to the specified low exclude spacing and less than the high exclude spacing away from the wide wire must be ignored.
Add the following new keywords in WRONGDIRECTION to routing layer SPACING rules: PRL: Indicates that the wrong direction spacing is only applied if long/side edges of two wires have common parallel run length greater than the specified PRL value. LENGTH: Specifies that the wrong direction spacing is switched to apply to the short/end edges if the length of both the wires is less than or equal to the specified length.
Other routing layer enhancements include: Enhanced LENGTH in Routing Layer PROTRUSIONWIDTH Rule If the given value of LENGTH in PROTRUSIONWIDTH is zero, then the length of the protrusion wire is irrelevant. In this case, the width of the protrusion wire should always be checked independent of the length of the wire. For more information, see Defining Routing Layer Properties to Create 32/28 nm and Smaller Nodes Rules in the "LEF Syntax" chapter of the LEF/DEF Language Reference Guide.
Macro Enhancements
You can define new MACRO properties to create rules for macros that: Add CELLROW in EDGETYPE rule, to indicate which cell row the edge type is defined on for multiple height cells. In addition, the EDGETYPE rule has been enhanced to define multiple edge types on an edge, including single height cells, such that different type of constraints can be defined on an edge. For more information, see Macro in the "LEF Syntax" chapter of the LEF/DEF Language Reference Guide.
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7
Flip Chip
Bump Placement Enhanced To Check Overlapping Based on Real Geometry findPinPortNumber Enhanced To Report Port Number for IO Cells viewBumpConnection Enhanced To Automatically Redraw Flightlines after Bump Manipulation
Bump Placement Enhanced To Check Overlapping Based on Real Geometry

In previous releases, overlapping of bumps was checked on the basis of their rectangular cell frames during bump placement and manipulation. This meant that for rectilinear bumps, ciopCreateBump would not allow bumps to be placed together if their cell frames overlapped even if there was no overlap in their real geometry. In this release, bump placement has been enhanced to check overlapping based on the real geometry of the bumps instead of their rectangular cell frames. As a result, bump placement is now more area efficient because bumps can be placed closer together.
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findPinPortNumber Enhanced To Report Port Number for IO Cells

This release makes the usage of findPinPortNumber more flexible as you can now find the pin port number of the instance of the specified cell using the new -cellName parameter. The -cellName parameter cannot be used with the existing -instName parameter, which is used to find the pin port number of the specified instance. Additionally, findPinPortNumber has been enhanced to return a list of suitable port numbers as a Tcl list. This means you can now use set result [findPinPortNumber] or catch {findPinPortNumber} result to get the result. For example, the command findPinPortNumber -instName IOPADS_INST/esd* -pinName VDD may return the following port number string as result: IOPADS_INST/esd:VDD:1 IOPADS_INST/esd1:VDD:1
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viewBumpConnection Enhanced To Automatically Redraw Flightlines after Bump Manipulation

In flip chip designs, flightlines are used extensively to interact with the design. You can display flip chip related flightlines using viewBumpConnection. This release makes flightline usage more user friendly by enhancing viewBumpConnection to automatically redraw flightlines after bump manipulation. Specifically, flightlines are now redrawn after the following actions: Bump assignments are swapped using swapSignal: Flightlines of the selected bumps are swapped to reflect the manipulation. Bumps are unassigned using unassignBump: Flightlines of specified bumps are removed. A bump/IO pad is moved: Flightlines are redrawn to reflect the new location. An instance is deleted from the floorplan area using deleteSelectedFromFPlan: Flightlines of that instance are also removed.
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8
Netlist Verilog
New Global Variable To Ignore Non-fatal Verilog Netlist Errors setDoAssign Exclusion File Enhanced To Support Bus Names without Qualifiers
New Global Variable To Ignore Non-fatal Verilog Netlist Errors

During design import, the software, by default, issues an error and quits when it detects netlist errors such as port mismatches. However, in a live design environment, you may want to view the physical data in the layout even though the design is not in a perfect state. In such cases, you will want to proceed despite the netlist errors. A new feature of this release is that you can use the new vl_tolerate_illegal_syntax global variable to ignore non-fatal Verilog netlist errors during design import. If you set this variable to 1, the software displays the following warning but continues with the design import: **WARN: (ENCSYC-1975): Encounter will try to proceed in the presence of Verilog netlist errors because vl_tolerate_illegal_syntax is set to non-zero by the user for prototyping. Carefully examine and resolve all unexpected errors. Then proceed with caution. Note: Although you can use vl_tolerate_illegal_syntax to enable the software to read a Verilog netlist with invalid syntax, Cadence strongly advises you to resolve netlist errors before proceeding.
setDoAssign Exclusion File Enhanced To Support Bus Names without Qualifiers

This release makes it easier for you to specify assign nets and buses that are not to be replaced with a userspecified assign buffer. The setDoAssign exclusion file has been enhanced to accept bus names without a qualifying range. If the bus name is specified without a qualifier, setDoAssign -excNetFile treats it the same way as a bus name with a full range. For example, the following two entries are treated as equivalent: module N3TSBASTA adrs_map_adrs_900 module N3TSBASTA adrs_map_adrs_900 [0:899]
April 2012
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Netlist-to-Netlist
runN2NOpt Enhanced To Support Semiauto Mode
In this release, the runN2NOpt command has been enhanced to support the semiauto mode to import or export data from or to EDI System and allow you to execute a script in between. In previous releases, you could run the command only either completely automatically (default auto mode) or completely customized (custom mode). The new semiauto mode now allows you to use a custom script while using the standard EDI System interface flow as in auto mode. Additionally, you can use the new -floorplanOnly parameter to save and reload only the floorplan in the semiauto mode.
April 2012
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Partitioning
DPT Colorizer Support editPin Command Enhanced Enhanced Pin QoR for Multi-Partition Nets Incremental assembleDesign Capability Enhanced insertPtnFeedthrough Command Enhanced New Clone Place Menu Command New Commands for Setting Pin Assignment Mode Support for Wildcards in Net Name
DPT Colorizer Support

The colorizer support has been added in the 20nm partitioning and pin assignment domain to track Double Pattern Technology. If the color of the first track is undefined, then red color is assigned to the first track. The colorizer support helps to identify if a design has double patterning or not by checking tracks, signal and regular wires and vias.
editPin Command Enhanced

In this release, the editPin command has been enhanced to simplify the pin-attribute manipulation. Changes have been made to the following parameters to support this enhancement: spreadType Specifies how to spread pins along a block's edges. This parameter is now optional. However, the results of pin updation will take into account values of other options (default or specified by user). For example, if fixOverlap is set as 1 and after updation the pin is not legal, then it will traverse the partition periphery according to spreadDirection and find the closest legal location. layer Specifies the layer on which the pins will be assigned. This parameter is now optional but only when spreadType is not specified. The updated syntax of the editPin command is as follows:
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Enhanced Pin QoR for Multi-Partition Nets

Earlier, for multi-partition nets, pin assignment tried to align the pair of pins near the routing cross-point. In this release, pin assignment tries to minimize the distance from the source pin to the sink pins. Additionally, the reportUnalignedNets command has been enhanced to measure the average misalignment with standard deviation for multi-partition nets. reportUnalignedNets -ptnToPtn multiFanout -topToPtn multiFanout -statistics multiFanout.rpt This is helpful in measuring the QoR of multi-partition nets.
Incremental assembleDesign Capability Enhanced

In the previous release, the partition command had to be used in order to call the incremental design of a block again. With enhancements in this release, you can call the incremental assembleDesign multiple times in a session without partitioning the block.
insertPtnFeedthrough Command Enhanced

In the previous release, the -noBuffer parameter of the insertPtnFeedthrough command could not be used on a design that had master-clone partitions. With enhancements in this release, this limitation has been addressed and the insertPtnFeedthrough -noBuffer command now supports master-clone feedthrough insertions.
New Clone Place Menu Command

In this release, the Clone Place menu command has been added to the Partition menu. You can now use the Clone Place menu command to place all clone instances with location and orientation relative to the master partition instances. It adjusts the instance orientation based on the clone orientation. Alternatively, you can use the clonePlace command.
New Commands for Setting Pin Assignment Mode

You can now use the setPinAssignMode command to set the global parameters of the partition or block pin assignment feature. Parameters specified with the setPinAssignMode command are used whenever you run pin-related commands. You can use the new getPinAssignMode command to return the information about setPinAssignMode parameters in the log file and in the console.
Support for Wildcards in Net Name

In this release, the createNetGroup and addNetToNetGroup commands have been enhanced to support wildcards while specifying the net names using the -net parameter. This enhancement makes it easier for you to select multiple nets with a common prefix or suffix.
April 2012
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Floorplanning
createPlaceBlockage Command Enhanced Enhanced Support for High Effort planDesign flipOrRotateObject Command Enhanced Floorplan Toolbox Enhanced Plan Design GUI Form Enhanced Specify Floorplan GUI Form Enhanced Support for Adding Named Prefixes to Blockages Support for Aligning Objects of Mixed Type Support for Shifting SDP Groups
createPlaceBlockage Command Enhanced

You can now use the -noCutByCore parameter of the createPlaceBlockage command to specify that the placement blockages should not be cut by row area in the core. The -noCutByCore parameter allows creation of placement blockages that overlap the core boundary and the IO ring area.
Enhanced Support for High Effort planDesign

In this release, high effort planDesign (setPlanDesignMode -effort high) has been enhanced to fully support VERSION 1.0 of the constraint file format, including the following: For seed selection and auto fence creation, it honors the user-specified utilization and the min/max aspect ratio constraints. For auto fence creation and macro placement, it honors all the spacing constraints specified in the constraint file. For details of the constraint file, see Automatic Floorplan Synthesis Constraint File Format. As a result of the new constraints and options added for high effort flow, the following spacing options for medium effort planDesign have been removed from the setPlanDesignMode and getPlanDesignMode commands: -abSpacingX -abSpacingY -exclusiveSpacing -maxDistToGuide -spacingX -spacingY
flipOrRotateObject Command Enhanced

The flipOrRotateObject command has now been enhanced to flip or rotate objects that can be modules, groups, placement blockage, routing blockage, hard macros, special routings, and special vias (including 45 degree) and special wires.
Floorplan Toolbox Enhanced

In this release, the Floorplan Toolbox had been enhanced to add the Set Placement Status button. You can now use the Set Placement Status button on the Floorplan Toolbox to access the Set Placement Status form directly which you can use to change the placement status for either all or selected instances. Alternatively, you can access the Set Placement Status form by choosing Floorplan Edit Floorplan Set Instance Placement Status.
April 2012
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Plan Design GUI Form Enhanced

In this release, the setPlanDesignMode page of the Plan Design form, which is used to set the Automatic Floorplan Synthesis global parameters, has been enhanced to provide options that match the setPlanDesignMode command. The newly added GUI options are highlighted below:
Specify Floorplan GUI Form Enhanced

In this release, the Specify Floorplan Advanced form, which is used to specify the standard cell rows and bottom I/O pad orientation, has been enhanced to provide options that match the floorplan command.
The newly added GUI options are highlighted below:
Support for Adding Named Prefixes to Blockages

Since some routing or placement blockages are valid only for certain steps while other blockages should be maintained throughout, enchancements have been made in this release to allow the user to name routing or placement blockages with prefixes. These prefixed blockages can then be easily identified and removed in different flow steps. To accomodate this enhancement, -prefixOn parameter has been added to the createPlaceBlockage and createRouteBlk commands. Additionally, the fpgDefaultBlockageNamePrefix global variable has been added that you can use to set the prefix name for routing and placement blockages.
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Support for Aligning Objects of Mixed Type

Previously, the alignObject command did not align selected objects or mixed type. For example, if the selected objects contained an instance and a blockage, they were not aligned. However, with enhancements in this release, selected objects of mixed type can be aligned.
Support for Shifting SDP Groups

In the previous release, the shiftObject command was used to shift instances, modules, groups, placement blockage, routing blockage, hard macros, special routings, and I/O pins vertically or horizontally by a specified distance. In this release, the shiftObject command has been enhanced to support the shifting of Structured Data Path (SDP) groups as well. This capability is also accessible through the Floorplan Toolbox.
April 2012
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Multiple Supply Voltage (MSV)

With this release, a new option -netPrefix has been added to the command addPowerSwitch. The option adds a prefix to power switch enable nets.
April 2012
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NanoRoute Router

With enhancements in this release, the number of nets that were not routed due to the existence of mixed signal constraints is reported in the log file using the NanoRoute Router.
April 2012
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Metal Fill and Via Fill
New trimMetalFill Parameter To Support Non-Default Spacing Metal Fill Enhanced To Honor Non-default Rule Hardspacing trimMetalFillNearNet -createFillBlockage Now Supports Custom Names New trimMetalFillNearNet Parameter To Remove Metal Fill Near Critical Nets addMetalFill Now Supports Check Board Vias addMetalFill Enhanced To Allow User-specified List of Critical Nets in Timing-aware Mode setMetalFill -diagOffset Now Supports 0 Value
New trimMetalFill Parameter To Support Non-Default Spacing

In this release, the trimMetalFill command has been enhanced to support non-default spacing. Some critical nets use a non-default rule (NDR) for routing as they may need to have wider wires or wider spacing than other nets. The new -useNonDefaultSpacing parameter enables you to use non-default spacing while trimming metal fill. Use this parameter to extend NDR control to trimming metal fill.
Metal Fill Enhanced To Honor Non-default Rule Hardspacing

Non-default rule (NDR) hardspacing is supported in LEF/DEF. From this release, the following metal fill commands honor NDR hardspacing: addMetalFill addViaFill trimMetalFill This enables NanoRoute to support the NDR hardspacing rules.
trimMetalFillNearNet -createFillBlockage Now Supports Custom Names

In this release, trimMetalFillNearNet -createFillBlockage has been enhanced to support custom names. If you specify a name, the tool uses that name as the fill blockage name. If you do not specify a name, the tool uses the default name netName_layerName_* for the fill blockage. The advantage of using a custom name is that it makes it easier for you to delete all the fill blockage when required using the deleteRouteBlk command.
New trimMetalFillNearNet Parameter To Remove Metal Fill Near Critical Nets

In this release, a new option has been added to trimMetalFillNearNet to remove the metal fill near nets. Use the new -remove parameter if you want to remove the metal fill around critical nets instead of just trimming it.
addMetalFill Now Supports Check Board Vias

In this release, addMetalFill has been enhanced to support check board via generation. addMetalFill checks the snap grid and cut spacing to determine if the check board via is needed.
Check board vias are used between metal fill.
addMetalFill Enhanced To Allow User-specified List of Critical Nets in Timing-aware Mode

In this release, addMetalFill has been enhanced to enable you to specify a list of critical nets when adding metal fill in the timing-aware mode. If you are using a third-party tool for sign-off static timing analysis (STA), your list of timing critical nets may be different from that generated by report_timing in EDI/ETS. In such a case, you can use the new -extraCriticalNet option in addMetalFill to specify additional critical nets. You can use the -extraCriticalNet option in one of the following ways: In the -timingAware sta mode: There is likely to be some overlap between the list you specify and the EDI list of critical nets. The tool adds the extra nets you specify to the EDI list of critical nets determined via the -slackThreshold method. If the list you specify is exactly the same as the EDI list of critical nets, the tool works in the same way as it would without the -extraCriticalNet option. In the -timingAware on mode: In this mode, the tool considers the specified citical net list as medium cost. Use the -extraCriticalNet option in this mode if you want to avoid the run time hit that is associated with performing timing analysis using the -timingAware sta option. Note: If you use -extraCriticalNet option in the -timingAware off mode, the tool waives the extraCritcalNet option and issues a warning message.
setMetalFill -diagOffset Now Supports 0 Value

If you want to add metal fill shapes in a staggered pattern (addMetalFill -stagger diag), you must
first set -diagOffset offset_x offset_y in setMetalFill. In previous releases, both offset_x and offset_y values had to be larger than 0. In this release, setMetalFill has been enhanced to support the value 0 for offset_x and offset_y. This makes it possible for you to add metal fill staggered in one direction. For example, you can choose to have just a horizontal offset as follows: setMetalFill -diagOffset 6 0
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Timing Budgeting
Added Global Variables justifyBudget Enhanced to Honor report_timing_format Global Variable New Command to Reset Modified Budget
Added Global Variables

In this release, the following Timing Budgeting global variables have been added: tbgConsolidateTrialNoTrialIPO Specifies that the method used to create the DRV constraints is the same as that for performing timing budgeting, both with or without trial In-Place-Optimization (IPO). tbgCorrelateMaxTranWithActualTran Correlates the estimated max transition with the actual transition.
justifyBudget Enhanced to Honor report_timing_format Global Variable

The justifyBudget command now honors the report_timing_format global variable, which allows you to customize the timing report according to the user-specified columns. Previously, the justify report created during budgeting did not honor report_timing_format, therefore, the timing report format displayed only fixed columns by default. Now, the columns can be customized through the global variable. For example, the following command only lists the instance, arc, slew, and arrival times in the report: set_global report_timing_format {instance arc slew arrival} You must set this global before specifying justifyBudget or deriveTimingBudget -justify to get the report in the desired format.
New Command to Reset Modified Budget

You can now use the new command resetModifiedBudget to reset the budget that was modified using the modifyBudget command. resetModifiedBudget allows you to revert to the original generated budget if the modified budget is not yielding the correct timing for a block, or rectify an incorrectly modified budget. The syntax of the command is: resetModifiedBudget {-ptn partitionName | -inst instanceName} -pin pinName [-setup | -hold]
[-view viewName] [-help]
April 2012
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RC Extraction
preRoute Extraction Enhanced to Support height_over Construct in the ICT or QRC Technology File RC Extraction Mode GUI Enhanced for Specifying Standalone Signoff QRC Settings Support for Selecting SPEF par_value Triplet Field and Assigning to Corresponding RC Corner
preRoute Extraction Enhanced to Support height_over Construct in the ICT or QRC Technology File
Earlier, the ICT construct, height_over was not supported in preRoute extraction. In this release, preRoute extraction is enhanced to support height_over construct defined in the 20NM interconnect technology (ICT) file or QRC technology file.
RC Extraction Mode GUI Enhanced for Specifying Standalone Signoff QRC Settings
Earlier, the RC Extraction Mode form only supported the auto cmd mode, wherein, the QRC cmd file was automatically created from the EDI settings. In this release, the form is enhanced to provide additional controls for running Standalone Signoff QRC . The Signoff Run Settings include options to specify Run Mode including Auto, Partial or Custom mode, Command Type, Command File name, and Layer Map File name. This enhancement enables users to set QRC's CCL scripts in RC extraction form in the GUI.
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For details, see Specify RC Extraction Mode section in the EDI Menu Reference document.
Support for Selecting SPEF par_value Triplet Field and Assigning to Corresponding RC Corner
In this release, spefIn command is enhanced to allow selection of SPEF par_value triplet field and its assignment to the appropriate RC corner. For this, the following parameters are added to the command: -early_rc_corner: Annotates the parasitics to the early RC corner for multi-corner analysis. -early_spef_field: Specifies the field of the triplet values in spef to be loaded corresponding to early RC corner. -late_rc_corner: Annotates the parasitics to the late RC corner for multi-corner analysis. -late_spef_field: Specifies the field of the triplet values in spef to be loaded corresponding to late RC
corner. -spef_field: Specifies the field of the triplet values in spef to be loaded. The -spef_field parameter is used only when an existing RC corner is specified or when no corner is specified. This parameter is mutually exclusive to the -late_rc_corner, -early_rc_corner, late_spef_field, and -early_spef_field parameters.
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Timing
Reporting Enhancements Timing Library Enhancements SSTA Enhancements Other Enhancements Default Behavior Changes in Timing
Reporting Enhancements
report_property/get_property Supports Power and Ground Pins Added New Global to Report Constant Mismatch
report_property/get_property Supports Power and Ground Pins

You can now use the report_property and get_property commands to report and query on related power and ground pins names for the corresponding library pins. The following new properties have been added: related_ground_pin_name related_power_pin_name For example, get_property [get_lib_pins CELLA/A] related_power_pin get_property [get_lib_pins CELLA/A] related_ground_pin
Added New Global to Report Constant Mismatch

When the timing_enable_case_analysis_conflict_warning global variable is set to true during a full timing update, the software issues a warning when propagated and asserted constant values are not same. A report, named CTE_constant_mismatch.rpt, is generated that contains details of pins and the reason for constant mismatch. This report file is over-written each time a full timing update takes place. By default, the timing_enable_case_analysis_conflict_warning global is set to false.
Timing Library Enhancements

Added New Command to Check Library Database Version Added New Global to Derive Capacitance Range Ability to Read Library Without ECSM Data Added New Global to Disable ECSM Sensitivity Data
Added New Command to Check Library Database Version

You can use the following command to check the library database version: check_ldb_version If the library version is not updated, the details of missing features and recommendations for recompiling the
library database will be displayed.
Added New Global to Derive Capacitance Range

The following global variable has been added to infer the rise or fall of capacitance range values from CCS receiver capacitance model: timing_library_infer_cap_range_from_ccs_receiver_model By default, the global is set to false.
Ability to Read Library Without ECSM Data

The EDI system now allows you to change the mode of use (without ECSM timing model) if the timing library contains NLDM, ECSM, or CCS data in the same file. You can use the following global variable to disable loading ECSM data: timing_read_library_without_ecsm By default, the global is set to false.
Added New Global to Disable ECSM Sensitivity Data

You can use the following global variable to disable loading of ECSM timing sensitivity data when libraries are read: timing_read_library_without_sensitivity By default, the global is set to 0.
SSTA Enhancements
Ability to Report Sensitivity Details of Process Parameters
You can use the following global variable to report sensitivity details of each process parameter for slack, arrival, and required times at the endpoint of a timing path: timing_ssta_report_endpoint_description
Other Enhancements
Added New Parameters to MMMC RC Corner Commands Added New Global to Use Clock Slew for Check Arcs Ability to Reset/Update MMMC Data By Default Added New write_sdf Parameters
Added New Parameters to MMMC RC Corner Commands

The following new parameters have been added to the create_delay_corner and update_delay_corner commands: -early_rc_corner: Specifies the RC corner object to associate with the early corner object. -late_rc_corner: Specifies the RC corner object to associate with the late corner object
Added New Global to Use Clock Slew for Check Arcs

The following new global variable has been added to compute delays for check arc based on slews: timing_path_based_use_min_max_clock_slew_for_check When set to true, slews for delay calculation of check arc are deduced from the following: Slew at the signal pin of check arc is considered as retimed slew. For the reference pin slews of both min/max (or setup/hold) modes are considered . Based on the above slew conditions, two delays for a check arc are calculated. The worst value is considered as the check arc delay. By default this global variable is set to false.
Ability to Reset/Update MMMC Data By Default

In this release, the EDI system resets the timing, delay calculation, and RC corner data for MMMC objects by default. This is specific to MMMC objects that are created during system initialization. In previous releases, this data had to be reset or updated using the respective update commands update_analysis_view, update_constraint_mode, update_delay_corner, update_io_latency, update_library_set, and update_rc_corner.
Added New write_sdf Parameters

The following new parameters have been added to the write_sdf command: -exclude_whatif_arcs: Excludes what-if arcs in the SDF file. -target_application: Allows customization of the SDF output for use with STA or Verilog applications.
Default Behavior Changes in Timing


The report_timing -not_through parameter default behavior has been changed as follows: Previous Behavior Earlier, the -not_through parameter reported all the paths not traversing through the specified nets, ports, or pins of a cell. New Behavior Now by default, the -not_through parameter will be ignored when an object has already been specified. The following behavior changes have been made: If a collection of all the input ports have been specified (using all_inputs command), then the report will show paths to the inout part, and paths starting from the internal part of inout will be excluded. If a collection of all output ports have been specified (using the all_outputs command)
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Impact This behavior change was made so that paths going from/to/through inout parts are also reported.
April 2012
then the report will show paths starting from the internal part of inout, and paths ending at inout part will be excluded. If any other collection (not specified using all_inputs and all_outputs commands) is specified, then paths to both the parts will not be reported.
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Timing Debug

The Timing Debug Paths are now nested trees for easier collapse and un-collapse. The entries display the category information. The columns in this field include name of the category, worst negative slack (WNS), total negative slack (TNS), and number of failing paths.
April 2012
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Verification
Enhanced Verify AC Limit Form Enhanced Verify Cut Density Form Enhanced Verify Metal Density Form Enhanced Verify Power Via Form Enhanced Verify Routing Constraints Form New Verify Geometry Option To Report Out-of-die Objects Support for Rectangular Edges Enhanced Verify Geometry Support for LEF Properties verifyGeometry -noMinSpacing Enhanced To Ignore All Spacing Rule Checks verifyACLimit Enhanced To Perform Peak and Average Current Analysis
Enhanced Verify AC Limit Form

In this release, the GUI equivalent of an additional verifyACLimit parameter has been added to the Verify AC Limit form to improve usability: Rule File : Writes a file with suggested routing rules. The fixACLimitViolation command uses this file for widening wires and repairing AC current density violations. TheRule File option is equivalent to using verifyACLimit -ruleFile filename.
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Enhanced Verify Cut Density Form

The GUI equivalent of an additional verifyCutDensity parameter has been added to the Verify Cut Density form to improve usability: Ignore blocked window : Disables checking of windows that are fully covered by block or pad obstructions. This option is equivalent to using verifyCutDensity -ignoreCellBlock. In addition, the Oversize check box has been renamed to Size Up Area By for consistency with the Verify Metal Density form.
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Enhanced Verify Metal Density Form

The GUI equivalent of two additional verifyMetalDensity parameters have been added to the Verify Metal Density form: Save to DB : Saves density information to the EDI System database. This option is equivalent to using verifyMetalDensity -saveToDB. Size Up Area By : Specifies an offset value to the area that is to be verified. The value is in user units (not in DBU) and can be positive or negative. A positive value adds to the area that is verified. This option is equivalent to using verifyMetalDensity -oversize value.
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Enhanced Verify Power Via Form

In this release, the GUI equivalent of an additional verifyPowerVia parameter has been added to the Verify Power Via form to improve usability: Keep Previous Setting : Specifies that all previous verifyPowerVia settings will be kept. This option is equivalent to using verifyPowerVia-append.
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Enhanced Verify Routing Constraints Form

In this release, the Detailed option has been added to the Verify Routing Constraints form. If you select this option, the Verify Routing Constraints report will contain all information related to routing constraints instead of only violations.
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New Verify Geometry Option To Report Out-of-die Objects

Use the new setVerifyGeometryMode -boundaryHalo value option to report objects that are out of the die boundary. At the chip level, if any shape is outside the die-boundary, it may cause a problem. This option is defined to check if any shape, such as pin, routing, special routing, or cell, is outside the die boundary. The boundaryHalo value option specifies an offset value to the area to be verified. The value can be positive or negative. A positive value adds to the area that is verified. If (-area) + (-boundaryHalo) is within the design boundary, the behavior is same as with -area. If (-area) + (-boundaryHalo) is outside the design boundary, the out-of-die objects are checked.
Support for Rectangular Edges

In this release, as part of the NanoRoute2 implementation, EDI System introduces virtual nodes and adds patches in the form of rectangular edges. The rectangular edge defined by dbsWire is a virtual edge with a tag marked as rect. verifyGeometry and verifyConnectivity have been enhanced to support these rectangular edges. In previous releases, the wires were connected by the end points of the center line. Rect edges are rectangular patches in which connectivity cannot be traced through the center line. Without the rect edges, there would have been gaps between the regular wires connected by the center line and pins. As a
result, verifyGeometry would flag many same-net violations.
Enhanced Verify Geometry Support for LEF Properties

Verify Geometry has been enhanced to support the following LEF properties: NONEOLCORNERONLY keyword in PARALLELEDGE in end-of-line (EOL) SPACING rule The NONEOLCORNERONLY keyword specifies that the parallel edge neighboring wire must contain a corner that does not belong to another EOL edge. ABOVE, BELOW, PARALLELEDGE and MINLENGTH keywords in the EOLENCLOSURE rule ABOVE | BELOW: Specify that the EOL enclosure rule only applies on the routing layer above or below. PARALLELEDGE parSpace EXTENSION backwardExt forwardExt: Indicates that the EOLENCLOSURE rule only applies if there is a parallel edge on one side that is less than parSpace subtracting the width of the EOL edge and by extending backwardExt going backward and forwardExt going forward in the direction orthogonal to the EOL edge. MINLENGTH minLength: Indicates that if the EOL length is less than minLength along the side, then any parallel edge on that side is ignored, and the EOLENCLOSURE rule may not apply.
verifyGeometry -noMinSpacing Enhanced To Ignore All Spacing Rule Checks

Previous Behavior verifyGeometry -noMinSpacing ignores minimum spacing rule checks. New Behavior verifyGeometry noMinSpacing ignores all spacing rules and not just minimum spacing rule. This also applies to the setVerifyGeometryMode minSpacing false setting. Impact Improves Verify Geometry run time due to fewer checks. Usually, there is no need for checking advanced spacing rules when minimum spacing rules are being ignored.
verifyACLimit Enhanced To Perform Peak and Average Current Analysis

Traditionally, verifyACLimit is used to check RMS current (Irms ) violations. In this release, verifyACLimit has been enhanced to support peak current (Ipeak ) and average current (Iavg ) calculations. The following parameters have been added to verifyACLimit to enable these calculations:
-method: Use this parameter to specify the type of checks to be performed -- rms, peak, or avg. Note: Only the Advanced Analysis Engine (AAE) delay calculation engine supports I peak and I avg calculation. If you specify -method as peak or avg but AAE is not enabled, the tool displays the following error message: **ERROR(ENCVAC-92): verifyACLimit checks for -method peak or avg requires the AAE delay calculation engine. You must use setDelayCalMode -engine aae in EDI, before running verifyACLimit for peak or avg checks. -scaleCurrent: Use this parameter to specify the scale factor for the current. verifyACLimit multiplies the final current value (I rms , I peak , I avg ) by the specified scale factor before comparing it to the appropriate current limit to check for violations. This allows derating. -minPeakDutyRatio: Use this parameter to change the default minimum duty ratio value for I peak calculation. If a signal net has a duty ratio less than the minimum duty ratio, the minimum duty ratio will be used. -minPeakFreq: Use this parameter to ignore the I peak current limit calculation for signal nets that have an effective frequency below the specified value in Hertz. -avgRecovery: Use this parameter to specify the recovery factor for calculating the I avg current density with recovery. By default, the recovery factor (per layer) is read from the QRC techfile. If you specify -avgRecovery em_recover, it overrides the QRC tech em_recover factor for all the layers used in I avg limits. In addition to the above, the following parameters were also added to verifyACLimit: -useQrcTech: Use this parameter to force verifyACLimit to use the QRC tech file instead of the LEF technology file for Irms checks. Note: If either I peak or Iavg is also checked, all checks, including Irms, will use the QRC tech file. -deltaTemp: This parameter specifies the maximum temperature rise permitted in units of Celsius. This value is normally used in the QRC tech file for the RMS current limit equation.
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Yield Analysis
The reportYield command is now obsolete. This command still works in this release but will be removed in the next major release of the software.
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Power Calculation
Annotation Summary Reporting Enhancements Enhanced Register Gating Efficiency Reporting New Parameter to Control Output of Clock Gates Previously Supported but not Documented Parameter Added to Documentation
Annotation Summary Reporting Enhancements

The annotation summary reported in the EPS log file and validation file (.validation) has been enhanced to support object type based categorization. The summary is based on the mapping file specified using the map_activity_file command. This enhancement is useful when performing RTL VCD-based power analysis since it categorizes the entries used for annotation based on the following: Primary Input (PI), Primary Output (PO), Flops (DFF), Latches (DLAT), and Blackbox (BBOX). The following is a sample of the information appended to the log file: PI: 25/47 PO: 10/20 DFF: 299/350 DLAT: 345/500 BBOX: 45/90 The validation file has the following categories: Eliminated Entries with same names in RTL & GL netlist: Eliminated Entries which are missing in GL netlist which could be in RTL: Entries which matched the RTL VCD Variables to Gate Level objects: Entries in which RTL VCD Variables were found directly in design: Entries in which RTL names are not covered in VCD file: Each category is further categorized by object types. The following is a sample validation file: Entries in which RTL names are not covered in VCD file: PI entries: PO entries: DFF entries:
DLAT entries: BBOX entries: G inv R vin
Enhanced Register Gating Efficiency Reporting

In this release, the Register Gating Efficiency (RGE) reporting has been improved to display the ICG cluster information. The report now contains information about registers at the fanout of each ICG instance along with their RGE metrics. A sample report is given below: ICG block1_CG block2_CG Root Clock Toggles 1.0000e+08 1.0000e+08 Toggles at Clock Pin 1.0000e+08 1.0000e+08 Toggles at Q pin 5.0000e+07 5.0000e+07 RGE 0 0 DAGE 1 1 Instance block1/SEQDFF block2/SEQDFF2
New Parameter to Control Output of Clock Gates

You can use the new parameter -clock_gates_output_ratio of the set_default_switching_activity command to control the transition density at the output pin(s) of the integrated and combinational clock gating cells. This parameter is equivalent to specifying the parameters -icg_ratio and comb_clockgate_ratio together and with the same value. For example, the set_default_switching_activity -clock_gates_output_ratio 0.6 is equivalent to set_default_switching_activity -icg_ratio 0.6 -comb_clockgate_ratio 0.6. The -clock_gates_output parameter of the command set_default_switching_activity is now obsolete and has been replaced by -clock_gates_output_ratio. The obsolete parameter still works in this release, but to avoid a warning message and to ensure compatibility with future releases, update your script to use -clock_gates_output_ratio.
Previously Supported but not Documented Parameter Added to Documentation

The -compatible_internal_power parameter of the set_power_analysis_mode command was previously supported but not documented. This parameter has been set to true by default in the 11.1 release. The parameter specifies whether to use the new or old algorithm for internal power calculation. When set to true, the software uses the new algorithm. The new algorithm fixes problems in arc handling of some standard cells and is proven to be more accurate leading to better correlation with other third party tools. This would change the internal power numbers in 11.1 as compared to previous releases. At the design level, internal power can vary between 0-10%.
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Rail Analysis
auto_fetch_dc_sources Command Enhanced New Parameter to Support User-Specified Technology File Resistance Extraction for T/L Junctions set_power_data -instance Command Parameter Enhanced to Honor -format ascii Parameter set_rail_analysis_mode -power_up_fast_mode Parameter Default Behavior Changed Support for Decoupling Capacitance Static Violation GIF Plot Support for Embedded Bumps in Hierarchical TSV Designs
auto_fetch_dc_sources Command Enhanced

In this release, the auto_fetch_dc_sources command was improved to fetch the voltage sources within the specified region of a specific layer controlled by the region pitch (xPitch/yPitch). If the voltage sources with the specified region pitch are not on the stripe, you can use the -snap parameter to snap the voltage sources to the stripe. As a result, the voltage sources are generated only on the stripes and the region pitch is honored. This feature was added to enable the software to generate mesh type voltage sources on any process layer. Earlier, when the Edit Pad Location GUI form was used to auto fetch voltage sources within a region using the xPitch/yPitch option, the software always used the lower-left point of the defined region as the start point without checking if this point is on the net or not. Now, the start point will be snapped to the specified net automatically and then the region pitch will be used to fetch. The following parameters were added to the auto_fetch_dc_sources command to support this feature: -region {x1 y1 x2 y2 }generates the voltage sources in the specified region -region_pitch {xpitch ypitch }specifies the region pitch in the x and y direction for the voltage sources -layer {layername }specifies the process layer in LEF on which the voltage sources are to be generated The -lowest_layer parameter of the command auto_fetch_dc_sources is now obsolete and has been replaced by -layer. The obsolete parameter still works in this release, but to avoid a warning message and to ensure compatibility with future releases, update your script to use -layer.
New Parameter to Support User-Specified Technology File

You can now use the -extraction_tech_file parameter of the set_rail_analysis_mode command to specify the extraction technology file to be used for top-level power-grid extraction. If you do not specify this parameter, the software will use the extraction technology file stored inside the power-grid view library.
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Resistance Extraction for T/L Junctions

A minor change has been made to the resistance extraction algorithm for T/L junctions of metal geometries to produce more accurate results. This would change resistance values of such topology in the design and could result in some changes in IRdrop.
set_power_data -instance Command Parameter Enhanced to Honor format ascii Parameter

The set_power_data -instance command parameter now honors the -format ascii option. This enhancement allows you to specify the power consumption data for individual hierarchical instances in a simple ASCII two-column or three-column instance power file. The first column specifies the instance name, the second column specifies the power consumption, in watts, and the third column specifies the power pin of the instance for MSMV designs. Previously, the set_power_data -instance parameter was supported only when the power format was set to -format current.
set_rail_analysis_mode -power_up_fast_mode Parameter Default Behavior Changed

In this release, the default value of the -power_up_fast_mode parameter of the set_rail_analysis_mode command has been changed to true. In the current implementation, the software enables fast-mode simulation for native power-up analysis by default. Previously, the default value of this parameter was false. This default value has been changed because of performance penalty that was being caused when considering IRdrop feedback between always-on and powering-up domains. Even though IRdrop feedback is turned off during power-up analysis, the software does not use ideal voltage on power-gate always-on pins and uses realistic voltage considering the IRdrop effects of the always-on domain.
Support for Decoupling Capacitance Static Violation GIF Plot

Decap optimization in EDI System (set_rail_analysis_mode -decap_opt_method) does not calculate decap requirement in the regions of high static or average IRdrop, because IRdrop in such regions cannot be fixed with decaps. In this release, rail analysis will generate a new .gif plot called "decap_static_violations.gif" inside the state directory to highlight these regions when the average IRdrop exceeds the specified IRdrop threshold. To calculate the average IRdrop, the average current for the instances are derived from dynamic currents. The GIF plot will not be generated if the average IRdrop does not exceed the IRdrop threshold at any node on the power-grid.
Support for Embedded Bumps in Hierarchical TSV Designs

The auto_fetch_dc_sources command has been enhanced to support IR drop analysis for a hierarchical TSV design. When you specify the auto_fetch_dc_sources command to fetch the voltage sources from the LEF file, the command not only searches for the P/G pin of the pad connected to the specified P/G net, but also fetches for the embedded bump property definition for the P/G pin. The port that contains the point defined in the embedded bump property is considered as the center point of the embedded bump. The following LEF file syntax shows how to define an embedded bump: PROPERTYDEFINITIONS PIN EMBEDDEDBUMP STRING; END PROPERTYDEFINITIONS MACRO SUBSYS CLASS BLOCK; PIN VDD USE POWER ; PROPERTY EMBEDDEDBUMP M7 100 50; PORT LAYER M7; POLYGONE xxx; END END VDD END SUBSYS
The following command saves the voltage source name of the embedded bump, the pad location x and y coordinates, and the layer data to a file named bump.pp: save_pad_location format xy tsv file bump.pp The syntax of the pad location file is: <block_instance_name>/EmbeddedBump<No.> x y <layer_name>
April 2012
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23
Early Rail Analysis
Auto Trace Function for Switched Nets Supported New Parameters to Control Virtual Followpin Generation
Auto Trace Function for Switched Nets Supported

In this release, ERA has been enhanced to read the power-grid view library and trace switched-on nets of power gate cells automatically using the information stored in power gates' power-grid view. Previously, ERA could only trace switched-on nets using the power gate file specified with the analyze_early_rail power_gate_file command. If the power gate file was not specified, ERA could not trace switched-on nets of the power gate cells and you had to specify the switched-on net explicitly using the -net parameter.
New Parameters to Control Virtual Followpin Generation

In this release, the analyze_early_rail command was enhanced to specify the extension target for followpin generation. This feature allows you to reduce the turnaround time for generating followpin wire by sroute. The following parameters were added to the analyze_early_rail command: -extend_followpins_to_trunkextends the followpins to the next stripe. You can use this parameter if followpins extend its previous stripe but cannot reach the next stripe. -stop_followpins_at_rowendextends all followpins till the row end. By default, followpins stop at the last instance they reach.
April 2012
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Mixed-Signal Interoperability
GUI Updates New Commands Added
GUI Updates
The Integration Constraints Editor form now includes the following new buttons: Set OutsideSpacing, Set ShieldWidth, Set ShieldGap, and Set TandemWidth.
New Commands Added

In this release, the following new parameters have been added to the mixed-signal commands: run_vsr The run_vsr command is used for launching the Virtuoso Space-based Router (VSR) from EDI System. It accepts the library name, cell name and view name, and opens the cellview for speciality routing. It routes the selected nets in the following order: bus, diffPair, symmetry, match, nets and shield. Then, it saves this information within the given cell view. The following new parameters have been added to this command: -no_taper_to_pinwidth -share_shields
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setIntegRouteConstraint The setIntegRouteConstraintcommand applies specialty routing constraints in the database for nets in the designs. It allows creation of differential pair, match pair, shield nets, and nets with non-default rules. The following new parameters have been added to this command: -shieldWidth -shieldGap -tandemWidth -groupToOutsideSpacing
April 2012
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Clock Concurrent Optimization
This release is enhanced to provide a new technology called Clock Concurrent Optimization (CCOpt), which is a single-step process that optimizes both the clock tree and the datapath to meet global timing constraints. As clock trees become more complex in todays high-performance designs, with considerations required for aggressive chip frequency, clock gating, and power domains, a skew-driven clock tree synthesis (CTS) solution is not the best approach. EDI Systems CCOpt technology combines CTS with power, performance, and area optimization. Compared to the traditional skew-driven CTS, this technology provides a 10% improvement in design performance and total power, a 30% reduction in clock power and area, and a 30% reduction in dynamic IR drop. The following commands support this feature: ccoptDesign: Performs CCOpt on the current loaded design in the EDI system. This command optimizes both the clock tree and the datapath to meet global timing constraints generateCCOptRCFactor: Automatically computes resistance and capacitance multipliers for each operating condition and creates a script that sets these multipliers getCCOptMode: Displays information about the setCCOptMode command parameters in the EDI System log file and in the EDI System console setCCOptMode: Sets global parameters for ccoptDesign For more information about the commands, see the Clock Concurrent Optimization Commands chapter in the EDI System Text Command Reference. For more information about the CCOpt flow, see the Clock Concurrent Optimization section in the Synthesizing Clock Trees chapter in the EDI System User Guide.
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Clock Tree Synthesis
New Parameter Added to Size Up Gating Components to Maximum setCTSmode -routeClkNet Enhanced to Route Clock Nets after Synthesis or Optimization
New Parameter Added to Size Up Gating Components to Maximum

Use the new setCTSMode -synthUpsizeClockGate parameter to size up gating components to maximum. These can be sized down later by the software in order to reduce power and area without degrading the skew. The default value of this parameter is false.
setCTSmode -routeClkNet Enhanced to Route Clock Nets after Synthesis or Optimization

Previous Behavior The default value of setCTSmode routeClkNet option is false. So, when you run clockDesign to synthesize a clock tree, the command internally sets the setCTSmode routeClkNet option to true, routes clock nets after synthesis, and then resets this option back to false. This behavior is not desired as it ignores user option setting. New Behavior In this release, the default value of setCTSmode routeClkNet option is set to true. Impact With this change, setCTSMode routeClkNet default value and clockDesign default behavior are now consistent.
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OpenAccess
New Beta Control Variable
The following commands will now work using a new beta control variable. copy_design copy_design_hier compare_cellview save_abstract saveDesign -hier set_cell_binding Contact your Cadence representative for more information.
New Global to Specify a Constraint Group Name

You can use the new init_oa_default_rule global to specify a constraint group name at the start of EDI System session. The name provided would be used by EDI System for reading the place-and-route technology rules from the constraint group.
April 2012
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TSV
New Option Added to the Create TSV/Bump Form New Options Added to the Assign TSV/Bump Form
New Option Added to the Create TSV/Bump Form

The following new option has been added to the Create TSV/Bump form: Perimeter Matrix Creates TSV/Bump along the rings on perimeter, based on user's definition.
New Options Added to the Assign TSV/Bump Form

The following new options have been added to the Assign TSV/Bump form: Assign Region Exclude Region Assign Net Exclude Net Assign TSV/Bump within the region only. Do not assign TSV/Bumps within the specified region. Assign the specified nets to TSV/Bumps. Do not assign the specified nets to TSV/Bumps.
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Power Planning

The following two options have been added for the command setAddStripeMode. -stripe_min_width Specifies the minimum width of the remaining stripe after being trimmed. -trim_stripe Specifies if shape is trimmed by the specified shape.
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ECO Flows

A new flow has been added that allows you to make late logic changes after the masks are made. This flow uses pre-existing spare cells, so no poly/diffusion changes are allowed, and only the routing is modified. You can direct the software to make routing changes only on specific layers. For more details, refer PostMask ECO Changes from a New Verilog Netlist (Using Spare Cells Flow).
April 2012
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EDI System What's New 11.

About This Manual

Obsolete Command Parameters

EDI System Display and Tools

Importing and Exporting the Design

Multiple Supply Voltage (MSV)

Metal Fill and Via Fill

Timing Library Enhancements

Default Behavior Changes in Timing

Early Rail Analysis

Clock Concurrent Optimization Clock Tree Synthesis

EDI System What's New 11.1, 11.1

How This Document Is Organized

EDI System Product Documentation

EDI System What's New 11.1, 11.1

Product Version 11.1

EDI System What's New 11.1, 11.1

New Text Commands and Global Variables

EDI System What's New 11.1, 11.1

New Command Parameters

Chapter Low Power Commands

Rail Analysis Commands

Clock Tree Synthesis Commands

Timing Analysis Commands

EDI System What's New 11.1, 11.1

createPlaceBlockage -noCoreByCut -prefixOn createRouteBlk -prefixOn findPinPortNumber -cellName run_vsr -share_shields

Floorplan Commands and Global Variables

Floorplan Commands and Global Variables

Flip Chip Commands and Global Variables

Clock Tree Synthesis Commands

Power Calculation Commands

Power Calculation Commands

EDI System What's New 11.1, 11.1

setPlaceMode -groupFlopToMacroLevel -groupFlopToMacroList set_rail_analysis_mode -extraction_tech_file setIntegRouteConstraint -shieldWidth

Placement Commands and Global Variables

Rail Analysis Commands

Import and Export Commands and Global Variables

Metal and Via Fill Commands and Global Variables

EDI System What's New 11.1, 11.1

Metal and Via Fill Commands and Global Variables

Timing Analysis Commands

Timing Analysis Commands

Obsolete Text Commands and Global Variables

Obsolete Command Parameters

EDI System What's New 11.1, 11.1

Supported in this Release

Removed from the Software

Default Behavior Changes

EDI System What's New 11.1, 11.1

Commands Rail Analysis Resistance Extraction for T/L Junctions

Support to On-Chip Thermal Analysis Solution is Withdrawn

New and Revamped Documentation

New Chapter on Clock Concurrent Optimization Commands

Product Version 11.1

EDI System What's New 11.1, 11.1

Defining ccoptDesign for Clock Tree Construction

Defining ccopt Top and Bottom Layers

Variable Name clk_tree_top_layer