ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6

Compare Vedic Multipliers with Conventional Hierarchical array of array multiplier

Arushi Somani, Dheeraj Jain, Sanjay Jaiswal, Kumkum Verma and Swati Kasht
Abstract Multiplication is an important function in arithmetic operations. A CPU (central processing unit) devotes a considerable amount of processing time in performing arithmetic operations. Multiplication requires substantially more hardware resources and processing time than addition and subtraction [9]. Digital signal processors (DSPs) are the technology that is omnipresent in engineering Discipline. Fast multiplication is very important in DSPs for digital filter, convolution, Fourier transforms etc, [10]. This paper presents the comparative study of Vedic Multiplier are Urdhva Tiryakbhyam multiplier with Conventional multiplier Hierarchical array of array multiplier on various performance factors like power, delay, space, speed, Power Delay Product and Energy Delay Product. This paper gives information of Urdhva Tiryakbhyam algorithm of Vedic Mathematics which is utilized for multiplication to improve the speed, power and area of multipliers. Index TermsHierarchical array of array multiplier (HAOA), Energy Delay Product (EDP), Power Delay Product (PDP), Vedic Mathematics, Urdhva Tiryakbhyam.

I. INTRODUCTION The multiplier is a basic building block in Standard Digital Signal Processors (DSP). Most of the DSP tasks require real-time processing with several multiplications. Multiplication is most important arithmetic operation having wide applications from normal multiplication in DSP. Multiplication process is used in many applications like instrumentation and measurement, communications, audio and video processing, animations, special effect, Graphics, image enhancement, Navigation, radar, GPS, and control applications like robotics, machine vision.

Multiplication is the process of adding a number of partial products. Multiplication algorithms differ in terms of partial product generation and partial product addition to produce the final result [8]. Higher throughput arithmetic operations are important to achieve the desired performance in many real time signal and image processing applications. With time applications, many researchers have tried to design multipliers which offer either of the following- low power consumption, high speed, regularity of layout and hence less area or even grouping of them in multiplier. However, the two design criteria are often in conflict and that improving one particular aspect of the design constrains the other. The need of fast multiplication has gives rise to algorithms such as Baugh-Wooley method, Booth multiplier using recoding bits, Modified Booth algorithm (MBE). Although the MBE is most successful algorithms yet it is also a time consuming process. Nowadays, new methods are required for even faster multiplication strategies [5]. The conventional mathematical algorithms can be simplified and even optimized by the use of Vedic mathematics [4]. By using this technique we can improve the computational speed of processor to perform fast arithmetic operations. This paper summarize comparative study of Vedic multipliers (Urdhva Tiryagbhyam (U.T) type 1 [1] & type 2 [2]) with Conventional multiplier like hierarchical array of array multiplier [3] using Tanner Tool in 180nm technology. Section II presented conventional vs. vedic multiplication scheme. Section III explained basic working of vedic multiplier using Urdhva Triyagbhyam algorithms with example. Results and Comparison are described in Section IV. Finally conclusion of the paper is given in Section V.

II. CONVENTIONAL VS. VEDIC MULTIPLICATION SCHEME The Vedic mathematics is the ancient system of mathematics which has a unique technique for fast mental calculations, based on 16 sutras [11]. This approach is completely different from other multiplication algorithms and considered very close to the way a human mind works. Any ordinary human can perform mental operations for very small magnitude of numbers and hence Vedic mathematics provides techniques to solve operations with large magnitude of numbers easily. It covers explanation of several modern mathematical terms including arithmetic, trigonometry, plain, calculus, quadratic equations, factorization and spherical geometry.

Arushi Somani, Institute of Technology & management, Bhilwara, (e-mail: arushisomani@gamil.com). Bhilwarar(Raj.), India, Dheeraj Jain, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: dheeraj.suryamtech@gmail.com). Sanjay Jaiswal, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: to.sanjay1985@gmail.com). Kumkum Verma, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: kumkum.verma1983@gmail.com). Swati Kasht, Electronics & Communication, Institute of Technology & management, Bhilwara, Bhilwarar(Raj.), India, (e-mail: swati.kasht.26@gmail.com).

52

ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6, December 2012 In [3], author has presented a hierarchical implementation of multiplication based on an array of array technique. This multiplier architecture is based on generating all partial products and their sums. We have considered this architecture name as HAOA. This architecture shows moderate area and delay performance. The author claimed that HAOA multiplier is faster than the corresponding array multiplier and Booth multiplier. The author in [1] has proposed unsigned Array of Array multiplier circuit designed with hierarchical structuring. Author has considered this architecture name as U.T Type I. It has been optimized using Vedic Multiplication Sutra Urdhva Triyagbhyam and Karatsuba-Ofman algorithm. The author has showed large reduction in average power dissipation and in time delay as compared to Booth encoded radix-4 multiplier. In [2], the author presented a systematic design methodology for fast and area efficient digit multiplier based on Vedic mathematics. This Multiplier architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics. Author has considered this architecture name as U.T Type II. The Urdhva Tiryagbhyam sutra under Vedic mathematics is the general formula applicable to all cases of multiplication. The formula being very short and terse consists of only one compound word, means vertically and crosswise. III. VEDIC MULTIPLIER USINGURDHVA TRIYAGBHYAM SUTRA Urdhva and Tiryagbhyam words are derived from Sanskrit literature. Urdhva means Vertically and Tiryagbhyam means crosswise [7]. It is based on a novel concept, where the generation of all partial products can be done with the concurrent addition of partial products. Anyone can easily realize that this Vedic method probably makes difference for mental calculations [12]. For mental calculations it can be proved more convenient, as we can easily visualize Vedic multiplication line diagram shown in Figure 1. If someone tries to do multiplication mentally, in a conventional method, one would have to remember first row, then second row and likewise; then add all of them. In this case it might be difficult to remember these many numbers at a time. But in this Vedic method, to visualize line diagram and keep adding two consecutive product terms is easier for manual calculations. One needs to memorize only few numbers. So, one may find Vedic multiplication faster or more convenient for manual calculations [4]. The application of this sutra will ensure simpler means to solve typical multiplication problems encountered in the engineering environment. A simple example shown in Figure 2, the digits on the two ends of the line are multiplied and the result is added with the prior carry. When there are more lines in one step; all the results are added to the previous carry. The least significant digit of the number thus obtained acts as one of the result digits and the rest act as the carry for the next step. In the beginning the carry is taken to be zero [6], [9].

Fig. 2 Multiplication of 232 X 323=74936 by Urdhva Tiryagbhyam sutra with line diagram [6]

IV. RESULTS AND COMPARISON The Vedic Multipliers are U.T. Type 1 [1], U.T. Type 2 [2] and Conventional Multiplier is HAOA multipliers [3] have been implemented using Tanner Tool in 180nm technology. The comparative results of three multipliers are shown in table I, table II and table III for 4, 8 and 16 bits at Wp/Wn=3. The comparison graph for same is shown in Figure 4 to Figure 7 and output waveform of all the multipliers are shown in Figure 3. Table I Comparison of 4-bit multipliers
Multiplier Power (mw) Delay (ns) PDP (p-J) EDP (10-21Js) Transi stor Simulation time(S)

HAM U.T type 1 U.T type 2

0.21 0.21 0.2

5.45 5.16 4.86

1.14 1.08 0.97

6.24 5.59 4.72

636 552 514

17.88 15.97 16.64

Table II Comparison of 8-bit multipliers

Multiplier HAM U.T type 1 U.T type 2 power (mw) Delay (ns) PDP (p-J) EDP (10-21Js) Transi stor Simulaton time (S)

1.2 1.07 0.97

14.84 14.59 13.36

17.81 15.61 12.96

264.27 227.77 173.13

3524 2880 2634

57.76 51.59 45.77

Table III Comparison of 16-bit multipliers

Multiplier HAM U.T type 1 U.T type 2 power (mw) Delay (ns) PDP (p-J) EDP (10-21 Js) 3498.18 2345.34 1413.12 Transist or Simulation time(S)

5.79 4.6 4.12

24.58 22.58 18.52

142.32 103.87 76.30

15776 12864 11674

315.42 249.91 217.96

Fig.1 Multiplication Scheme using Urdhva Tiryagbhyam[4]

53

ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6 It is clear from table I, II and III that the U.T type 2 multiplier is shows better result compare to Hierarchical Array (HAM) and U.T type 1 multiplier with respect to Power, Delay, PDP, EDP and Required number of transistors. This is due to the hierarchical structuring & effectual addition of the partial product terms. The below results can be confirmed after comparison of all three multipliers for 16-bit number. Power is reduced by 28.84% and 10.43% for U.T type2 multiplier in compare to the HAM and U.T type 1 Multipliers respectively. Delay is reduced by 24.65% and 17.98% for U.T type2 multiplier in compare to the HAM and U.T type 1 Multipliers respectively. PDP is reduced by 46.38% and 26.54% for U.T type2 multiplier in compare to the HAM and U.T type 1 Multipliers respectively. EDP is reduced by 59.60% and 39.74% for U.T type2 multiplier in compare to the HAM and U.T type 1 Multipliers respectively. The result obtained from U.T type2 multiplier is faster and consuming low power than HAM and U.T type 1 multiplier. Speed improvements are grained by parallelizing the generation of partial products with their concurrent summations. The numbers of transistor used in construction of U.T type2 multiplier are also less in compare with HAM and U.T type1 multipliers. We have used 11674 transistors for U.T type2 multiplier in compare to 12864 transistors for U.T Type I multiplier, 15776 transistors for HAM. U.T type2 multiplier is space efficient also in compares to other multipliers. The result shows that, as the numbers of bits in the multiplier increases, the Vedic Multiplier i.e. U.T Type 2 takes the dominating role over U.T Type I and HAOA multiplier as shown in Figure 4 to Figure 7.

Fig. 4 Comparison of Power in different multipliers for 8 and 16 bits

Fig. 5 Comparison of Delay in different multipliers for 8 and 16 bits

(a)

Fig. 6 Comparison of PDP in different multipliers for 8 and 16 bits (b)

(c) Fig. 3 Output of 16-bit Multipliers (a) HAM (b) U.T type 1 (c) U.T type 2

Fig. 7 Comparison of EDP in different multipliers for 8 and 16 bits

54

ISSN 2249-6343 International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6, December 2012 V. CONCLUSION It can be concluded that Vedic Multiplier i.e. U.T type 2 is smallest, fastest multiplier using low power. The U.T type 2 multiplier dominates other multipliers as number of bits increases in multiplication. Due to various factors like timing efficiency, space, lesser area and PDP the traditional multipliers can be replaced by U.T type2 multiplier. In summary, the Power, Delay and PDP in U.T type2 multiplier is reduced by 28.84%, 24.65% and 46.38% compare to HAM respectively and 10.43%, 17.98% and 26.54% compare to U.T type1 multiplier respectively. This is due to the hierarchical structuring & effectual addition of the partial product terms. If the bits in the multipliers are continuously increases to N X N (where N is any number) bits than the U.T Type 2 multiplier showing better performance in compare to other multiplier on various performance factors like PDP & area. ACKNOWLEDGMENT The authors wish to thank all friends for their fruitful suggestion, support and precious time. REFERENCES
[1] Dr. K.S. Gurumurthy, M.S Prahalad, Fast and Power Efficient 1616 Array of Array Multiplier using Vedic Multiplication, International Conference on Computational Intelligence and Multimedia Application, 2006. [2] Shamim Akhter, VHDL implementation of fast NN multiplier based on Vedic mathematic, in 18th European Conference on Circuit Theory and Design, Sevilla Spain, pp. 472-475, August,2007. [3] Abhijit Asati, Chandrashekhar, A High-Speed, Hierarchical 1616 Array of Array Multiplier Design, International Conference on Multimedia, Signal processing and Communication Technologies (IMPACT), pp. 161-164, march 2009. [4] Parth Mehta, Dhanashri Gawali, Conventional versus Vedic mathematical method for Hardware implementation of a multiplier, 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies, Trivandrum Kerala, India, pp. 640-642, December 2009. [5] Prabha S.Kasliwal, B.P.Patil and D.K.Gautam, Performance Evalution of squaring operation by vedic mathematics, IETE Journal of research,Vol 57,Issue 1, pp.39-41, jan-feb 2011. [6] Harpreet Singh Dhillon, abhijit Mitra,A Reduced Bit Multiplication Algorithm for Digital Arithmetic, International journal of Computational and Mathematical Sciences, pp. 64-69,spring, 2008. [7] Manoranjan Pradhan, Rutuparna Panda, Sushanta Kumar Sahu, Speed Comparison of 16x16 Vedic Multipliers, International Journal of Computer Applications (0975 8887), vol 21 No.6, May 2011. [8] Hesham A. Al-Twaijry, Michael J. Flynn, Technology Scaling Effects on Multipliers, IEEE Transactions on Computers, vol. 47, No. 11, pp.1201-1215, November 1998. [9] Sumit Vaidya, Deepak Dandekar, Delay-Power performance comparison of multipliers in VLSI circuit design, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, pp.47-56, July 2010. [10] Ramesh Pushpangadan, Vineeth Sukumaran, Rino Innocent, Dinesh Sasikumar, Vaisak Sundar High Speed Vedic Multiplier for Digital Signal Processors,IETE journal,Vol.55, Issue 6, pp.282-286, November-December 2009. [11] Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic mathematics, Motilal Banarsidass Publishers Pvt Ltd,Delhi, 2009. [12] Anvesh kumar, Ashish raman, Low Power ALU Design by Ancient Mathematics, 2010 IEEE, Vol.5, pp.862-865, 2010. AUTHORS PROFILE : Arushi Somani received her B.E degree in Electronics and Communication Engineering with honors from Rajasthan University, Jaipur in 2007, and pursuing M.Tech in VLSI Design from Rajasthan Technical University, Kota. Her research interests include digital integrated circuit design, Signal and System, Digital Signal Processing, Wireless Communication and Microprocessor. Dheeraj Jain received his M.Tech. Degree in VLSI Design from the Centre for Development of Advanced Computing (C-DAC), Ministry of I.T. Government Noida. He is an Assistant Professor in Electronics and Communication Engineering, from Institute of Technology and Management Bhilwara (Rajasthan). He is pursuing Ph.d from Dr. K.N. Modi University (Raj.). His field of interest includes VLSI Design, Communication system, Electronics Devices and Circuit, and Embedded System. Sanjay Kumar Jaiswal received his M.Tech. Degree in VLSI Design from the Centre for Development of Advanced Computing (C-DAC), Ministry of I.T. Government Noida. He is an Assistant Professor in Electronics and Communication Engineering, from Institute of Technology and Management Bhilwara (Rajasthan). His field of interest includes VLSI Design, Communication system, Null convention Logic Design, SRAM Memory Design, and Sense Amplifier. He is also a member of IETE, Delhi. Kumkum Verma received her M.Tech. Degree in VLSI Design from the Centre for Development of Advanced Computing (C-DAC), Ministry of I.T. Government Noida. She is an Assistant Professor in Electronics and Communication Engineering, from Institute of Technology and Management Bhilwara (Rajasthan). Her field of interest includes VLSI Design, SRAM Memory Design, Communication system, Null convention Logic Design, and Sense Amplifier. She is also a member of IETE, Delhi. Swati Kasht received her B.E degree in Electronics and Communication Engineering with honors from Rajasthan University, Jaipur in 2009, and pursuing M.Tech in VLSI Design from Rajasthan Technical University, Kota. Her research interests are analog and digital integrated circuit design, biomedical, microprocessor.

55