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Three-Phase Dual-Buck Inverter With Unied Pulsewidth Modulation

Pengwei Sun, Student Member, IEEE, Chuang Liu, Student Member, IEEE, Jih-Sheng Lai, Fellow, IEEE, Chien-Liang Chen, Member, IEEE, and Nathan Kees, Student Member, IEEE

AbstractThis paper presents a new type of three-phase voltage source inverter (VSI), called three-phase dual-buck inverter. The proposed inverter does not need dead time, and thus avoids the shoot-through problems of traditional VSIs, and leads to greatly enhanced system reliability. Though it is still a hard-switching inverter, the topology allows the use of power MOSFETs as the active devices instead of IGBTs typically employed by traditional hardswitching VSIs. As a result, the inverter has the benet of lower switching loss, and it can be designed at higher switching frequency to reduce current ripple and the size of passive components. A unied pulsewidth modulation (PWM) is introduced to reduce computational burden in real-time implementation. Different PWM methods were applied to a three-phase dual-buck inverter, including sinusoidal PWM (SPWM), space vector PWM (SVPWM) and discontinuous space vector PWM (DSVPWM). A 2.5 kW prototype of a three-phase dual-buck inverter and its control system has been designed and tested under different dc bus voltage and modulation index conditions to verify the feasibility of the circuit, the effectiveness of the controller, and to compare the features of different PWMs. Efciency measurement of different PWMs has been conducted, and the inverter sees peak efciency of 98.8% with DSVPWM. Index TermsDual-buck inverter, three-phase inverter, unied PWM, voltage source inverter.

Fig. 1.

Proposed three-phase dual buck VSI with MOSFETs.

I. INTRODUCTION

HE widely used standard three-phase voltage source inverter (VSI) has two active switches in one phase leg that present some common problems. First, dead time is needed between the two active switches of the same phase leg, which reduces the equivalent pulsewidth-modulated voltage, and leads to output waveform distortions and less energy transfer. Second, even with dead time, shoot-through is still the major killer of VSIs, especially at some fault conditions. Third, people cannot simply employ power MOSFETs because of the reverse recovery problems of the body diode [1][5]. In order to obtain the benets of using MOSFETs, such as low switching loss, resistive conduction voltage drop, and fast switching speed that allows reduction of current ripple and the size of passive components, conventional approaches adopt soft-switching tech-

Manuscript received April 26, 2010; revised June 29, 2011; accepted July 30, 2011. Date of current version February 7, 2012. Recommended for publication by Associate Editor J. Clare. P. Sun, J.-S. Lai, C.-L. Chen, and N. Kees are with Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, VA 24060 USA (email: spw21st@vt.edu; laijs@vt.edu; jlchen99@vt.edu; nkees@vt.edu). C. Liu is with the Harbin Institute of Technology, Harbin 150001, China (e-mail: victorliuchuang@163.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2011.2164269

niques [6][9]. However, soft-switching inverters require additional auxiliary switches, passive components, and more gate driving circuits, which reduces reliability and increases system cost and complexity. This paper proposes a three-phase dual-buck inverter, shown in Fig. 1. It is hard-switching-based, but it can incorporate power MOSFETs as the active switches. The device count is the same as that of the standard three-phase VSI using insulated-gate-bipolar-junction-transistors (IGBTs). The idea of a three-phase dual-buck inverter originated from single-phase half-bridge and full-bridge dual-buck inverters [10][12]. It does not need dead time and has no shoot-through concerns. Because the body diode of the MOSFET never conducts, it can be hard-switched. The free-wheeling diodes can be chosen independently with fast reverse recovery features to minimize switching loss. Compared to single-phase dual-buck inverter, the three-phase counterpart does not have double-fundamentalfrequency ripple on the dc bus, and can be modulated with discontinuous space vector PWM (DSVPWM) to further reduce the switching losses and fully utilize the dc bus voltage. In order to modulate the three-phase dual-buck inverter, a unied pulsewidth modulation is adopted [13][16]. Compared to traditional space vector PWM (SVPWM) sector calculations [17][19], this method has much less computational burden when implemented by a digital signal processor (DSP). Due to the unique operation principle of the three-phase dual-buck inverter, the unied PWM is modied to use the current reference to generate the required gate signals. Different PWM methods can be considered as special cases of the unied PWM technique, including sinusoidal PWM (SPWM), space vector PWM (SVPWM), and discontinuous space vector PWM (DSVPWM). This paper rst presents the basic operation principle of the proposed inverter. Second, it analyzes the specic unied PWM technique applied to the three-phase dual-buck inverter. Third, it introduces the closed-loop controller design with

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Fig. 3. Four switching states for phase A. (a) S1 on, iA > 0. (b) D4 on, iA > 0. (c) S4 on, iA <0. (d) D1 on, iA < 0.

Fig. 2.

Relation between phase current and conducting devices.

proportional-resonant (PR) and admittance-compensation controllers. Finally, it shows a 2.5-kW hardware prototype and the test results under different dc bus voltage and duty cycle conditions to compare SPWM, SVPWM, and DSVPWM. Efciency of different cases was measured and compared. The DSVPWMcontrolled three-phase dual-buck VSI with MOSFETs allows an efciency of 98.8%. II. TOPOLOGY AND OPERATION PRINCIPLE The proposed three-phase dual-buck inverter has been shown in Fig. 1. Though it is a VSI, the PWMs for the active switches are determined by the phase output current. Fig. 2 shows the relation between the polarity of phase current and the operation of switches. Take phase A, for example, when iA is positive, S1 and D4 are the conducting devices and when iA is negative, S4 and D1 are the conducting devices. The same operation principle applies to phases B and C. Fig. 3 shows the four switching states for phase A. It can clearly be seen that the body diodes of S1 and S4 never have the opportunity to conduct, which ensures the safe switching of power MOSFETs. Since there is only one active switch per leg, shoot-through is no longer possible. Therefore, the reliability of the three-phase dual-buck inverter is much higher than with traditional VSIs. No dead time is needed because when S1 operates, S4 is always OFF and vice versa. The output waveforms are more sinusoidal and

the energy is transferred more completely without the dead-time effect. Because the power MOSFET and diode can be selected independently, the system efciency can be further improved. To minimize conduction loss, it is better to choose a power MOSFET with smaller on-resistance and a power diode with smaller forward voltage. To optimize the switching loss, a diode with fast reverse recovery capability is preferred. III. UNIFIED PWM ANALYSIS Even though MOSFETs are used for the three-phase dualbuck inverter to cut down switching losses, it is still a hardswitching VSI. Therefore, it is better to further reduce the switching loss by incorporating DSVPWM. At the same time, the dc bus voltage can be fully utilized by adopting SVPWM or DSVPWM rather than SPWM. Traditionally, the SVPWM methods [17][19] need to do trigonometric calculation and perform recombination of actual gating times, which is unfavorable for real-time implementation by a digital signal processor. Thanks to unied PWM methods [13][16], SVPWM and DSVPWM can be equivalently generated using triangle carrier comparison like SPWM, which greatly reduces computational burden and is very easy to implement by DSP. Fig. 4 shows the unied PWM generation block diagram. The switch to which PWM is applied is selected based on the current reference polarity. The phase duty cycles da , db , and dc are provided by a closed-loop controller, which will be discussed in Section IV. The injected zero sequence duty cycle dzs is generated by the following equation [13] dz s = [(1 2k0 ) + k0 dm ax + (1 k0 ) dm in ] (1)

where dm ax = max(da , db , dc )and dm in = min(da , db , dc ).

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Fig. 4.

Unied PWM generation block diagram.

k0 is the PWM determination factor. Under this unied PWM scheme, when k0 = 0.5, the output PWM is SVPWM; when k0 follows the relation in (2), the output PWM is DSVPWM with nonswitching state at phase current 60 peak region. k0 = 1 J > 0 k0 = 0 J < 0 J = max(iaref , ibref , icref ) + min(iaref , ibref , icref ). (2) Fig. 5 shows the simulation results of PWM generation using the unied PWM scheme with phase duty cycles da = db = dc = 0.9: (a) is SPWM with dzs = 0; (b) shows the SVPWM when k0 = 0.5; (c) shows the DSVPWM when k0 follows (2). For SPWM, the maximum phase duty cycle is 1; but, after injecting dzs , SVPWM and DSVPWM can boost the phase duty cycle up to 1.15, which means 15% more dc bus voltage utilization gain. From Fig. 5, it is clear that in terms of switching loss, SPWM is almost the same as SVPWM. In contrast, DSVPWM can further decrease switching loss because each phase does not switch for a 60 interval when its absolute phase current is the largest among the three phase currents. In addition, from (1) and (2), it is clear that the calculation burden required to implement this unied PWM is very small. IV. CLOSED-LOOP SYSTEM DESIGN In order to demonstrate the feasibility and advantages of the three-phase dual-buck inverter, the closed-loop control is derived and designed for a three-phase standalone system. Fig. 6 shows the average model of three-phase dual-buck inverter. dj (j = a, b, c) is the phase duty cycle, Lf and Cf are the lter inductor and capacitor, and Lj is the output inductor of each phase. Lj = Lp Lj = Ln ij > 0 ij < 0. (3)

Fig. 5. Unied PWM simulation results. (a) SPWM. (b) SVPWM. (c) DSVPWM.

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The PR controller transfer function can be represented as follows: GPR (s) = kp + s2 2c kr s 2. + 2c s + 1 (8)

For a 2.5 kW, 208VAC output inverter system, the following parameters are obtained through frequency domain design: kp = 0.02, kr = 12, c = 10. The current loop controller is a simple P-controller; its design result is shown in (9). The admittance loop gain is shown in (10). GPI (s) = 0.05 GAC (s) = 1 . Vdc /2 (9) (10)

Fig. 6.

Average model of three-phase dual-buck inverter.

Dene L = Lj + Lf , and the following equation can be obtained from Fig. 6 dj (t) Vdc dij (t) vj (t) = L . 2 dt (4)

Transform (4) to s domain ij (s) = 1 sL dj (s) Vdc vj (s) . 2 (5)

So the transfer functions from duty cycle dj to current ij and voltage vj to current ij are as follows: Gid (s) = Giv (s) = Vdc /2 ij (s) = dj (s) sL 1 ij (s) = vj (s) sL (6) (7)

GLPF (s) is second order low pass lter with cut-off frequency 5 kHz and a damping ratio 0.7. After obtaining phase duty cycles dj from Fig. 7, the unied PWM scheme shown in Fig. 4 can be used to generate the desired PWM to drive all the active switches. It is true that there will be some difference between the reference current and the real current around the zero-crossing, especially under transient conditions. In the prototype discussed here, the current sensor is simply used to feedback the real current information. It is not specically designed to track the zero-crossing. Therefore, the authors believe that it is better to use the reference as the PWM control signal because it has more immunity to noise, and does not have the current ripple problems of the real current. Experimental tests have been conducted using the reference signal, which proved to be no problem for the control performance. On the other hand, if the real current polarity information can be accurately sensed and determined near the zero-crossing point, it might be better to use that information to generate the PWM. In [26], a real current polarity detection circuit and algorithm are provided, and these could be adopted in the proposed topology. Of course, this will increase the complexity of the sensing circuit and require more of the computational capacity of the digital controller. V. EXPERIMENTAL RESULTS To prove the viability and merits of the proposed three-phase dual-buck inverter and evaluate the unied PWM scheme, a 2.5 kW, 208VAC output inverter system in standalone operation was designed and tested. The switching frequency is 20 kHz. All the devices are rated at 600 V. The MOSFET is STY80NM60N with on-resistance 35 m, and the diode is RURG3060 with reverse recovery time 55 ns. The passive components are selected as follows: Lp = Ln = 250 H, Lf = 1 mH, Cf = 2.4 F. The obtained cut-off frequency with the lters is 2.9 kHz. The load is variable resistive load bank. The design rules for Lp (Ln ) are provided below: Rule No. 1: For standalone and grid-tie applications, Lp (Ln ) can be designed based on the same rule that a conventional three-phase VSI follows. In this case, Lp (Ln ) serves as the lter Lf . It can be chosen based on the ripple current requirement of ia , ib , and ic , as well as the controller demand of lter cut-off

where Gid (s) is the control-to-output transfer function and Giv (s) is an uncontrolled feed-forward term. Fig. 7 shows the control block diagram of the three-phase dual-buck inverter operating at standalone mode. The control adopts the natural frame in a-b-c coordinates without the burden of transformation back and forth into rotational d-q coordinates for the digital signal processor [20]. Therefore, the control design needs high controller gain at the fundamental frequency. The closed-loop design adopts a two-loop concept, the inner current loop with a PI controller, GPI (s), to achieve fast dynamic response and enough damping and the outer voltage loop with a PR controller, GPR (s), to ensure a higher loop gain at the fundamental frequency [20][23]. In addition, the closed-loop control utilizes an admittance compensation controller, GAC (s). By introducing the admittance compensation controller, GAC (s), the undesirable term, Giv (s), can be cancelled out, smoothing zerocurrent start-up and reducing current steady-state error [24], [25].

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Fig. 7.

Control block diagram of three-phase dual-buck inverter at standalone mode.

Fig. 9.

Unied PWM when duty extended to 1.1. (a) SVPWM. (b) DSVPWM.

Fig. 8. Unied PWM signals for positive half-cycle switches when duty cycle is 0.9. (a) SPWM. (b) SVPWM. (c) DSVPWM.

frequency after selecting Cf . For example, if the selection of Lp (Ln ) follows this design rule, then Lp (Ln ) = 1.25 mH. Rule No. 2: If Rule No. 1 is followed, the total inductance will be twice that of conventional three-phase VSIs because there are six inductors instead of three. To solve this, one phase can share a common lter inductor Lf , and the remaining inductances can serve as Lp (Ln ). This solution was implemented in the prototype discussed in this paper. Lf is allocated 1 mH, and the remaining inductance, 0.25 mH, is dedicated to Lp (Ln ). In this way, a total of 3 mH inductance (1.25 mH 6 (0.25 mH 6 + 1 mH 3)) can be saved compared to Rule No. 1. The

inductance is only increased by 0.25 mH per phase compared to conventional VSIs. However, Rule No. 2 leads to another question: What is the smallest that Lp (Ln ) can be? Besides ltering, one of the functions of Lp (Ln ) is to protect against shoot-through under fault conditions. As discussed in Section II, in normal operation, the proposed inverter totally eliminates shoot-through problems. However, under some fault conditions, the gating signals for S1 and S4 might be high at the same time. Under this condition, Lp and Ln are inserted in the shoot-through path through the dc power supply, which will limit the di/dt of the devices, and thus decrease the failure rate of the circuit and provide enough time for the protection circuit to shut down the system. Therefore, larger Lp (Ln ) leads to less failure under fault conditions. As a result, when determining the value for Lp (Ln ) there is a tradeoff between cut-down of total inductance and protection under fault conditions.

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Fig. 10. Output voltage and current waveforms at dc bus voltage 380 V. (a) SPWM. (b) SVPWM. (c) DSVPWM.

Rule No. 3: In motor drive applications, there is no need to put in lter inductors because the motor inductance serves as the lter. In this case, Lp (Ln ) can be a smaller value selected to protect against shoot-through under fault conditions as discussed in Rule No. 2. The system controller and unied PWM are implemented using a TI oating point DSP TMS320F28335. For SPWM, the phase duty cycle can reach 1, while for SVPWM and DSVPWM the duty cycle can be extended to 1.15. Two duty cycle conditions are tested: one is 0.9 for SPWM, SVPWM, and DSVPWM; the other is 1.1 for SVPWM and DSVPWM. For the 0.9 duty

cycle condition, the dc bus voltage is set at 380 V. For the 1.1 duty cycle condition, the dc bus is lowered to 308 V. Efciency curves of different test conditions were measured and plotted. Fig. 8 shows the phase A duty cycle at 0.9 and the PWM for the active switch that operates during the positive half-cycle of each phase. It matches the simulation results. The PWM signals for the negative half-cycle are shifted 180 for each phase. Fig. 9 shows the relationship between da , dan and the corresponding PWM when the duty cycle is 1.1. It can be seen that after injection of dzs for SVPWM and DSVPWM, da can be larger than 1, which means further utilization of dc bus voltage. iS 4 is the current through S4 . It is clear that when S1 is switching during the positive half-cycle, S4 is OFF because the current through the switch is zero. When S1 is OFF during the negative half-cycle, S4 is operating based on the PWM pattern provided. Fig. 10 shows three-phase output current and phase-to-neutral voltage waveforms for SPWM, SVPWM, and DSVPWM under dc bus voltage 380 V with duty cycle 0.9. It is at the peak power condition (2.5 kW) with 120 V rms and 7 A rms ac output of each phase. It can be seen that the change between PWM schemes can be achieved effortlessly with unied PWM by adjusting the injected dzs while the output characteristics remain the same. Fig. 11 shows three-phase output current and voltage waveforms for SVPWM and DSVPWM under dc bus voltage 308 V with duty cycle 1.1. It can be seen that the output voltage is still 120 V, but the dc bus requirement is greatly reduced for these two SVPWM methods. Fig. 12 shows positive half-cycle three-phase output current waveforms for SPWM, SVPWM, and DSVPWM under dc bus voltage 380 V with duty cycle 0.9. It is the half-cycle current, unique to this topology, which ensures that only one active switch per phase works at any given time, eliminating the possibility of shoot-through. Loss analysis of the proposed inverter against conventional inverter is provided below: 1) Active switch loss comparison. Because of reverse recovery problems with the MOSFET body diode, conventional VSIs have to use IGBTs when the dc bus voltage ranges from 300 V to 600 V. This proposed topology avoids conducting through the body diode, and that is the reason why high voltage power MOSFETs (600 V to 900 V, such as CoolMOS or MDMesh series) can be employed. Conventional inverters use IGBTs, and the switching loss of IGBTs is much higher than that of MOSFETs for two major reasons. First, the switching speed of IGBTs is slower, so the overlap time of voltage and current during switching is longer and the overlap area is larger. Second, when IGBTs turn OFF, there is a large tail current which creates higher losses. The proposed inverter uses MOSFETs to reduce switching loss through its faster switching and lack of turn-off tail current. Because MOSFETs have a resistive conduction voltage drop while IGBTs have a xed voltage drop, the conduction loss is reduced as well when using MOSFETs. When this topology is used in higher current applications, MOSFETs can be paralleled to reduce the resistive voltage drop and thus still obtain a lower conduction loss than IGBTs of the same current rating.

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Fig. 11. Output voltage and current waveforms at dc bus voltage 308 V. (a) SVPWM. (b) DSVPWM.

Fig. 12. Output positive half-cycle current waveforms at dc bus voltage 380 V. (a) SPWM. (b) SVPWM. (c) DSVPWM.

Applications with very high output current may require more MOSFETs than can be practically put in parallel. In that case, it is a good idea to adopt the hybrid-switch concept [9], building each active switch by placing MOSFETs in parallel with an IGBT. The MOSFETs conduct when current is low, and the IGBT takes over under highcurrent conditions. The hybrid-switch might suffer from the tail current of the IGBT during high-current operation, but, compared to conventional VSIs, performance is still better in low-current regions because of the MOSFETs. 2) Diode loss comparison. Most conventional inverters use IGBT modules with antiparallel diodes. Most diodes paired with IGBTs are not designed to be fast switching diodes. When the diodes turn OFF, there are large reverse recovery losses. In contrast, the proposed topology allows the designer to pick a better free-wheeling diode. It is desirable to choose diodes with fast or ultrafast reverse recovery features to further cut down the switching losses, and, at the same time, diodes with lower voltage drops can be selected to reduce conduction losses. 3) Inductor loss comparison. When this topology is used in standalone and grid-tie applications where lter inductors are needed, the losses in the inductors are the same as the

Fig. 13. Efciency measurement under different PWM methods. (a) Efciency versus output power. (b) Efciency versus output current.

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losses in conventional VSIs. Even though the three-phase dual-buck inverter has more inductors than a conventional VSI, the loss is the same because Lp only works during the positive half-cycle, and Ln only works during the negative half-cycle. In motor drive applications, because Lp and Ln are small values, the associated losses are also small. The energy lost in the inductors is outweighed by the energy saved in the active switches. Therefore, the overall efciency of the proposed inverter is higher than that of traditional VSIs. Fig. 13 shows measured efciency curves under different dc bus voltage and duty cycle conditions for SPWM, SVPWM, and DSVPWM. The switching frequency is 20 kHz, and the output phase voltage is 120 V. The load is a three-phase, Yconnected, variable resistive load bank. All efciency measurements were done using digital power meters with 0.1% accuracy. The model number of the meters is YOKOGAWA WT1600. Fig. 13 (a) shows the efciency against total output power, while Fig. 13 (b) shows the efciency against phase rms current to meet the common practice of drive applications. It can be seen that DSVPWM can improve efciency by an average of 0.4% compared to SVPWM or SPWM under the same dc bus and duty cycle conditions. In addition, with the help of extended duty cycle, SVPWM and DSVPWM can run at lower bus voltage, further reducing switching losses. For example, the efciency of DSVPWM at 308 V with duty 1.1 is 0.7% higher than that of SPWM at 380 V with duty 0.9. The peak efciency of the inverter is 98.8%.

VI. CONCLUSION A new type of VSI, the three-phase dual-buck inverter, has been proposed. It has the advantage of utilizing power MOSFETs as active switches, and improves inverter reliability by eliminating the possibility of shoot-through and the need for dead-time. In order to reduce the computational load on the digital signal processor, unied PWM was analyzed and applied, including SPWM, SVPWM, and DSVPWM. To prove the effectiveness of the proposed topology and control scheme, a three-phase dual-buck inverter system operating at standalone mode with 2.5 kW, 208VAC output capability has been designed and tested. Different PWM methods were tested under different dc bus voltage and duty cycle conditions. The efciency of different cases was reported, and the peak efciency was 98.8%. REFERENCES
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Pengwei Sun (S07) received the B.S. and M.S. degrees, in electrical engineering, in 2004 and 2007, respectively, from North China Electric Power University (NCEPU), China. Since 2007, he has been a Graduate Research Assistant and Ph.D. student in the Future Energy Electronics Center (FEEC), at the Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, VA. His research interests are related to design and control of high-efciency single-phase and three-phase inverters, as well as multilevel and cascade inverters for renewable energy applications, including electric vehicle, and solar and wind power systems.

Chien-Liang Chen (M11) received the B.S. degree from National Taiwan University of Science and Technology, in 2002, the M.S. degree from National Tsing-Hua University, in 2004, and the Ph.D. degree from the Virginia Polytechnic Institute and State University (Virginia Tech), in 2011, all in electrical engineering. He is currently doing postdoctoral research at the Future Energy Electronics Center (FEEC), Virginia Tech. His research interests include grid-tie inverters, parallel inverters, mircogrid applications, and softswitching techniques.

Chuang Liu (S11) received the M.S. degree in electrical engineering, in 2009, from Northeast Dianli University, China. Since 2009, he has been a Ph.D. student in electrical engineering at Harbin Institute of Technology, China. Since September 2010, he has been at the Future Energy Electronics Center (FEEC), Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, VA, as a Visiting Student, supported by the Chinese Scholarship Council. His research interests are related to intelligent universal transformer (IUT) for renewable energy systems, as well as future dc-based renewable energy nanogrid, PHEV/PEV smart parking lot/building, and battery energy storage systems.

Nathan Kees (S07) received the B.S. degree in electrical engineering from Virginia Polytechnic Institute and State University (Virginia Tech), in 2008, where he is currently working toward the M.S. degree in electrical engineering. In 2008, he received the Bradley Fellowship from the Bradley Department of Electrical and Computer Engineering at Virginia Tech. He joined Dr. Hardus Odendaal in Electromagnetic Launcher Research at Virginia Tech as a Graduate Research Assistant in the same year. In 2010, he began work with Dr. JihSheng Lai in the Future Energy Electronics Center (FEEC) at Virginia Tech. He is interested in EMI problems in soft-switching inverters.

Jih-Sheng Lai (S85M89SM93F07) received the M.S. and Ph.D. degrees in electrical engineering from the University of Tennessee, Knoxville, in 1985 and 1989, respectively. From 1980 to 1983, he was the Head of the Electrical Engineering Department of the Ming-Chi Institute of Technology, Taipei, Taiwan, where he initiated a power electronics program and received a grant from his college and a fellowship from the National Science Council to study abroad. In 1986, he became a staff member at the University of Tennessee, where he taught control systems and energy conversion courses. In 1989, he joined the Electric Power Research Institute (EPRI) Power Electronics Applications Center (PEAC), where he managed EPRI-sponsored power electronics research projects. Starting in 1993, he worked with the Oak Ridge National Laboratory as the Power Electronics Lead Scientist, where he initiated a high power electronics program and developed several novel high power converters including multilevel converters and soft-switching inverters. In 1996, he joined Virginia Polytechnic Institute and State University (Virginia Tech), where he is currently a Professor and the Director of the Future Energy Electronics Center (FEEC). He has published more than 200 technical papers and 2 books and received 18 U.S. patents. His main research areas are in high efciency power electronics conversions for high power and energy applications. Dr. Lai chaired the 2000 IEEE Workshop on Computers in Power Electronics (COMPEL 2000), the 2001 IEEE/DOE Future Energy Challenge, and the 2005 IEEE Applied Power Electronics Conference and Exposition (APEC 2005). He is the recipient of several distinctive awards including a Technical Achievement Award at Lockheed Martin Award Night, two IEEE IAS Conference Paper Awards, and Best Paper Awards from IECON-97, IPEC-05, and PCC-07.