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1 System-on-chip research leads to hardware/software co-design degree

Dent, D.J. Fac. of Sci., Technol. & Design, Luton Univ. ; This paper appears in: Frontiers in Education Conference, 2000. FIE 2000. 30th Annual 10/18/2000 -10/21/2000, 2000 Location: Kansas City, MO , Volume: 2, 2000 USA On page(s): S1G/1-S1G/6 vol.2 References Cited: 6 Number of Pages: 2 vol.623+596 INSPEC Accession Number: 6839815

Abstract: A case study of multi-chip module design, implementation and evaluation has been undertaken by the author at Matra Marconi Space as part of an on-going research programme into large electronic designs. Multi-chip modules offer an intermediate step towards system-on-chip. The intention of Matra Marconi Space is to use unprecedented levels of electronic integration in the next generation of communications satellites to provide the maximum number of channels thereby giving maximum revenue to the satellite operators. This case study has already had an impact on the curriculum of the degree courses at the University of Luton. Consequently, hardware description languages have been integrated into the electronics degrees for many years now and all students have extensive use of current, industry standard electronic design automation tools. The theme of all of the electronics courses at Luton is Design, Simulate, Build and Evaluate . Students educational experience has immediate relevance in industry which has resulted in the student's obtaining exceptionally good careers when they graduate. This case study laid the foundation of the system-on-chip research at the University of Luton that has resulted in the hardware/software co-design masters programme

NO. 2 Test of future system-on-chips

Zorian, Y. Dey, S. Rodgers, M.J. LogicVision Inc., San Jose, CA; This paper appears in: Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on 11/05/2000 -11/09/2000, 2000 ,Location: San Jose, CA , On page(s): 392-398 2000 References Cited: 43 IEEE Catalog Number: 00CH37140 Number of Pages: xxv+575 INSPEC Accession Number: 6820120 Abstract: Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a single chip. Being able to rapidly develop, manufacture, test, debug and verify complex SOCs is crucial for the continued success of the electronics industry. This growth is expected to continue full force at least for the next decade, while making possible the production of multimillion transistor chips. However, to make its production practical and cost effective the industry road maps identify a number of major hurdles to be overcome. The key hurdle is related to test and diagnosis. This embedded tutorial analyzes these hurdles, relates them to the advancements in semiconductor technology and presents potential solutions to address them. These solutions are meant to ensure that test and diagnosis contribute to the overall growth of the SOC industry and do not slow it down. This embedded tutorial in addition presents the state of the art in system-level integration and addresses the strategies and current industrial practices in the test of system-on-chip. It discusses the requirements for test reuse in hierarchical design, such as embedded test strategies for individual cores, test access mechanisms, optimizing test resource partitioning, and embedded test management and integration at the System-on-Chip level. Processor cores being one of the most common cores embedded in a SOC, issues related to self-testing embedded processor cores are addressed. Future research challenges and opportunities are discussed in enabling testing of future SOCs which use deep submicron technologies 2 USA

NO. 3 Adaptive systems-on-chip: architectures, technologies and applications

Becker, J. Pionteck, T. Glesner, M. Inst. of Microelectron. Syst., Darmstadt Univ. of Technol.; This paper appears in: Ingegrated Circuits and Systems Design, 2001, 14th Symposium on. 09/10/2001 -09/15/2001, 2001 Location: Pirenopolis , On page(s): 2-7 2001 References Cited: 25 Number of Pages: xii+237 INSPEC Accession Number: 7154506 Brazil

Abstract: The fast technological development in Very Large Scale Integration (VLSI) has enabled chip-designers to integrate complete electronic systems, formerly built of several separate chips, onto one single piece of silicon. These Systems-on-Chip (SoCs) introduce a set of various challenges for their interdisciplinary microelectronic implementation, from system theory (application) level over efficient CAD methods to suitable technologies. Important aspects for the industry are the flexibility and adaptivity of SoCs, which can be realized by integrating reconfigurable hardware parts on different granularities into Configurable Systems-on-Chip (CSoCs). The paper describes the major challenges and first approaches in architecture, design and application of application-specific adaptive SoCs, e.g. in digital baseband processing for future mobile radio devices

NO. 4 An efficient bus architecture for system-on-chip design

Cordan, B. Palmchip Cor., Loveland, CO; This paper appears in: Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 05/16/1999 -05/19/1999, 1999 Location: San Diego, CA , On page(s): 623-626 1999 References Cited: 0 IEEE Catalog Number: 99CH36327 Number of Pages: 668 INSPEC Accession Number: 6467854 USA

Abstract: This paper presents the issues confronted when integrating system-on-chip (SOC) designs and offers solution through a detailed description of the CoreFrameTM system-on-chip bus architecture that has dramatically reduced system design and verification effort while enhancing the reusability and customizability of system-on-chip product developments. The CoreFrame on-chip bus architecture is defined along with examples to illustrate how a design friendly bus standard will effect the mix and match of reusable cores without sacrificing performance

NO. 5 Configurable systems-on-chip: commercial and academic approaches

Becker, F. Inst. fuer Technik der Informationsverarbeitung, Karlsruhe Univ., Germany; This paper appears in: Electronics, Circuits and Systems, 2002. 9th International Conference on On page(s): 809- 812 vol.2 Volume: 2, ISSN: Number of Pages: 3 vol.xxxvii+1270 INSPEC Accession Number: 7574661 2002

Abstract: Systems-on-chip (SoCs) has become reality now, driven by fast development of CMOS VLSI technologies. Complex system integration on to one single die introduces a set of various challenges and perspectives for industrial and academic institutions. Important issues to be addressed here are cost-effective technologies, efficient and application-tailored hardware/software architectures, and corresponding IP-based EDA methods. Due to exponentially increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into configurable systems-on-chip (CSoCs).

NO. 6 A hierarchical simulation framework for application development on system-on-chip architectures

Mathur, V. Prasanna, V.K. Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA; This paper appears in: ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International 09/12/2001 -09/15/2001, 2001 Location: Arlington, VA , On page(s): 428-434 2001 References Cited: 18 Number of Pages: 480 INSPEC Accession Number: 7168177 USA

Abstract: We propose a hierarchical simulation methodology to assist application development on System-on-Chip architectures. Hierarchical simulation involves simulation of a SoC based system at different levels of abstraction. Thus, it enables a system designer to exploit simulation speed vs. accuracy of results trade-offs. Vertical simulation is a special case of hierarchical simulation, where a feedback mechanism between the different simulation levels helps in "interpreting" the results of stand-alone simulations in the system-wide context. The paper presents an approach to perform vertical simulation of a class of applications under a simplified scenario

NO. 7 Configurable systems-on-chip (CSoC)

Becker, J. Inst. fuer Technik der Informationsverarbeitung (ITIV), Karlsruhe Univ., Germany; This paper appears in: Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on On page(s): 379- 384 2002 ISSN: Number of Pages: xiv+390 INSPEC Accession Number: 7516590

Abstract: Systems-on-chip (SoCs) has become reality now, driven by fast development of CMOS VLSI technologies. Complex system integration onto one single die introduces a set of various challenges and perspectives for industrial and academic institutions. Important issues to be addressed here are cost-effective technologies, efficient and application-tailored hardware/software architectures, and corresponding IP-based EDA methods. Due to exponentially increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into configurable systems-on-chip (CSoCs).

NO. 8 Specification, modeling and design tools for system-on-chip

Lavagno, L. Dey, S. Gupta, R. Dept. of Electr., Manage. & Mech. Eng., Undine Univ., Udine; This paper appears in: Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings. 01/07/2002 -01/11/2002, 2002 Location: Bangalore , On page(s): 21-23 2002 Number of Pages: xxx+810 INSPEC Accession Number: 7253748 India

Abstract: Summary form only given. Illustrates first the languages and models of computation available to the system-level. designer to capture precisely and unambiguously requirements. We discuss for what application domain and platform each language is most appropriate, focusing mostly on platform-independent languages and MOCs, since they support the greatest freedom in mapping choice. We will then discuss how the architecture of the platform, and the services it offers to the application designer, can also be formally and compactly captured and specified. We will show how the mapping paradigm can be used to select an implementation for the functional blocks and their communication, and how simulation and implementation methods can be derived automatically. In particular, we will describe how software estimation and synthesis for reactive real-time systems can be competitive with hand design, while retaining the ease of re-use typical of high-level specifications. In the next part of the tutorial, we will establish the importance of on-chip communication architectures in determining the performance of System-on-Chips (SoCs). We will track several on-chip communication architectures that are in use today

NO. 9 Interconnect IP node for future system-on-chip designs

Saastamoinen, I. Siguenza-Tortosa, D. Nurmi, J. Inst. of Digital & Comput. Syst., Tampere Univ. of Technol.; This paper appears in: Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on 01/29/2002 -01/31/2002, 2002 Location: Christchurch , On page(s): 116-120 2002 References Cited: 9 Number of Pages: xvii+517 INSPEC Accession Number: 7327785 New Zealand

Abstract: An interconnect IP (intellectual Property) node architecture for flexible on-chip communication is introduced. This architecture is targeted for communication in future gigatransistor SoC (System-on-Chip) designs. The interconnect IP will be used as a testing platform when the efficiency of network topologies and routing schemes are investigated for the on-chip environment. The interconnect node uses packet based communication and forms a reusable component itself. The node is constructed from a collection of parameterized and reusable hardware blocks, which include components such as FIFO buffers, routing controllers and standardized interface wrappers. A node can be tuned to fulfill the desired characteristics of communication by selecting the internal architecture properly

NO. 10 Automatic software toolkit generation for embedded systems-on-chip

Halambi, A. Grun, P. Tomiyama, H. Dutt, N. Nicolau, A. Center for Embedded Comput. Syst., California Univ., Irvine, CA; This paper appears in: VLSI and CAD, 1999. ICVC '99. 6th International Conference on 10/26/1999 -10/27/1999, 1999 Location: Seoul , 1999 References Cited: 44 Number of Pages: xvii+620 INSPEC Accession Number: 6589210 South Korea On page(s): 107-116

Abstract: Modern embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memory. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-qualify software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on approaches to software toolkit generation that automatically produce the software infrastructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs

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NO. 11 Design of an optimal test access architecture using a genetic algorithm

Ebadi, Z.S. Ivanov, A. Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC; This paper appears in: Test Symposium, 2001. Proceedings. 10th Asian 11/19/2001 -11/21/2001, 2001 Location: Kyoto , 2001 References Cited: 13 Number of Pages: xxvi+473 INSPEC Accession Number: 7204880 Japan On page(s): 205-210

Abstract: Test access is a major problem for core-based system-on-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. One of the most important issues in designing a test access architecture is testing time. Here, several issues related to the design of an optimal test access architecture with the goal of minimizing testing time are discussed. These issues include the assignment of cores to test buses, the distribution of test data width between multiple test buses, and the estimation of test data requirements to satisfy an upper bound on the testing time. Previous works show that all of these problems are NP-complete. Here, we applied a genetic algorithm (GA) to solve these problems. Experiments were run on two hypothetical but non-trivial SOCs using the implemented GA. The results show a 40% improvement. The performance improvement is principally due to our removing the constraints of the necessity of serialization and allowing the system to handle serial or parallel test data loading for any core

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NO. 12 Matisse: a system-on-chip design methodology emphasizing dynamic memory management

Verkest, D. Jong, G. Leao da Silva, J., Jr. Ykman, C. Croes, K. Miranda, M. Wuytack, S. de Catthoor, F. De Man, H.

Alcatel Telecom, Antwerp; This paper appears in: VLSI '98. System Level Design. Proceedings. IEEE Computer Society Workshop on 04/16/1998 -04/17/1998, 16-17 Apr 1998 Location: Orlando, FL , On page(s): 110-115 16-17 Apr 1998 References Cited: 16 IEEE Catalog Number: 98EX158 Number of Pages: ix+142 INSPEC Accession Number: 6046640 USA

Abstract: Matisse is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of Matisse on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption

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NO. 13 Designing for the IP supermarket

Bray, N. ARM Ltd., Cambridge; This paper appears in: Fall VIUF Workshop, 1999. 10/04/1999 -10/06/1999, Oct 1999 Location: Orlando, FL , On page(s): 8-13 Oct 1999 References Cited: 5 IEEE Catalog Number: PR00465 Number of Pages: ix+110 INSPEC Accession Number: 6409771 USA

Abstract: It is becoming unfeasible to create large high gate count System-on-Chip devices within the short development times being demanded unless existing design methodologies are adapted. The trends continue relentlessly with further demand for reduction of time-to-market device gate count increasing in accordance with Moore's Law and growing consumer expectations for improved cost/functionality in each new generation of products. It is also being widely recognised that reuse and sharing of virtual components (VCs) is becoming fundamental to closing the deep sub-micron design gap for successful System-on-Chip design. Design reuse can increase productivity while also enabling faster more complex IC designs. A recent study warns that companies who do not embrace the use of such commercial IP could quickly find themselves at a strategic disadvantage. The paper describes an approach used within ARM to develop reusable soft IP (intellectual property) designs. Reference is made to PrimeCell designs which are System-on-chip peripherals having bus interfaces based on ARM's Advanced Microcontroller Bus Architecture. Reusable IP designs are targeted for widespread usage, and faster and easier integration in a multiple source IP chip synthesis design flow. Design reuse is considered in a wide context, applying it to the complete design together with associated development environment, test infrastructure and documentation. The emphasis is on reduction of time-to-market in order to bridge the growing process-productivity gap for System-on-Chip devices, by designing for wide usage with independence from semiconductor processes and design tools 13

NO. 14 A system-level simulation environment for system-on-chip design

Schneider, T. Mades, J. Windisch, A. Glesner, M. Monjau, D. Ecker, W. Inst. of Microelectron. Syst., Darmstadt Univ. of Technol.; This paper appears in: ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International 09/13/2000 -09/16/2000, 2000 Location: Arlington, VA , On page(s): 58-62 2000 References Cited: 16 IEEE Catalog Number: 00TH8541 Number of Pages: xix+417 INSPEC Accession Number: 6812817 USA

Abstract: This paper presents a mixed-signal/multi-language simulation environment for the languages VHDL-AMS, Java, and C++. The environment is implemented in Java and based upon a previously developed VHDL-AMS design environment consisting of a compiler, an elaborator and a simulator. The latter was extended by open object-oriented Java and C++ interfaces towards system-level simulation capabilities. Obviously, this approach lends itself to a VHDL-centric modeling style. However it also results in a well-defined overall simulation semantics based on the proven semantic principles of VHDL-AMS. Moreover the object-oriented Java and C++ interfaces enforce a much better language modeling style than traditional callback-based procedural language interfaces. The presented open architecture provides good capabilities for research in the field of system-level simulation

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