An all-Digital PLL Clock Multiplier

Thomas Olsson and Peter Nilsson

Dept. of Electroscience, Lund University. P.O. Box 118, SE-22100, Lund, Sweden.

Thomas.Olsson@es.lth.se, Peter.Nilsson@es.lth.se ABSTRACT

A fully integrated digital PLL used as a clock multiplying circuit is designed and manufactured. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35m standard CMOS process and a 3.0V supply voltage, the PLL has a frequency range of 152MHz to 366MHz and occupies an on-chip area of about 0.07mm2. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation change of process. This paper consists of two major parts. First, an implementation of the all-digital PLL is described together with measurement results. Second some fundamental improvements of the first design are discussed. These improvements are such as describing the PLL in synthesizable VHDL code and improved phase error measurement.

2. DESIGN OVERVIEW
Figure 2 shows the block structure for the all-digital PLL. The phase detector is controlling the counter, which is in this configuration is clocked by "clk_out". The output of the DCO is divided by the multiplication factor and then compared in phase to the reference. The phase error is translated into a digital signal in a time-to-digital converter (T2D). The signal "UPDATE" from the phase-detector is used to clock the registers and to reset the counter.

1. INTRODUCTION
PLLs are widely used circuits for clocking digital IP-blocks. Traditionally, a PLL is made as a partly analog building block. However, integrating an analog PLL in a digital noisy environment is difficult. In addition, the analog PLL is also sensitive to process variations and must therefore be redesigned for each new process. Robust and easy implemented fully digital clock multipliers without phase locking are proposed in [1] and [2]. These clock multipliers produce a fixed number of cycles for each period of an external reference clock signal followed by an idle margin. For many digital applications, using such simpler clock generators is a possible solution. However, for a number of applications, using for instance synchronous on-chip communication, a PLL is necessary to ensure correct functionality. In this paper, an implementation of a digital PLL is presented. The digital PLL is designed as an IP-block described as a netlist linked to a standard cell library. For most digital applications, a standard cell description of the PLL simplifies the design, since the design including the PLL becomes portable between technologies.

REF /M clk_out
BUF

EVENT

*UPDATE

Ph-det
UP/DOWN

T2d

Recursive filter *

REG
*

+/REG

DCO

0.5

Figure 2. Block structure of all-digital PLL.

3. DIGITALLY OSCILLATOR

CONTROLLED

REF

PD /M

Filter

OSC

CLK

Figure 1. PLL block structure. The block structure of a PLL, shown in figure 1, is divided into a phase detector, a loop filter an oscillator and a frequency divider. For the digital PLL, the phase detector is a slightly modified standard type IV detector [3], the loop filter consists of a counter and a digital recursive filter, and the oscillator is a digitally controlled oscillator (DCO).

The difficulty when making an all standard cell PLL is often to implement an oscillator with high resolution. A variable number of inverters can be used for implementing a variable delay. However, this results in delay steps of several hundred ps, which give an inaccurate and unstable phase lock for high frequency applications. The oscillator for the digital PLL is a 7 stage ring oscillator with one inverter replaced by a NAND-gate for shutting down the ring oscillator during idle mode. To change the frequency of the ring oscillator, a set of 21 inverting tri-state gates are connected in parallel with each inverter (see figure 3). When the tri-state gates are enabled additional current drive is added to each inverter stage. The 126 tri-state gates are controlled by a 126 bit vector C, which is decoded from a 7 bit control word, W. The 126 bit vector is all ones for W=0 and all zeros for W=125 to 127. For W<126, the number of zeros in C is equal to the value of W.

RUN C[0] C[120] C[1] C[121] C[5] C[125]

Figure 3. DCO. Measured period time versus digital control word for the DCO at 3.0V supply voltage is shown in figure 4. The plot in figure 4 has a slope of between 10 ps/bit and 150ps/bit. It is important to keep the slope low since the slope sets the resolution of the DCO. A negative slope must also be avoided, since this might cause the PLL to be unstable. Since adding current drive by enabling a tri-state gate cannot slow down the oscillator, negative slope will not occur. The curve of figure 4 is therefore always monotonic.

There is therefore always a pulse at both nodes "UP" and "DOWN". For the "EVENT" signal in figure 5, the internal delay is canceled out using an exor gate. Thereby, a more accurate measurement of the phase error is achieved. This PLL implementation works as a synchronous digital circuit, which thus needs a clock pulse for updating all registers. At the end of each phase error a short pulse is produced at the node "UPDATE". This pulse, which is as long as the internal delay of the phase detector, is further delayed and used as a system clock.
UP

REF

DIRECTION

RESET CLK

EVENT UPDATE DOWN

Figure 5. Phase detector.

5. LOOP FILTER
The loop filter consists of a time to digital converter (T2D) and a digital recursive filter (see figure 2). The time to digital converter consists of a counter, which measures the phase error using the DCO output as a reference. The result from the counter is used to update the control word for the DCO.

6. FABRICATION RESULTS

AND

TEST

Figure 4. Measured period time vs. digital control word (W). Although the DCO of figure 3 has the advantage of being made from all-standard cells, it has disadvantages such as relatively high power consumption and low maximum frequency from high capacitive load in the ring oscillator. The extremely nonlinear behavior also makes it difficult to find a proper loop gain for the PLL. For applications demanding high resolution and less power consumption for the DCO, a full-custom design is preferable. For high frequency operation, a D/A converter followed by a VCO might be a good alternative.

The all-digital PLL is fabricated in a in a 0.35m triple-metal CMOS process. Figure 6 shows a chip photo of a prototype chip containing the digital PLL. The actual core area for the digital PLL is 0.07mm2.

4. PHASE DETECTOR
The type IV phase detector has in its original configuration two outputs controlling the oscillator frequency: One for signaling "UP" and one for signaling "DOWN" for the duration of the phase error. A slight modification is done to produce one signal "DIRECTION" and one signal "EVENT" showing the length of the phase error. The modified phase detector is shown in figure 5.
Due to internal delay of the phase detector, the pulses at node "UP" and "DOWN" are longer than the actual phase error. Figure 6. Chip Photo.

To study the pull-in and lock process of the PLL, the step response is tested. Figure 7 shows the step response for a reference period of 400ns and a multiplication factor of 64. Since an exact frequency never is found, the control word will oscillate between two values during phase lock.

Figure 9. PLL lock range.

7. IMPROVED DESIGN
This part describes an improved implementation of the alldigital PLL. The improved implementation is verified using analog and digital simulation, but not yet manufactured. For the improved implementation, two main goals where set up. 1) The PLL-control shall be independent of the oscillator frequency, i.e a high frequency can be produced if a good DCO is available. 2) The current design is made as a digital design in a schematic netlist editor. A more convenient method is to have a synthesizable VHDL description of the PLL. This makes system simulation including the PLL possible in a digital VHDL simulator and it also makes the design completely process independent. To make the PLL-control independent of the DCO frequency, a new time to digital converter must be implemented. The option here is either to keep the existing counter and clock it with an extra reference oscillator or to make an entire new time to digital converter using a gate delay as reference. Since a gate delay is substantially shorter than the minimum clock period for a counter, the method using gate delay reference is chosen. Figure 10 show the new time to digital converter. It is essentially made of three parts, the gate delay reference (ANDchain), SR-latches to temporary store the result (Storage) and a coder to translate the result into a digital word. Since the optimum loop gain will differ with factors as multiplication factor and DCO resolution, a shifter is also implemented to scale the result.

Figure 7. Step response. Figure 8 shows the power consumption in mW/MHz for the PLL. During this measurement, the power consumption is measured for phase lock at maximum and minimum possible DCO frequency, thereby the two curves of figure 8. The measurement is made for a voltage range of 0.8V to 3V. Figure 9 comes from the same measurement as figure 8. It shows maximum and minimum DCO period time where phase lock is achieved for a voltage range of 0.8V to 3V. The lockrange was found to be equal to the frequency range of the DCO.

Max DCO frequency

Min DCO frequency

EVENT

ANDchain
D(1 to n)

Storage
S(1 to n)
Figure 8. Power consumption.

reset

coder shifter Digital phase error

Figure 10. Time to digital converter.

Figure 11 show the gate delay reference corresponding to ANDchain of figure 10. When the phase error signal EVENT from the phase detector is high, initially, a 1 is passed through the chain of AND-gates. The last gate in the chain is a NAND-gate which output is fed back to the first AND-gate. If EVENT is still high when the output of the NAND-gate change value to 0, a 0 will start to propagate through the AND-gates. The result is an oscillation at each of the nodes D(1) to D(n), which continues until EVENT goes low.
D(1) D(2) D(n-2) D(n-1) D(n)

To obtain correct loop gain, the output from the coder must often be down-shifted, i.e. divided by factors of two. Instead of simply throwing all the least significant bits, the number of bits in the digital filter is increased by two. The two extra bits then represents 2-1 and 2-2. This reduces rounding errors for the digital filter. All parts of the PLL except for the DCO is described in synthesizable VHDL-code. Since the DCO is dependent on the tri-state gates for functionality, exact selection of which tristate gate to use is crucial. A netlist description is therefore more suitable for the DCO. Furthermore, a full custom implementation is likely to be used for the DCO, since the performance of the PLL then can be substantially improved.

8. CONCLUSIONS
EVENT
Figure 11. Chain of AND-gates. To perform a time measurement, it is essential to store the state of ANDchain just before EVENT goes low. To do this, an SR-latch is attached to each of the signals D(1) to D(n) (see figure 12). As long as both signals EVENT and reset are high, S(k) is equal to D(k). When EVENT goes low, the current value of S(k) is preserved until reset goes low. In the coder of figure 10 a counter is attached to the output of the last storage element (S(n)). The result from this counter together with the phase of ANDchain gives a digitalized time measurement. The new time to digital converter is verified in analog simulations to have a resolution of 250ps with minimum sized AND-gates in ANDchain.
D(k) S(k)

A prototype of a standard-cell all-digital PLL clock multiplier is designed and manufactured using a 0.35m CMOS process. The all-digital PLL has a frequency range of 152MHz-366MHz at 3V supply and occupies about 0.07mm2 of on-chip area. Instead of a charge pump and an analog filter, a counter and a recursive digital filter is used as a loop filter. A digitally controlled oscillator with is made from a ring oscillator with additional tri-state gates. The digital PLL is implemented using cells found in an ordinary standard-cell library, which makes it portable between technologies. For the next version of a VHDL-described all-digital PLL, an new time to digital converter, which uses gate delay reference is proposed. The PLL control loop then becomes independent of the high frequency output from the DCO.

9. REFERENCES
[1] P. Nilsson and M. Torkelson, A Monolitic Digital ClockGenerator for On-Chip Clocking of Custom DSPs, IEEE J. Solid-State Circuits, vol.31, No. 5, pp. 700-706, May. 1996. [2] T. Olsson , P. Nilsson, T. Meincke, A. Hemani and M. Torkelson. A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs, In Proceedings of ISCAS2000, Geneva, May 2000. [3] R. E. Best, Phase-locked loops, McGraw-Hill, 1984.

EVENT
reset

Figure 12. Storage element made from a SR-latch.