KI Ế NTR Ú CM Á YT Í NH CE2010

dce
2010
KIN TRC MY TNH CE2010

BK
TP.HCM
Khoa Khoa hc v K thut My tnh BM K thut My tnh inh c Anh V http://www.cse.hcmut.edu.vn/~anhvu

2010, Dr. Dinh Duc Anh Vu
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Instructions: Language of the Computer
Computer Architecture, Chapter 2
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Computer Architecture Is
the attributes of a [computing] system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, 1964
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CAs Changing Definition

1950s to 1960s: Computer Architecture Course = Computer Arithmetic 1970s to mid 1980s: Computer Architecture Course = Instruction Set Design, especially ISA appropriate for compilers 1990s: Computer Architecture Course = Design of CPU, memory system, I/O system, Multiprocessors
Computer Architecture, Chapter 2 2010, Dr. Dinh Duc Anh Vu 4
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The Instruction Set Architecture (ISA)

software
instruction set architecture
hardware
The interface description separating the software and hardware

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Evolution of Instruction Sets

Single Accumulator (EDSAC 1950) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953) Separation of Programming Model from Implementation
High-level Language Based (B5000 1963)
Concept of a Family (IBM 360 1964)
General Purpose Register Machines Complex Instruction Sets (Vax, Intel 432 1977-80) Load/Store Architecture (CDC 6600, Cray 1 1963-76) RISC (Mips,Sparc,HP-PA,IBM RS6000,PowerPC . . .1987) LIW/EPIC?
(IA-64. . .1999)
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Example: C := A + B
add C, A, B
Accumulator
load A add B store C #accum = M[A]; #accum += M[B]; #M[C] = accum; #M[C] = M[A] + M[B]; #R1 = M[A]; #R1 = R1 + M[B]; #M[C] = R1; #R1 = M[A]; #R2 = M[B]; #R3 = R1 + R2; #M[C] = R3;
Memory Memory
add C,A, B
Memory Register
load R1, A add R1,B store C,R1
Register Register
load R1,A load R2,B add R3,R1,R2 store C,R3
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Major advances in computer architecture are typically associated with landmark instruction set designs
Ex: Stack vs GPR (System 360)
Design decisions must take into account:

technology machine organization programming languages compiler technology operating systems applications
And they in turn influence these

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RISC Reduced Instruction Set Computer

RISC philosophy
fixed instruction lengths load-store instruction sets limited number of addressing modes limited number of operations
MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them CISC (C for complex), e.g., Intel x86
Design goals: speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memory space (embedded systems)
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Instruction Set
The repertoire of instructions of a computer Different computers have different instruction sets
But with many aspects in common
Early computers had very simple instruction sets

Simplified implementation
Many modern computers also have simple instruction sets
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The MIPS Instruction Set

Used as the example throughout the course Stanford MIPS commercialized by MIPS Technologies (www.mips.com) Large share of embedded core market
Applications in consumer electronics, network/storage equipment, cameras, printers,
Typical of many modern ISAs
12
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The MIPS ISA

Instruction Categories
Load/Store Computational Jump and Branch Floating Point
coprocessor
Registers R0 - R31
Memory Management Special

OP OP OP
PC HI LO
3 Instruction Formats: all 32 bits wide

rs rs rt rt jump target
2010, Dr. Dinh Duc Anh Vu 13
rd
shamt immediate
funct
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MIPS (RISC) Design Principles

Simplicity favors regularity
fixed size instructions small number of instruction formats opcode always the first 6 bits
Smaller is faster
limited instruction set limited number of registers in register file limited number of addressing modes
Make the common case fast

arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands
Good design demands good compromises

Same instruction length Single instruction format => 3 instruction formats
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MIPS Instruction Classes Distribution

Frequency of MIPS instruction classes for SPEC2006
Instruction Class Integer Arithmetic Data transfer Logical Cond. Branch Jump 16% 35% 12% 34% 2% Frequency Ft. Pt. 48% 36% 4% 8% 0%
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MIPS Arithmetic Instructions

MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs one operation Each specifies exactly three operands that are all contained in the datapaths register file ($t0,$s1,$s2)
destination source1 op source2
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MIPS Register File

Holds 32 32-bit registers
Two read ports and One write port
Registers are
Faster than main memory
But register files with more locations are slower (e.g., a 64 word file could be as much as 50% slower than a 32 word file) Read/write port increase impacts speed quadratically
Easier for a compiler to use

e.g., (A*B) (C*D) (E*F) can do multiplies in any order vs. stack
Can hold variables so that

code density improves (since register are named with fewer bits than a memory location)
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Aside: MIPS Register Convention

Name $zero $at $v0 - $v1 $a0 - $a3 $t0 - $t7 $s0 - $s7 $t8 - $t9 $k0 - $k1 $gp $sp $fp $ra Register Number 0 1 2-3 4-7 8-15 16-23 24-25 26-27 28 29 30 31 Usage constant 0 (hardware) reserved for assembler returned values arguments temporaries saved values temporaries reserved for operating system global pointer stack pointer frame pointer return addr (hardware) Preserve on call? n.a. n.a. no yes no yes no n.a yes yes yes yes
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Registers vs. Memory

Arithmetic instructions operands must be in registers
Processor Control Datapath
Memory
Devices Network Input Output
Compiler associates variables with registers What about programs with lots of variables?
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Processor Memory Interconnections

Memory is a large, single-dimensional array An address acts as the index into the memory array
Memory read addr/ write addr Processor read data write data
10 101 1 8 4 0
? locations
32 bits
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Accessing Memory
MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 2410)
lw sw $t0, 4($s3) $t0, 8($s3) #load word from memory #store word to memory
The data transfer instruction must specify

where in memory to read from (load) or write to (store) memory address where in the register file to write to (load) or read from (store) register destination (source)
The memory address is formed by summing the constant portion of the instruction and the contents of the second register
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MIPS Memory Addressing

The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register
$s3 holds 8
Memory ...0110 ...0101 ...1100 ...0001 ...0010 ...1000 ...0100 32 bit Data lw sw $t0, 4($s3) $t0, 8($s3) 24 20 16 12 8 4 0 Word Address
#what? is loaded into $t0 #$t0 is stored where?

2010, Dr. Dinh Duc Anh Vu 22
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Compiling with Loads and Stores

Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b
... A[3] A[2] A[1] A[0] ... $s3+12 $s3+8 $s3+4 $s3
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Compiling with a Variable Array Index
Assuming that the base address of array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement ... ... c = A[i] - b
A[3] A[2] A[1] A[0] add add $s4+12 $s4+8 $s4+4 $s4 $t1, $s3, $s3 $t1, $t1, $t1 #array index i is in $s3 #temp reg $t1 holds 4*i
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Dealing with Constants

Small constants are used quite frequently (50% of operands in many common programs)
e.g., A = A + 5; B = B + 1; C = C - 18;
Solutions? Why not?

Put typical constants in memory and load them Create hard-wired registers (like $zero) for constants like 1, 2, 4, 10,
How do we make this work?

How do we Make the common case fast !
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Constant (or Immediate) Operands

Include constants inside arithmetic instructions
Much faster than if they have to be loaded from memory (they come in from memory with the instruction itself)
MIPS immediate instructions

addi $s3, $s3, 4 #$s3 = $s3 + 4
There is no subi instruction, can you guess why not?

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MIPS Instructions, so far

Category Instr Example Meaning
add Arithmetic subtract add immediate Data transfer load word store word
add sub
$s1, $s2, $s3 $s1, $s2, $s3
$s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 4 $s1 = Memory($s2+32) Memory($s2+32) = $s1
addi $s1, $s2, 4 lw sw $s1, 32($s2) $s1, 32($s2)
27

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dce

KIN TRC MY TNH CE2010

Khoa Khoa hc v K thut My tnh BM K thut My tnh inh c Anh V http://www.cse.hcmut.edu.vn/~anhvu

Instructions: Language of the Computer

Computer Architecture, Chapter 2

2010, Dr. Dinh Duc Anh Vu

Computer Architecture, Chapter 2

2010, Dr. Dinh Duc Anh Vu

CAs Changing Definition

The Instruction Set Architecture (ISA)

The interface description separating the software and hardware

Evolution of Instruction Sets

High-level Language Based (B5000 1963)

Concept of a Family (IBM 360 1964)

2010, Dr. Dinh Duc Anh Vu

Evolution of Instruction Sets

Computer Architecture, Chapter 2

Evolution of Instruction Sets

Computer Architecture, Chapter 2

Evolution of Instruction Sets

Design decisions must take into account:

And they in turn influence these

RISC Reduced Instruction Set Computer

Early computers had very simple instruction sets

Many modern computers also have simple instruction sets

Computer Architecture, Chapter 2

2010, Dr. Dinh Duc Anh Vu

The MIPS Instruction Set

Typical of many modern ISAs

Computer Architecture, Chapter 2

2010, Dr. Dinh Duc Anh Vu

The MIPS ISA

Memory Management Special

3 Instruction Formats: all 32 bits wide

MIPS (RISC) Design Principles

Make the common case fast

Good design demands good compromises

MIPS Instruction Classes Distribution

Computer Architecture, Chapter 2

2010, Dr. Dinh Duc Anh Vu

MIPS Arithmetic Instructions

Computer Architecture, Chapter 2

2010, Dr. Dinh Duc Anh Vu

MIPS Register File

Easier for a compiler to use

Can hold variables so that

Aside: MIPS Register Convention

Computer Architecture, Chapter 2

2010, Dr. Dinh Duc Anh Vu

Registers vs. Memory

Processor Control Datapath

Devices Network Input Output

Processor Memory Interconnections

The data transfer instruction must specify

MIPS Memory Addressing

#what? is loaded into $t0 #$t0 is stored where?

Computer Architecture, Chapter 2

Compiling with Loads and Stores