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Xilinx Spartan-3E
Xilinx Spartan-3E
Product Specification
Summary
The Xilinx Automotive (XA) Spartan-3E family of FPGAs is specifically designed to meet the needs of high-volume, cost-sensitive automotive electronics applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in Table 1. - Enhanced Double Data Rate (DDR) support - DDR SDRAM support up to 266 Mb/s Abundant, flexible logic resources - Densities up to 33,192 logic cells, including optional shift register or distributed RAM support - Efficient wide multiplexers, wide logic - Fast look-ahead carry logic - Enhanced 18 x 18 multipliers with optional pipeline - IEEE 1149.1/1532 JTAG programming/debug port Hierarchical SelectRAM memory architecture - Up to 648 Kbits of fast block RAM - Up to 231 Kbits of efficient distributed RAM Up to eight Digital Clock Managers (DCMs) - Clock skew elimination (delay locked loop) - Frequency synthesis, multiplication, division - High-resolution phase shifting - Wide frequency range (5 MHz to over 300 MHz) Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing Configuration interface to industry-standard PROMs - Low-cost, space-saving SPI serial Flash PROM - x8 or x8/x16 parallel NOR Flash PROM Complete Xilinx ISE and WebPACK software support MicroBlaze and PicoBlaze embedded processor cores Fully compliant 32-/64-bit 33 MHz PCI technology support Low-cost QFP and BGA packaging options - Common footprints support easy density migration
Introduction
XA devices are available in both extended-temperature Q-Grade (40C to +125C TJ) and I-Grade (40C to +100C TJ) and are qualified to the industry recognized AEC-Q100 standard. The XA Spartan-3E family builds on the success of the earlier XA Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These XA Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, XA Spartan-3E FPGAs are ideally suited to a wide range of automotive applications, including infotainment, driver information, and driver assistance modules. The XA Spartan-3E family is a superior alternative to mask programmed ASICs and ASSPs. FPGAs avoid the high initial mask set costs and lengthy development cycles, while also permitting design upgrades in the field with no hardware replacement necessary because of its inherent programmability, an impossibility with conventional ASICs and ASSPs with their inflexible hardware architecture.
Features
Very low-cost, high-performance logic solution for high-volume automotive applications Proven advanced 90-nanometer process technology Multi-voltage, multi-standard SelectIO interface pins - Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling - 622+ Mb/s data transfer rate per I/O - True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O
Refer to Spartan-3E FPGA Family: Complete Data Sheet (DS312) for a full product description, AC and DC specifications, and package pinout descriptions. Any values shown specifically in this XA Spartan-3E Automotive FPGA Family data sheet override those shown in DS312. For information regarding reliability qualification, refer to RPT081 (Xilinx Spartan-3E Family Automotive Qualification Report) and RPT012 (Spartan-3/3E UMC-12A 90 nm Qualification Report).
20072009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Notes:
1.
By convention, one Kb is equivalent to 1,024 bits.
Architectural Overview
The XA Spartan-3E family architecture consists of five fundamental programmable functional elements: Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including four high-performance differential standards. Double Data-Rate (DDR) registers are included. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.
These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XA3S100E, which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XA3S100E has only one DCM at the top and bottom, while the XA3S1200E and XA3S1600E add two DCMs in the middle of the left and right sides. The XA Spartan-3E family features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing.
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Notes:
1. The XA3S1200E and XA3S1600E have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XA3S100E has only one DCM at the top and one at the bottom.
Configuration
XA Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGAs configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or x8/x16 parallel NOR Flash Slave Serial, typically downloaded from a processor Slave Parallel, typically downloaded from a processor Boundary Scan (JTAG), typically downloaded from a processor or system tester.
I/O Capabilities
The XA Spartan-3E FPGA SelectIO interface supports many popular single-ended and differential standards. Table 2 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. XA Spartan-3E FPGAs support the following single-ended standards: 3.3V low-voltage TTL (LVTTL) Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V 3V PCI at 33 MHz HSTL I and III at 1.8V, commonly used in memory applications SSTL I at 1.8V and 2.5V, commonly used for memory applications
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XA Spartan-3E FPGAs support the following differential standards: LVDS Bus LVDS mini-LVDS RSDS
Differential HSTL (1.8V, Types I and III) Differential SSTL (2.5V and 1.8V, Type I) 2.5V LVPECL inputs
CPG132 8x8 User 83 (11) 92 (7) 92 (7) Diff 35 (2) 41 (2) 41 (2) -
FTG256 17 x 17 User 172 (40) 190 (41) 190 (40) Diff 68 (8) 77 (8) 77 (8) -
FGG400 21 x 21 User 304 (72) 304 (72) Diff 124 (20) 124 (20)
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Package Marking
Figure 2 provides a top marking example for XA Spartan-3E FPGAs in the quad-flat packages. Figure 3 shows the top marking for XA Spartan-3E FPGAs in BGA packages except the 132-ball chip-scale package (CPG132). The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. Figure 4 shows the top marking for XA Spartan-3E FPGAs in the CPG132 package. Note: No marking is shown for stepping.
Mask Revision Code Fabrication Code
R
SPARTAN
Device Type Package Speed Grade Temperature Range
Pin P1
DS635-1_02_082807
SPARTAN
Package C6 = CPG132
C6AGQ
4I
Speed Grade Process Code Fabrication Code
DS635_04_082807
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Ordering Information
XA Spartan-3E FPGAs are available in Pb-free packaging options for all device/package combinations. All devices are in Pb-free packages only, with a G character to the ordering code. All devices are available in either I-Grade or Q-Grade temperature ranges. Only the -4 speed grade is available for the XA Spartan-3E family. See Table 2 for valid device/package combinations.
Pb-Free Packaging
Example:
Device Type Speed Grade Package Type
XA3S250E -4 FT G 256 I
Temperature Range: I = I-Grade (TJ = 40oC to 100oC) Q = Q-Grade (TJ = 40oC to 125oC) Number of Pins Pb-free
DS635_06_121608
Speed Grade -4 Only VQG100 CPG132 TQG144 PQG208 FTG256 FGG400 FGG484
Package Type / Number of Pins 100-pin Very Thin Quad Flat Pack (VQFP) 132-ball Chip-Scale Package (CSP) 144-pin Thin Quad Flat Pack (TQFP) 208-pin Plastic Quad Flat Pack (PQFP) 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) 400-ball Fine-Pitch Ball Grid Array (FBGA) 484-ball Fine-Pitch Ball Grid Array (FBGA)
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Description Threshold for the VCCINT supply Threshold for the VCCAUX supply Threshold for the VCCO Bank 2 supply
Units V V V
Description Ramp rate from GND to valid VCCINT supply level Ramp rate from GND to valid VCCAUX supply level Ramp rate from GND to valid VCCO Bank 2 supply level
Max 50 50 50
Units ms ms ms
Table 5: Supply Voltage Levels Necessary for Preserving RAM Contents Symbol VDRINT VDRAUX
Notes:
1. RAM contents include configuration data.
Description VCCINT level required to retain RAM data VCCAUX level required to retain RAM data
Units V V
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DC Specifications
Table 6: General Recommended Operating Conditions Symbol TJ VCCINT VCCO
(1)
Description Junction temperature Internal supply voltage Output driver supply voltage Auxiliary supply voltage Voltage variance on VCCAUX when using a DCM Input voltage extremes to avoid turning on I/O protection diodes Input signal transition time(7) I/O, Input-only, and Dual-Purpose pins(3) Dedicated pins(4) I-Grade Q-Grade
Max 100 125 1.260 3.465 2.625 10 VCCO + 0.5 VCCAUX + 0.5 500
Units C C V V V mV/ms V V ns
VCCAUX VCCAUX
(2)
VIN(3,4,5,6)
TIN
Notes:
1. 2. 3.
4. 5. 6. 7.
This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 9 lists the recommended VCCO range specific to each of the single-ended I/O standards, and Table 11 lists that specific to the differential standards. Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks VCCO rails. Meeting the VIN limit ensures that the internal diode junctions that exist between these pins and their associated VCCO and GND rails do not turn on. See Absolute Maximum Ratings in DS312). All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCAUX and GND rails do not turn on. Input voltages outside the recommended range is permissible provided that the IIK input clamp diode rating is met and no more than 100 pins exceed the range simultaneously. See Absolute Maximum Ratings in DS312). See XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins." Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.
IRPU(2)
0.36 0.22 0.10 0.06 0.04 2.4 2.7 4.3 5.0 5.5
1.24 0.80 0.42 0.27 0.22 10.8 11.8 20.2 25.9 32.0
mA mA mA mA mA k k k k k
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Table 7: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued) Symbol IRPD(2) Description Current through pull-down resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins Equivalent pull-down resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPD per Note 2) Test Conditions VIN = VCCO Min 0.10 Typ Max 0.75 Units mA
RPD(2)
VIN = VCCO = 3.0V to 3.45V VIN = VCCO = 2.3V to 2.7V VIN = VCCO = 1.7V to 1.9V VIN = VCCO = 1.4V to 1.6V VIN = VCCO = 1.14V to 1.26V
120
k k k k k A pF
VREF current per pin Input capacitance Resistance of optional differential termination circuit within a differential I/O pair. Not available on Input-only pairs.
All VCCO levels VOCM Min VICM VOCM Max VOD Min VID VOD Max VCCO = 2.5V
Notes:
1. 2. The numbers in this table are based on the conditions set forth in Table 6. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
Table 8: Quiescent Supply Current Characteristics Symbol ICCINTQ Description Quiescent VCCINT supply current Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E ICCOQ Quiescent VCCO supply current XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E I-Grade Maximum 36 104 145 324 457 1.5 1.5 1.5 2.5 2.5 Q-Grade Maximum 58 158 300 500 750 2.0 3.0 3.0 4.0 4.0 Units mA mA mA mA mA mA mA mA mA mA
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Table 8: Quiescent Supply Current Characteristics (Continued) Symbol ICCAUXQ Description Quiescent VCCAUX supply current Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E
Notes:
1. 2. The numbers in this table are based on the conditions set forth in Table 6. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical devices at room temperature (TJ of 25C at VCCINT = 1.2 V, VCCO = 3.3V, and VCCAUX = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.465V, and VCCAUX = 2.625V. The FPGA is programmed with a blank configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements), measured quiescent current levels may be different than the values in the table. For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3E XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
I-Grade Maximum 13 26 34 59 86
Units mA mA mA mA mA
3. 4.
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VCCO for Drivers(2) Min (V) 3.0 3.0 2.3 1.65 1.4 1.1 3.0 1.7 1.7 1.7 2.3 Nom (V) 3.3 3.3 2.5 1.8 1.5 1.2 3.3 1.8 1.8 1.8 2.5 Max (V) 3.465 3.465 2.7 1.95 1.6 1.3 3.465 1.9 1.9 1.9 2.7 0.8 0.833 1.15 Min (V)
VIH Min (V) 2.0 2.0 1.7 0.8 0.8 0.7 0.5 * VCCO VREF + 0.1 VREF + 0.1 VREF + 0.125 VREF + 0.125
2. 3. 4. 5.
6.
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Logic Level Characteristics VOL Max (V) 0.4 VOH Min (V) 2.4
Logic Level Characteristics VOL Max (V) 0.4 10% VCCO 0.4 0.4
VTT 0.475
IOH
(mA)
IOH
(mA)
VOH Min (V) VCCO - 0.4 90% VCCO VCCO - 0.4 VCCO - 0.4
VTT + 0.475
2 4 6 8 12 16 2 4 6 8 12 16 2 4 6 8 12 2 4 6 8 2 4 6
2 4 6 8 12 16 2 4 6 8 12 16 2 4 6 8 12 2 4 6 8 2 4 6
VTT 0.61
VTT + 0.61
0.4
VCCO 0.4
Notes:
1. 2. The numbers in this table are based on the conditions set forth in Table 6 and Table 9. Descriptions of the symbols used in this table are as follows:
IOL the output current condition under which VOL is tested IOH the output current condition under which VOH is tested VOL the output voltage that indicates a Low logic level VOH the output voltage that indicates a High logic level VCCO the supply voltage for output drivers VTT the voltage applied to a resistor termination
0.4
VCCO 0.4
3. 4.
For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes. Tested according to the relevant PCI specifications. For information on PCI IP solutions, see www.xilinx.com/pci.
0.4
VCCO 0.4
0.4
VCCO 0.4
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IOSTANDARD Attribute
LVDS_25 BLVDS_25 MINI_LVDS_25 LVPECL_25(2) RSDS_25 DIFF_HSTL_I_18 DIFF_HSTL_III_18 DIFF_SSTL18_I DIFF_SSTL2_I Notes:
1. 2.
The VCCO rails supply only differential output drivers, not input circuits. VREF inputs are not used for any of the differential I/O standards.
VOD Max (mV) 450 450 600 400 Min (mV) Max (mV) 50 Min (V) 1.125 1.0 1.1
VTT + 0.61
VTT 0.61
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VCCO = 2.5V
Z0 = 50 100
VCCO = 2.5V
Z0 = 50
DS635_05_082807
Figure 5: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver
Switching Characteristics
I/O Timing
Table 13: Pin-to-Pin Clock-to-Output Times for the IOB Output Path -4 Speed Grade Symbol Clock-to-Output Times TICKOFDCM When reading from the Output Flip-Flop (OFF), the time from the active transition on the Global Clock pin to data appearing at the Output pin. The DCM is used. LVCMOS25(2), 12mA output drive, Fast slew rate, with DCM(3)
XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E
Description
Conditions
Device
Max
Units
2.79 3.45 3.46 3.46 3.45 5.92 5.43 5.51 5.94 6.05
ns ns ns ns ns ns ns ns ns ns
TICKOF
When reading from OFF, the time from the active transition on the Global Clock pin to data appearing at the Output pin. The DCM is not used.
Notes:
1. 2. 3. 4. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate Input adjustment from Table 17. If the latter is true, add the appropriate Output adjustment from Table 18. DCM output jitter is included in all measurements. For minimums, use the values reported by the Xilinx timing analyzer.
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Table 14: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
IFD_ DELAY_ VALUE= 0 -4 Speed Grade Device XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E LVCMOS25(2), IFD_DELAY_VALUE = default software setting 2 3 2 5 4 Hold Times TPHDCM When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is used. No Input Delay is programmed. When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is not used. The Input Delay is programmed. LVCMOS25(3), IFD_DELAY_VALUE = 0, with DCM(4) 0 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E LVCMOS25(3), IFD_DELAY_VALUE = default software setting 2 3 2 5 4 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E 0.52 0.14 0.14 0.15 0.14 0.24 0.32 0.49 0.63 0.39 ns ns ns ns ns ns ns ns ns ns XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E Min 2.98 2.59 2.59 2.58 2.59 3.58 3.91 4.02 5.52 4.46 Units ns ns ns ns ns ns ns ns ns ns
Description When writing to the Input Flip-Flop (IFF), the time from the setup of data at the Input pin to the active transition at a Global Clock pin. The DCM is used. No Input Delay is programmed. When writing to IFF, the time from the setup of data at the Input pin to an active transition at the Global Clock pin. The DCM is not used. The Input Delay is programmed.
TPSFD
TPHFD
Notes:
1. 2. 3. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 17. If this is true of the data Input, add the appropriate Input adjustment from the same table. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 17. If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clocks active edge. DCM output jitter is included in all measurements.
4.
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Table 15: Setup and Hold Times for the IOB Input Path
IFD_ DELAY_ VALUE -4 Speed Grade Device Min Units
Description
Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). No Input Delay is programmed. Time from the setup of data at the Input pin to the active transition at the IFFs ICLK input. The Input Delay is programmed.
All
2.12
ns
TIOPICKD
2 3 2 5 4
ns ns ns ns ns
Hold Times TIOICKP Time from the active transition at the IFFs ICLK input to the point where data must be held at the Input pin. No Input Delay is programmed. Time from the active transition at the IFFs ICLK input to the point where data must be held at the Input pin. The Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = 0 0 All 0.76 ns
TIOICKPD
2 3 2 5 4
ns ns ns ns ns
All
1.80
ns
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Table 16: Propagation Times for the IOB Input Path IFD_ DELAY_ VALUE -4 Speed Grade Device Max Units
Description
Conditions
The time it takes for data to travel from the Input pin through the IFF latch to the I output with no input delay programmed The time it takes for data to travel from the Input pin through the IFF latch to the I output with the input delay programmed
LVCMOS25(2), IFD_DELAY_VALUE = 0
All
2.25
ns
TIOPLID
2 3 2 5 4
ns ns ns ns ns
Notes:
1. 2. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from Table 17.
Table 17: Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 HSTL_I_18 HSTL_III_18 SSTL18_I SSTL2_I 0.43 0.43 0 0.98 0.63 0.27 0.42 0.12 0.17 0.30 0.15 ns ns ns ns ns ns ns ns ns ns ns Add the Adjustment Below -4 Speed Grade Units
Table 17: Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Differential Standards LVDS_25 BLVDS_25 MINI_LVDS_25 LVPECL_25 RSDS_25 DIFF_HSTL_I_18 DIFF_HSTL_III_18 DIFF_SSTL18_I DIFF_SSTL2_I Notes:
1. 2. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6, Table 9, and Table 11. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards.
ns ns ns ns ns ns ns ns ns
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Add the Adjustment Below -4 Speed Grade 5.24 3.21 2.49 1.90 4.15 2.13 1.14 0.75 4.68 3.97 3.11 3.38 2.70 1.53 6.63 4.44 0.34 0.55 0.46 0.25 0.20 0.55 0.04 0.56 Input Only 0.48 0.42 0.55 0.40 0.44 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Slow Fast
2 mA 2 mA
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Inputs VREF (V) VL (V) 0 0 0 0 0 0 Note 3 VH (V) 3.3 3.3 2.5 1.8 1.5 1.2 Note 3 RT () 1M 1M 1M 1M 1M 1M 25 25 0.9 1.1 0.9 1.25 VREF 0.5 VREF 0.5 VREF 0.5 VREF 0.75 VICM 0.125 VICM 0.125 VICM 0.125 VICM 0.3 VICM 0.1 VREF 0.5 VREF 0.5 VREF 0.5 VREF 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.75 VICM + 0.125 VICM + 0.125 VICM + 0.125 VICM + 0.3 VICM + 0.1 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 50 50 50 50
Inputs and Outputs VM (V) 1.4 1.65 1.25 0.9 0.75 0.6 0.94 2.03 VREF VREF VREF VREF VICM VICM VICM VICM VICM VICM VICM VICM VICM
50 1M 50 1M 50 50 50 50 50
2. 3.
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Propagation Times TILO The time it takes for data to travel from the CLBs F (G) input to the X (Y) output 0.76 ns
The minimum allowable pulse width, High or Low, to the CLBs SR input
1.80
ns
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Table 21: CLB Distributed RAM Switching Characteristics -4 Symbol Clock-to-Output Times TSHCKO Setup Times TDS TAS TWS Hold Times TDH TAH, TWH Hold time of the BX, BY data inputs after the active transition at the CLK input of the distributed RAM Hold time of the F/G address inputs or the write enable input after the active transition at the CLK input of the distributed RAM 0.15 0 ns ns Setup time of data at the BX or BY input before the active transition at the CLK input of the distributed RAM Setup time of the F/G address inputs before the active transition at the CLK input of the distributed RAM Setup time of the write enable input before the active transition at the CLK input of the distributed RAM 0.46 0.52 0.40 ns ns ns Time from the active edge at the CLK input to data appearing on the distributed RAM output 2.35 ns Description Min Max Units
Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input 1.01 ns
Table 22: CLB Shift Register Switching Characteristics -4 Symbol Clock-to-Output Times TREG Setup Times TSRLDS Hold Times TSRLDH Hold time of the BX or BY data input after the active transition at the CLK input of the shift register 0.16 ns Setup time of data at the BX or BY input before the active transition at the CLK input of the shift register 0.46 ns Time from the active edge at the CLK input to data appearing on the shift register output 4.16 ns Description Min Max Units
Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input 1.01 ns
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Clock-to-Output Times TMSCKP_P TMSCKP_A TMSCKP_B Setup Times TMSDCK_P Data setup time at the A or B input before the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(2) Data setup time at the A input before the active transition at the CLK when using the AREG input register(3) Data setup time at the B input before the active transition at the CLK when using the BREG input register(3) 3.98 ns Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using the PREG register(2) Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using either the AREG or BREG register(3) 1.10 ns
4.97
ns
0.23 0.39
ns ns
Data hold time at the A or B input before the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(2) Data hold time at the A input before the active transition at the CLK when using the AREG input register(3) Data hold time at the B input before the active transition at the CLK when using the BREG input register(3)
-0.97
TMSCKD_A TMSCKD_B
0.04 0.05
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Table 24: 18 x 18 Embedded Multiplier Timing (Continued) -4 Speed Grade Symbol Clock Frequency FMULT
Notes:
1. 2. 3. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
Description
Min
Max
Units
Internal operating frequency for a two-stage 18x18 multiplier using the AREG and BREG input registers and the PREG output register(1)
240
MHz
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Table 25: Block RAM Timing (Continued) -4 Speed Grade Symbol Clock Timing TBPWH TBPWL High pulse width of the CLK signal Low pulse width of the CLK signal 1.59 1.59 ns ns Description Min Max Units
Clock Frequency FBRAM Block RAM clock frequency. RAM read output value written back into RAM, for shift registers and circular buffers. Write-only or read-only performance is faster. 0 230 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as they meet the input requirements. The DLL will track the frequency changes created by the spread spectrum clock to drive the global clocks to the FPGA logic. See XAPP469, Spread-Spectrum Clocking Reception for Displays for details.
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Delay-Locked Loop
Table 26: Recommended Operating Conditions for the DLL
-4 Speed Grade Symbol Input Frequency Ranges FCLKIN CLKIN_FREQ_DLL Frequency of the CLKIN clock input 5(2) 240(3) MHz Description Min Max Units
Input Pulse Requirements CLKIN_PULSE CLKIN pulse width as a percentage of the CLKIN period FCLKIN < 150 MHz FCLKIN > 150 MHz 40% 45% 60% 55% -
Input Clock Jitter Tolerance and Delay Path Variation(4) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_DLL_HF CLKIN_PER_JITT_DLL CLKFB_DELAY_VAR_EXT Notes:
1. 2. 3. 4. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 28. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
Cycle-to-cycle jitter at the CLKIN input Period jitter at the CLKIN input
300 150 1 1
ps ps ns ns
Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input
CLKOUT_PER_JITT_DV1 CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing integer division Period jitter at the CLKDV output when performing non-integer division
ps ps
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CLKOUT_DUTY_CYCLE_DLL
Phase Alignment(4) CLKIN_CLKFB_PHASE CLKOUT_PHASE_DLL Phase offset between the CLKIN and CLKFB inputs Phase offset between DLL outputs CLK0 to CLK2X (not CLK2X180) All others 200 [1% of CLKIN period + 100] [1% of CLKIN period + 200] ps ps
ps
Lock Time LOCK_DLL(3) When using the DLL alone: The time from deassertion at the DCMs Reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase 5 MHz < FCLKIN < 15 MHz FCLKIN > 15 MHz 5 600 ms s
Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 26. 2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. 3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum jitter of [1% of CLKIN period + 150]. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250ps.
Description
Min
Max
Units
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See Note 4 [1% of CLKFX period + 100] [1% of CLKFX period + 200]
Duty Cycle(5,6) CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs, including the BUFGMUX and clock tree duty-cycle distortion All [1% of CLKFX period + 400] ps
Phase Alignment(6) CLKOUT_PHASE_FX CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX output and the DLL CLK0 output when both the DFS and DLL are used Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used All All 200 [1% of CLKFX period + 300] ps ps
Lock Time LOCK_FX(2) The time from deassertion at the DCMs Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are valid. If using both the DLL and the DFS, use the longer locking time. 5 MHz < FCLKIN < 15 MHz FCLKIN > 15 MHz All 5 450 ms s
Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 28. 2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 3. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching). Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application. 4. Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter. Use the Clocking Wizard to determine jitter for a specific design. 5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle. 6. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter of [1% of CLKFX period + 300]. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 300 ps] = 400 ps.
Phase Shifter
Table 30: Recommended Operating Conditions for the PS in Variable Phase Mode
-4 Speed Grade Symbol Operating Frequency Ranges PSCLK_FREQ (FPSCLK) Frequency for the PSCLK input 1 167 MHz Description Min Max Units
Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period 40% 60% -
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FINE_SHIFT_RANGE_MIN FINE_SHIFT_RANGE_MAX
ns ns
Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 30. 2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT attribute is set to 0. 3. The DCM_DELAY_STEP values are provided at the bottom of Table 27.
Notes:
1. 2. 3. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. This specification is equivalent to the Virtex-4 DCM_RESET specification. This specification does not apply for Spartan-3E FPGAs. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.
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Notes:
1. 2. 3. The numbers in this table are based on the operating conditions set forth in Table 6. This means power must be applied to all VCCINT, VCCO, and VCCAUX lines. Power-on reset and the clearing of configuration memory occurs during this period. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
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Temperature Range I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade
Units ns ns ns ns ns ns
Table 35: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol FCCLK1 FCCLK3 FCCLK6 FCCLK12 FCCLK25 FCCLK50 Description Equivalent CCLK clock frequency by ConfigRate setting ConfigRate Setting 1 (power-on value and default value) 3 6 12 25 50 Temperature Range I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade I-Grade Q-Grade Minimum 0.8 1.6 3.2 6.4 12.8 25.6 Maximum 2.1 4.2 8.3 16.5 33.0 66.0 Units MHz MHz MHz MHz MHz MHz
Table 36: Master Mode CCLK Output Minimum Low and High Time Symbol TMCCL, TMCCH Description Master mode CCLK minimum Low and High time I-Grade Q-Grade ConfigRate Setting 1 235 3 117 6 58 12 29.3 25 14.5 50 7.3 Units ns
Table 37: Slave Mode CCLK Input Low and High Time Symbol TSCCL, TSCCH CCLK Low and High time Description Min 5 Max Units ns
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Description
The time from the falling transition on the CCLK pin to data appearing at the DOUT pin
Both
1.5
10.0
ns
Setup Times TDCC The time from the setup of data at the DIN pin to the active edge of the CCLK pin Both 11.0 ns
Hold Times TCCD The time from the active edge of the CCLK pin to the point when data is last held at the DIN pin Both 0 ns
Clock Timing TCCH High pulse width at the CCLK input pin Master Slave TCCL Low pulse width at the CCLK input pin Master Slave FCCSER Frequency of the clock signal at the CCLK input pin No bitstream compression With bitstream compression Slave 0 0 See Table 36 See Table 37 See Table 36 See Table 37 66(2) 20 MHz MHz
Notes:
1. 2. The numbers in this table are based on the operating conditions set forth in Table 6. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
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The numbers in this table are based on the operating conditions set forth in Table 6. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification. Some Xilinx documents refer to Parallel modes as SelectMAP modes.
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Table 41: Configuration Timing Requirements for Attached SPI Serial Flash Symbol TCCS TDSU TDH TV fC or fR Description SPI serial Flash PROM chip-select time SPI serial Flash PROM data input setup time SPI serial Flash PROM data input hold time Requirement Units ns ns ns
T CCS T MCCL1 T CCO T DSU T MCCL1 T CCO T DH T MCCH1 T V T MCCLn T DCC 1 f C -----------------------------T CCLKn ( min )
ns
Maximum SPI serial Flash PROM clock frequency (also depends on specific read command used)
MHz
Notes:
1. 2. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source. Subtract additional printed circuit board routing delay as required by the application.
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Description
Minimum
Maximum
Units
(see Table 34) (see Table 34) 50 0 5 2 5 2 See Table 38 See Table 38 See Table 38 ns ns TCCLK1 cycles
Address A[23:0] outputs valid after CCLK falling edge Setup time on D[7:0] data inputs before CCLK rising edge Hold time on D[7:0] data inputs after CCLK rising edge
Table 43: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol TCE (tELQV) TOE (tGLQV) TACC (tAVQV) TBYTE (tFLQV, tFHQV)
Notes:
1. 2. 3. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source. Subtract additional printed circuit board routing delay as required by the application. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGAs LDC2 pin. The resistor value also depends on whether the FPGAs HSWAP pin is High or Low.
Description Parallel NOR Flash PROM chip-select time Parallel NOR Flash PROM output-enable time Parallel NOR Flash PROM read access time For x8/x16 PROMs only: BYTE# to output valid time(3)
Requirement
Units ns
T CE T INITADDR T OE T INITADDR T ACC 0.5T CCLKn ( min ) T CCO T DCC PCB T BYTE T INITADDR
ns
ns
ns
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The High pulse width at the TCK pin The Low pulse width at the TCK pin Frequency of the TCK signal
5 5 -
25
ns ns MHz
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Revision History
The following table shows the revision history for this document.
Revision
Updated "Key Feature Differences from Commercial XC Devices." Updated TACC requirement in Table 43. Updated description of TDCC and TCCD in Table 42. Removed Table 45: MultiBoot Trigger Timing. Added package sizes to Table 2, page 4. Removed Genealogy Viewer Link from "Package Marking," page 5. Updated data and notes for Table 6, page 8. Updated test conditions for RPU and maximum value for CIN in Table 7, page 8. Updated notes for Table 8, page 9. Updated Max VCCO for LVTTL and LVCMOS33, removed PCIX data, updated VIL Max for LVCMOS18, LVCMOS15, and LVCMOS12, updated VIH Min for LVCMOS12, and added note 6 in Table 9, page 11. Removed PCIX data, revised note 2, and added note 4 in Table 10, page 12. Updated figure description of Figure 5, page 14. Added note 4 to Table 13, page 14. Removed PC166_3 and PCIX adjustment values from Table 17, page 17. Deleted Table 18 (duplicate of Table 17, page 17). Subsequent tables renumbered. Removed PCIX data Table 18, page 18. Removed PCIX data and removed VREF values for DIFF_HSTL_I_18, DIFF_HSTL_III_18, DIFF_SSTL18_I, and DIFF_SSTL2_I from Table 19, page 19. Updated TDICK minimum setup time in Table 20, page 20. Updated notes, references to notes, and revised the maximum clock-to-output times for TMSCKP_P Table 24, page 22. Added "Spread Spectrum," page 24. Updated note 3 in Table 26, page 25. Added note 4 Table 28, page 26. Updated notes, references to notes, and CLKOUT_PER_JITT_FX data in Table 29, page 27. Updated MAX_STEPS data in Table 31, page 28. Updated ConfigRate Setting for TCCLK1 to indicate 1 is the default value in Table 34, page 30. Updated ConfigRate Setting for FCCLK1 to indicate 1 is the default value in Table 35, page 30.
09/09/09
2.0
Notice of Disclaimer
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