Digital Design

Outlines

Historical Perspectives Progresses in Semiconductor Industry Digital Design Metrics

Nitin Chaturvedi

Outlines

Historical Perspectives Progresses in Semiconductor Industry Digital Design Metrics

Nitin Chaturvedi

Major Challenges in Digital Designs

DSM
Microscopic Problems
Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution.

1/DSM
Macroscopic Issues
Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc.

Everything Looks a Little Different

and Theres a Lot of Them!

Nitin Chaturvedi

Design in Deep Submicron

Design in the deep submicron (DSM) era creates new challenges

Devices become somewhat different Global clocking becomes more challenging Interconnect effects play a more significant role Power dissipation may be the limiting factor

We must understand and be able to design digital ICs in advanced technologies (at or below 180 nm)

Nitin Chaturvedi

Design Metrics

How to evaluate performance of a digital circuit (gate, block, )?

Cost (Yield) Reliability (Noise Immunity) Scalability (Fan-In, Fan-out) Speed (delay, operating frequency) Power dissipation Energy to perform a function

Nitin Chaturvedi

Cost of Integrated Circuits

NRE (non-recurrent engineering) costs

design time and effort, mask generation one-time cost factor

Recurrent costs
silicon processing, packaging, test proportional to volume proportional to chip area

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NRE Cost is increasing

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Die Cost
Single Die

Wafer

Going up to 12 (30cm)
From http://www.amd.com
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Cost Per Transistor

(-per-transistor) 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

Cost

Fabrication capital cost per transistor (Moores law)

Year
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Yield
No . of good chips per wafer Y= 100 Total number of chips per wafer

Wafer cost Die cost= Dies per wafer Die yield

p ( Wafer diameter/2 ) p Wafer diameter Dies per wafer= Die area 2 Die area
2

Nitin Chaturvedi

Some Examples (in 1994)

Chip
386DX 486 DX2 Power PC 601 HP PA 7100 DEC Alpha Super Sparc Pentium

Metal Line layers width

Wafer cost

Def./ Area Dies/ Yield cm2 mm2 wafer

Die cost

2 3 4 3 3 3 3

0.90 0.80 0.80 0.80 0.70 0.70 0.80

$900 $1200 $1700 $1300 $1500 $1700 $1500

1.0 1.0 1.3 1.0 1.2 1.6 1.5

43 81 121 196 234 256 296

360 181 115 66 53 48 40

71% 54% 28% 27% 19% 13% 9%

$4 $12 $53 $73 $149 $272 $417

Nitin Chaturvedi

Reliability
Noise in Digital Integrated Circuits

i(t)

v(t)

V DD

Inductive coupling

Capacitive coupling

Power and ground noise

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Voltage Transfer Characteristics

V(y)
V f V(y)=V(x)

OH

VOH = f(VOL) VOL = f(VOH) VM = f(VM)

VM Switching Threshold V OL V OL V OH

DC Operations
V(x)

Nominal Voltage Levels

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Mapping between Analog and Digital

1
V OH V IH

out OH Slope = -1

Undefined Region
V IL OL

Slope = -1 V OL V IL V IH V in

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Definition of Noise Margins

"1" V OH NM H

Noise margin high

IH Undefined Region

V OL "0"

NM L

IL

Noise margin low

Gate Output

Gate Input

Nitin Chaturvedi

Key Reliability Properties

Absolute noise margin values are deceptive.

A floating node is more easily disturbed than a node

driven by a low impedance (in terms of voltages)

Noise Immunity is the more important metric

The capability to suppress noise sources

(Regenerative property)

Key metric:
Noise transfer functions, Output impedance of the driver, and Input impedance of the receiver.

Nitin Chaturvedi

Regenerative Property
v0 v 1 v2 v 3 v 4 v 5 v 6

A chain of inverters

Ability to recover a corrupted signal to a well-defined digital signal

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Regenerative Property I
Vout Vout

v3

f(v)
v1

finv(v)

v1

finv(v)

v3

f(v)

v2

v0

Vin

v0

v2

Vin

Regenerative
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Non-Regenerative

Fan-in and Fan-out

Indirectly define scalability

Fan-out N
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Fan-in M

CMOS Inverter

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VTC DESIGN ISSUES

STATIC POWER CONSUMPTION FULL LOGIC LEVELS SHARP TRANSITION SWITCHING THRESHOLD NOISE MARGINS

PRACTICAL VTC

FIVE CRITICAL VOLTAGES

Noise Margins

Static characteristics

Operating regions

VOH

VOL

VIL

VIH

V th -switching threshold