Analysis and Design of Sequential Logic Circuits

Analysis and Design of Sequential Logic Circuits
Digital Logic Analysis & Design
Poras T. Balsara & Dinesh K. Bhatia Center for Integrated Circuits and Systems Department of Electrical Engineering University of Texas at Dallas
Analysis and Design of Sequential Logic Circuits

Sequential Logic Circuit Sequential Logic analysis Sequential logic synthesis Sequential circuit timing Counters Sequence detectors State minimization State assignment problem
ptb/dkb (March 20, 2006)
Introduction
Sequential Logic Mealy Model

In a Mealy model outputs of a circuit are a function of the present state and the present inputs of the circuit.
Inputs
Input Forming Logic (IFL)
Next State
Output Forming Logic (OFL)
Outputs
Memory
Present State
Introduction
Sequential Logic Moore Model

In a Moore model outputs of a circuit are function of the present state only.
Inputs
Input Forming Logic (IFL)
Next State
Output Forming Logic (OFL)
Outputs
Memory
Present State
Introduction
Analysis of Sequential Logic Circuits

Given a sequential circuit, what does it do? What do the state transitions look like ? Analysis of sequential networks is done in three steps:
1. 2.
3.
Logic Equations: Determine the flip-flop excitation and sequential circuit output logic equations. State Table: State table is a tabular representation of the behavior of a sequential logic circuit. For a given input and present state of a circuit, it gives the output and the next state of the circuit. It is created using the characteristic table for the appropriate flip-flop. State Diagram: State diagram is a graphical depiction of a sequential logic circuit. Circles in this diagram depict the states and directed arcs depict the transitions. Ij /Oj Ik /Ok
Mealy Model
Sj
Sk
Ij
Sj /Oj
Ik
Sk /Ok
Moore Model
Introduction 5
State Table and State Diagram

1/0 0/0 1/0
a
0/0
b
1/0
0/1
Present State a b c
Next State x=1 b c b x=0 a a c
Output (z) x=1 0 0 0 x=0 0 0 1
Input (x ) 0 0 0 1 1 1
Present State a b c a b c
Next State a a c b c b
Output (z) 0 0 1 0 0 0
Introduction
State Encoding
Assigning binary labels to states. Example:
1/0 0/0 1/0
a
0/0
b
1/0
0/1
We may use the following encoding: a = 01

1/0 0/0 01 0/0 Next State Present State x=1 x=0 a b c b c b a a c Output (z) x=1 0 0 0 x=0 0 0 1 10 1/0 1/0
b =10
00 0/1
c = 00
Next State Present State x=1 x=0 01 10 00 10 00 10 01 01 00
Output (z) x=1 0 0 0 x=0 0 0 1
2 bits in state encoding

2 flip-flops are needed to store state information

Introduction 7
Example:
1.
Determine the flip-flop excitation and sequential circuit output logic equations.
D0 = Q0 D1 = Q1 Q0 + Q1 Q0
(there are no explicit outputs in the above circuit)
ptb/dkb (March 20, 2006) Introduction 8
2.
State Table: Use the characteristic table for D flip-flop

D
CLK
Q* 0 1
0 1
Input (none )
Present State
Flip-flop Inputs
Next State
Q1 0 0 1 1
Q0 0 1 0 1
D1 0 1 1 0
D0 1 0 1 0
Q1* Q0* 0 1 1 0 1 0 1 0
Output (none)
D0 = Q0 D1 = Q1 Q0 + Q1 Q0
3. State Diagram:
00 01
11
10
Introduction
Example:
1.
Input/Output logic equations:
D0 = Q 2 Q 0 ; X = Q 2 Q1 Q 0
D1 = Q1 Q0 + Q1 Q0 ;
D2 = Q1Q0 ;
Introduction
10
2.
State table:
D0 = Q2 Q0 ; X = Q2 Q1 Q0
Present State Input (none ) Q2 Q1 Q0 Flip-flop Inputs Next State Output
D1 = Q1 Q0 + Q1 Q0 ;
D2 = Q1 Q0 ;
D2 0 0 0 1 0 0 0 1
D1 0 1 1 0 0 1 1 0
D0 1 0 1 0 0 0 0 0
Q2* 0 0 0 1 0 0 0 1
Q1* 0 1 1 0 0 1 1 0
Q0* 1 0 1 0 0 0 0 0
X 1 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Introduction
11
3.
State diagram:
000 0/1
Present state Flip-flop input Next state (none) Q2 Q1 Q0 D2 D1 D0 Q2* Q1* Q0*
in
out X
0 0 0 0 1 1 1 1
0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1
0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0
1 0 1 0 0 0 0 0
0 0 0 1 0 0 0 1
0 1 1 0 0 1 1 0
1 0 1 0 0 0 0 0
1 0 0 0 0 0 0 0
101 5/0 010 2/0 001 1/0 100 4/0 111
7/0
3/0 011
6/0 110
Introduction
12
Example:
1.
Input/Output logic equations:
J 0 = Q1 X ; J1 = X ;
K 0 = Q1 X ; K 1 = X Q0 = XQ0 + X Q0
Introduction 13
2.
State table:
3.
State Diagram:
J 0 = Q1 X ; J1 = X ;
Input X 0 0 0 0 1 1 1 1 Present State Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1
K 0 = Q1 X ; K 1 = X Q0 = XQ0 + X Q0
Flip-flop Inputs Next State Q0* 0 1 1 1 0 1 0 0 0/11 1/1/10 1/0 0 0 1 1 1 1 0 Out
(none)
0/00 1/01
0/-
J1 K1 J0 K0 Q1* 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1
0/-
Introduction
14
An alternate method for describing a state table:
Present State
Next State
Q1* Q0*
x=1 10 11 10 00 x=0 00 01 01 11
Output (none) x=1 x=0
Q1 Q0
00 01 10 11
Introduction
15
Sequential Logic Synthesis

Sequential network design is simply the inverse process of sequential network analysis:
1. 2. 3.
4. 5.
Construct a state diagram Choose a set of state variables and assign state-variable combinations to the named states in the state diagram. Construct the excitation table: For a given transition from a present state to its next state, this table indicates the inputs that must be applied to the flip-flops. Derive the boolean equations for flip-flop excitation and the explicit outputs. Draw a logic diagram to implement the above equations using logic gates and flip-flops.
Introduction
16
Flip-flop Excitation Tables

Excitation tables for D and T flip-flops:
Q 0 0 1 1
Excitation table for JK flip-flop:
Q* 0 1 0 1
D 0 1 0 1
T 0 1 1 0 J 0 1 X X K X X 1 0
17
Q 0 0 1 1
Q* 0 1 0 1
Introduction
J 0 1 0 or 1 0 or 1
K 0 or 1 0 or 1 1 0
Example:
Design a 2-bit binary counter using D flip-flops.
State diagram:
00
01
11
10
Introduction
18
Excitation table:
Input (none )
Present State
Next State
Flip-flop Inputs
Q1 0 0 1 1
Q0 0 1 0 1
Q1* 0 1 1 0
Q0* 1 0 1 0
D1 0 1 1 0
D0 1 0 1 0
Output (none)
Introduction
19
Circuit implementation:
Introduction
20
Mealy Machine Implementation:
Present State
Next State
Q1 Q0
00 01 10
Q1* Q0*
x=1 01 01 01 x=0 00 10 00 0 0 1
Output (z) x=1 x=0 0 0 0
Introduction
21
Example:
A sequential circuit has one input and one output. When input sequence 110 occurs the output becomes 1 and remains 1 until the sequence 110 occurs again in which case the output returns to 0. The output remains 0 until 110 occurs a third time, etc.
State Diagram: State Encoding:
b
0/0 0/0 1/0
000 001
6 states 1/0
010
3-bit encoding
000 001 010 100 101

3 flip-flops
22
c
0/1
1/0
b c
0/0 1/1
d 011
0/1
101
011
d
0/1
e f
1/1
100
1/1
e
3-bit encoding
Introduction
Excitation table using D Flip-flops:

Input (X) 0 1
0/0 0/0
Present State Q2 0 0 0 0 0 0 0 0 1 1 1 1 Q1 0 0 0 0 1 1 1 1 0 0 0 0 Q0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 1
Next State Q2* Q1* 0 0 0 1 1 1 1 0 1 0 0 0 Q0* 0 1 0 0 1 0 1 0 1 1 0 1
Flip-flop Inputs D2 0 0 0 0 0 0 0 1 0 1 0 1 D1 0 0 0 1 1 1 1 0 1 0 0 0 D0 0 1 0 0 1 0 1 0 1 1 0 1
Output (S) 0 0 0 0 1 0 1 1 1 1 0 1
b
001 1/0 1/0 010 c 1/0 0/1 011 d 1/1 0/1 0/1
0 1 0 1 0 1 0 1 0 1
000
0/0 1/1
101 1/1 100
Introduction
23
Excitation and output logic functions:
D2 = XQ2 + XQ1 Q0 D1 = X Q2 Q1 Q0 + XQ1 + Q1 Q0 + XQ2 Q0 D0 = XQ1 + XQ2 + Q2 Q0 + X Q1 Q0 S = XQ1 + XQ2 + Q2 Q0 + Q1 Q0

Circuit Implementation
D2 = XQ2 + XQ1 Q0 D1 = X Q2 Q1 Q0 + XQ1 + Q1 Q0 + XQ2 Q0 D0 = XQ1 + XQ2 + Q2 Q0 + X Q1 Q0 S = XQ1 + XQ2 + Q2 Q0 + Q1 Q0
Introduction
25
Some Design Examples
1.
Design a Gray code counter using JK flip-flops. Design a 3 bit up/down counter using T flip-flops. The count direction is determined by input D (D=0 means count down).
2.
Introduction
26
Example:
Design a sequential comparator circuit that is to determine which of the two multi-bit numbers, A and B, of equal length is larger. Inputs are supplied in MSB first fashion.
10/10
10
X X /10
00,11/00
00
01/01
01
X X /01
Introduction
27
Example:
Design a sequential circuit that produces 1 on its output if it detects the sequence 101 on its input. The detector should keep checking for the appropriate sequence and should not reset to the initial state after it has recognized the sequence.
Mealy Implementation (using D flip-flops)
P.S. Q1Q0 s0 (00) s1 (01) s2 (10) P.S. Q1Q0 s0 (00) s1 (01) s2 (10) s3 (11)
N.S. (Q1*Q0*) x=0 s0 (00) s2 (10) s0 (00) x=1 s1 (01) s1 (01) s1 (01)
Out (z) x=0 0 0 0 x=1 0 0 1
D1 = x Q0 D0 = x z = x Q1
Moore Implementation (using D flip-flops)

N.S. (Q1*Q0*) x=0 s0 (00) s2 (10) s0 (00) s2 (10) x=1 s1 (01) s1 (01) s3 (11) s1 (01) Out (z) 0 0 0 1
28
D1 = x Q0 + x Q1 Q0 D0 = x z = Q1 Q0
Introduction
Example (contd.): Output Waveforms

CLK Input x Mealy State Output z State Output z
s0
s1
s2
s1
s1
s2
s1
s1
s2
s0
Moore
s0
s1
s2
s3
s1
s2
s3
s1
s2
s0
Mealy outputs may change when an input changes (i.e., not necessarily on a clock edge). output may have glitches. This problem can be solved by making Mealy inputs synchronous. Moore outputs only change on clock edges since they depend only on the present state. Moore outputs may be delayed w.r.t. the corresponding outputs in a Mealy implementation.
Introduction
29
Example: Moore Machine

Design a bit-serial odd parity checker: It counts the number of 1s in a bitserial input stream and asserts its output when the input stream contains an odd number of 1s.
0 1 reset even 0 1 odd 1 0 P.S. Q0 N.S. (Q0*) x=0 x=1 Out (z)
even (0) odd (1)
even (0) odd (1)
odd (1) even (0)
0 1
Using D flip-flops
Using T flip-flops
D0 = x Q0 z = Q0
T0 = x z = Q0
Introduction
30
Example: Moore Machine

A bus controller, that receives requests on separate lines, R0 to R3 from 4 devices to use the bus. It has four outputs, G0 to G3, only one of which is 1 (indicating which device is granted control for that clock period). The lowest number device has the highest priority. A higher priority device can preempt the bus. Assume that, before servicing any pending request, the controller remains idle for one clock period.
The bus controller has five state: A: idle, no device is using the bus B: device 0 is using the bus C: device 1 is using the bus D: device 2 is using the bus E: device 3 is using the bus
Introduction
31
Moore state machine for the bus controller example.

Inputs: R0R1R2R3 Outputs: G0G1G2G3
1XXX 0000
A
0000
XXX0 1XXX X1XX XX1X 0001
B
1000
1XXX
0XXX
E
0001
01XX
X0XX 1XXX
001X
XX0X 1XXX X1XX
0001
C
0100
01XX
D
0010
001X
Introduction
32
Example Modulo 3 in Binary

Analogous to Decimal - Use long division
1 9 1 5 9 3 5 7 4 7 9 3 2 2 7 0 3 1 1 5 2 2 7 2
ptb/dkb (March 20, 2006) Introduction
Modulus
Take one digit at a time

Start at the most significant digit
Calculate remainder Shift in another digit

The previous modulus moves to tens position Shifted digit gets added
Calculate remainder
Repeat until all digits are done

33
Binary Modulus
Take one bit at a time (MSB first) Calculate remainder m
Three possible values 0,1,2
Shift in the next bit

Shifting results in doubling the previous modulus value New digit gets added to this doubled value
Perform modulus of the resultant value
2m + 1; if next bit is 1 m' = 2m + 0; if next bit is 0
m = m' mod 3
State Table and State Diagram

Present Modulus 0 1 2 Next x=0 0 2 1 x=1 1 0 2 1 0 0
0
1
1
0
Present Modulus 00 01 10
Next x=0 00 10 01
Introduction
x=1 01 00 10
35
Implementation with T Flip-Flops

Input x 0 0 0 1 1 1 Present State Next State Flip-flop Inputs
Q1 0 0 1 0 0 1
Q0 0 1 0 0 1 0
Q1* 0 1 0 0 0 1
Q0* 0 0 1 1 0 0
T1 0 1 1 0 0 0
T0 0 1 1 1 1 0
T1 = x(Q1 + Qo ) T0 = ( x Q1 ) + Qo
Treatment of Unused States

A state machine has unused states when the number of states with n flip-flops, 2n, is greater than the number of states required, s. There are two approaches to deal with unused states, depending on the application requirements:
1.
Minimal Cost: This approach assumes that the machine will never enter an unused state. Therefore, next state entries of unused states can be marked as dont-cares. In most cases, this simplifies the excitation logic. Minimal Risk: This approach assumes that it is possible for the machine somehow to get into one of the unused (illegal) states. Therefore, all unused states should have explicit next state entries for any input combination so that they always reach some other safe state.
Introduction 37
2.
Sequential Circuit Timing

Once the functionality of a sequential network is designed, its timing parameters must be determined. Timing problems can be very subtle because timing parameters can vary with device age and other operating conditions.
Introduction
38
Timing Parameters
Global setup time (Tsu) Global hold time (Th) Maximum clock frequency Clock skew.
These parameters are derived using the circuit (known) delays described below.
tio delay from input of IFL to output of OFL tif delay from circuit inputs of flip-flop inputs tfo delay from flip-flop outputs to circuit outputs tff delay from flip-flop outputs to flip-flop inputs tc-q clock to Q propagation delay of flip-flops tsu setup time of flip-flops th hold time of flip-flops tc clock delay; time required for clock to reach all flip-flops
Global Setup and Hold Times

Changes that occur at inputs can be delayed by as much as maximum tif by the time they reach the flip-flop inputs. Hence, we want to setup circuit inputs relative to clock edge appearing at the flip-flops. Th Tsu
tc th tif tsu tif
CLK (at clock source) CK (at FF clock input) X (at sequential circuit input)
D (at FF input)
Tsu = tsumax + tifmax tcmin

Similarly, hold time of the circuit inputs relative to the system clock at the source is given by
Th = thmax tifmin + tcmax

Clock Frequency
The limiting factor on the clocking rate is the propagation delay through the IFL block:
Changes on the Qs must propagate through the IFL before they can affect the next state
Clock Frequency
The limiting factor on the clocking rate is the propagation delay through the combinational logic block (input forming logic):
Dj Qj
Comb. logic
CKj
Di
CKi CLK tff
Qi
Changes on the Qs must propagate through the combinational logic before they can affect the next state
Introduction
42
Maximum Clock Frequency

CKi Qi
tC-Q
Dj
tff
tsu
Tck (=Tclk)
Edge Triggering
For an edge-triggered circuit: minimum clock period is,
Tclk tC Q ,max + t ff ,max + tsu,max

Maximum Clock Frequency:
f clk
1 Tclk
43
Maximum Clock Frequency

Dj Qj
CKi Qi
Comb. logic
CKj
Di
CKi
Qi
tC-Q
Dj
tff
tsu
CLK
tff
Tck (=Tclk)
Edge Triggering
For an edge-triggered circuit: minimum clock period is,
Tclk t C Qmax + t ffmax + t sumax

Maximum Clock Frequency:
f clk
1 Tclk
44
Timing Violations
Tclk tC Qmax + t ffmax + tsumax
The clock period (Tclk) has a lower bound of tff.max . If the clock period is equal to (tff.max + tC-Q.max) then the flip-flop state changes can violate setup times. Remedy :
Use faster flip-flops (decrease tC-Q ) Use faster gates (decrease tff ) Use a slower clock (increase clock period, Tclk)
Clock Skew
The previous discussion assumes that clock signals arrive at all flip-flops simultaneously - this is not a good assumption since it is not true in practice. Because of different wire lengths over which the clock signals travel and the load at the destination, there is a slight difference in clock arrival times at different flip-flop inputs. Clock skew, tskew, is the difference in time between triggering edges seen at different flip-flops. Clock skew affects minimum Tclk.
Max. Clock Frequency with Skew

CKi CKj Qj
tskew tp tff tsu
Di
Tck (=Tclk)
Therefore, for an edge-triggered circuit with clock skew,
Tclk t skew,max + t p ,max + t ff ,max + t su ,max

Clock skew is a significant factor in determining the speed of highperformance sequential circuits. The larger the skew, the slower the circuit will operate.
Max. Clock Frequency with Skew

Dj Qj
CKi CKj
tskew tC-Q tff tsu
Comb. logic
CKj
Di
CKi
Qi
tskew
Qj
CLK
tff
Di
Tck (=Tclk)
Therefore, for an edge-triggered circuit with clock skew,
Tclk tskewmax + tC Qmax + t ffmax + tsumax

Clock skew is a significant factor in determining the speed of highperformance synchronous circuits. The larger the skew, the slower the circuit will operate.
Maximum Allowable Clock Skew

Can any skew be countered simply by slowing down the clock? No
If the skew is too large, state change caused by an edge at FFi will change the state of FFj erroneously when the clock edge finally gets there!
Dj Qj
CKi CKj
tskew tC-Q th
Comb. logic
CKj
Di
CKi
Qi
tskew
Qi
tff
Dj
state of Dj before clock becomes active
CLK
tff
tC Q + t ff tskew + th
state of Dj after clock becomes active
In the worst case, if tff = 0 then,
tskewallowed = tC Qmin thmax

flip-flops propagation delay must be greater than its hold time.
Timing Analysis Example

For the circuit given below determine all the sequential circuit timing parameters.
For a D flip-flop use: tsu = 2ns, th = 15ns and tC-Q = 20ns For a NAND gate use: tp,max = 10ns and tp,min = 3ns
tif ,max = 3t p ,max,nand = 30ns tif ,min = 2t p ,min,nand = 6ns t ff ,max = 2t p ,max,nand = 20ns t ff ,min = 2t p ,min,nand = 6ns tc ,max = 2t p ,max,nand = 20ns tc ,min = 2t p ,min,nand = 6ns
For a D flip-flop use: tsu = 2ns, th = 15ns, tC-Q = 20ns For a NAND gate use: tp,max = 10ns, tp,min = 3ns
Tsu = tsu ,max + tif ,max tc ,min = 2 + 30 6 = 26ns Th = th ,max tif ,min + tc ,max = 20 + 15 6 = 29ns Tclk tC Q ,max + t ff ,max + tsu ,max = 20 + 20 + 2 = 42ns f clk ,max = 1/ 42ns = 23.8MHz tskew,max = tC Q ,min + t ff ,min th ,max = 20 + 6 15 = 11ns
Why is clock skew irrelevant in this example?
1-Phase Clock w/ Level Triggering
Positive clock skew
Latch must be open for less than the shortest combinational logic delay but more than the worst setup time.
t w td q min + tlmin th max t skewmax t skewmax

and
tlmin t w td q min + th max + tskewmax

d q min
( (t
t w > t sumax or
+ tlmin tw th max
Introduction
52
Sequential Systems Using Latches

Latches can be used to create sequential systems. However, since these are level-triggered clocking must be done carefully must ensure that state changes only once per clock cycle.
tw < tff.min+ tD-Q.min
Dj Qj CLK Qi
Comb. logic
CKj
Di
CKi
> (tD-Q.max + tff.max+ tsu.max)
CLK
tff
Use narrow-width clock whose pulse width is less than the fastest possible path through the combinational logic. To guarantee correct next state, make sure that the clock period is longer than the worst-case propagation delay through the combinational logic.
Clocking Constraints with Latches

tw
CKi CKj Dj Qj Di
tsu tw tskew
Comb. logic
CKj
tD-Q
Di
CKi
Qi
tskew
Qi
tff th
CLK
tff
Dj
tw < t D Qmin + t ffmin thmax tskewmax tw > tsumax

Clocking Frequency with Latches

Tclk
CKi Dj Qj CKj Dj
tskew
tskew tw tsu tD-Q tff tsu
Comb. logic
CKj
Di
CKi
Qi
CLK
tff
Qj
Di
Tclk > tskewmax + tw tsumin + t D Qmax + t ffmax + tsumax

2-Phase Clock w/ Latches
For block CL1 :
tcycle t1 tsumin + td q max + tl 1max + tsumax + t 21 For block CL2 : tcycle t 2 t sumin + td q max + tl 2max + tsumax + t12 tskewmin For latching: t1 > tsumax and t 2 > t sumax
( (
Two-Phase Clocking with Latches

D1 D1 Q1 Q1
Comb. logic
tff
D2
Q2
Comb. logic 1
tff1
D2
Q2
Comb. logic 2
CLK2 tff2
CLK1
t12
CLK1
t21
CLK1
CLK2
CLK2
non-overlap periods
Introduction 57
Two-Phase Clocking Frequency

tw1 t12
CLK1
t21
t12
D1
Q1
Comb. logic
tff
D2
Q2
CLK2
tw2 tsu1 tsu1
D1
tD-Q1
CLK1
CLK2
Q1
tff tsu2
D2
Tclk1 > ( tw1 tsu1min ) +tDQ1max + t ffmax +tsu2max + t21 Tclk 2 > ( tw2 tsu 2min ) + tDQ2max + tsu1max + t12
tD-Q2
tsu1
Q2
Tclk1 Tclk2
Counters
Counters are sequential circuits that go through a prescribed sequence of states upon the application of input pulses, i.e. they are sequence generators. Sequence of counter states may follow a binary count or any other sequence of states. Binary Counter: It follows the binary counting sequence, An n-bit binary counter has n flip-flops and can count in binary from 0 to (2n 1).
00 01 00 01
11
10
11
10
Up Counter
Down Counter
59
Divide-by-n Counter
It is a binary counter with n states. It resets to state 0 after going through n states.
00
01
10 Divide-by-3 Counter
Introduction
60
Ripple Counters
Each bit toggles if and only if the immediately preceding bit changes from 1 to 0. Q0 Q1 Q3 Q2
Q Q CLK T
Q Q CLK
Q Q CLK
Q Q CLK
CLK
CLK
Q0 Q1 Q2 Q3
A bit change from 1 to 0 generates a carry to the next most significant bit => ripple Slower than other counters when MSB has to change, the output is not valid until time n.tclkQ for an n-bit counter. Requires fewer components.
61
Modulo-16 Counter Implementation
Ripple Carry Output
D0 = Q0 D1 = Q1 Q 0 D 2 = Q 2 Q1Q 0 D 3 = Q 3 Q 2Q1Q 0
Input forming logic: Parallel implementation
high fan-in gates Serial (cascaded) implementation low fan-in gates, but longer clock period
Introduction 62
Modulo-16 Counter with Enable Input
Introduction
63
Modulo-16 Counter w/ Load & Enable
Introduction
64
Modulo-16 w/ Load, Clear & Enable
Introduction
65
Free-running Modulo-16 Counter

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
CLK D3 D2 D1 D0 LD EN CLR Q0 0 1 0
CLK
Q0 Q1 Q2 Q3
RCO Mod-16 Counter
Q3
Q2
Q1
RCO
Introduction
66
Counter with a Beginning Offset

Example: This counter counts sequence 0110 through 1111 and repeat.
6 7 8 9 10 11 12 13 14 15 6 7 8 9 10 11 12 13
D3 D2 D1 D0 LD EN CLR
Q0
0 1
CLK
CLK LD
RCO Mod-16 Counter
Q1
Q0 Q1 Q2
1 1 0
Q3
Q2
Q3
This counter is self-starting. Resetting clears the counter to 0000. Although it starts off in an invalid state, it reaches the desired sequence within 6 clock cycles.
Counter with a Cutoff Limit

Example: This counter counts sequence 0000 1001 and repeats (a decade counter)
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
D3 D2 D1 D0 LD EN CLR
CLK
RCO Mod-16 Counter
1 0
Q0
CLK CLR
Q1
Q0 Q1 Q2 Q3
Q3
Q2
Introduction
68
Cascading Synchronous Counters

0 1 0 0 0 0 D3 D2 D1 D0 LD EN CLR RCO Mod-16 Counter CLK Q3 Q2 Q1 Q0 Q7
1 2
D3 D2 D1 D0 LD EN CLR RCO Mod-16 Counter CLK Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Q6
3 4
Q5
5 6
Q4
7 8 9
10 11 12 13 14 15 16 17 18
CLK Q0 Q1 Q2 Q3 RCO Q4 Q7
Introduction
69
Ring Counter
It is a circulating bit counter. It counts by shifting 1 through a counter. This family of counters is also referred to as Shifting Counters.
It requires n bits of memory to encode n states. However the states are directly usable, e.g., in state i, the ith bit is 1, others are 0. Binary counters are more efficient since n states can be represented by log2n bit binary representation of i. Where can you use ring counters?
Ring Counter Design

A ring counter operates by circulating a single 1 as shown below:
A start pulse sets a 1 in flip-flop n and 0 in all others. On subsequent clock pulses the 1 in bit 1 shifts right.
Introduction
71
State diagram of a basic 4-bit Ring counter:
In this basic design if the counter gets caught in an invalid state, it will never be able to come to a valid state on its own.
Self-Correcting Ring Counter

It automatically forces the counter to valid states if it makes a transition to an invalid state. In a ring counter there is exactly ONE bit which is 1 in the ring, so if a 1 has to be forced into the counter (at MSB) then the remaining (n-1) low order bits have to be 0. That is, the correcting action is taken at the beginning of every cycle 0s are pushed in till all the (n-1) low order bits are 0.
The feedback mechanism for an n-bit counter ensures return to the valid states within a maximum of (n-1) clock cycles.
Note: Preset and clear on flip-flops are no longer required if time is available for the counter to self-correct. Hence, it is also a Self-starting counter. State diagram of a self-starting, self-correcting 4-bit ring counter:
Introduction
74
Johnson Counter
This is another shifting counter. It is a compromise between binary and ring counter since it encodes 2n states in n bits. The counter is first initialized to all 0s. Then each next state is formed by shifting in 1s until all bits are 1, after which 0s are shifted until all bits are 0.
Shifting counters can get into unused state and will persist in moving from one invalid state to another and never find its way to a valid state. Proper design can prevent this from happening.
Introduction 75
Johnson Counter Design

It is a counter with 2n states using n flip-flops. It has (2n-2n) unused (invalid) states. Design of a 3-bit Johnson counter using JK flip-flops.
State diagram
100 000 110 Present State Q2 0 1 1 001 011 111 1 0 0 Q1 0 0 1 1 1 0 Q0 0 0 0 1 1 1 1 1 1 0 0 0
Excitation table
Next State Q2* Q1* 0 1 1 1 0 0 Q0* 0 0 1 1 1 0 J2 1 X X X 0 0 Flip-flop Inputs K2 X 0 0 1 X X J1 0 1 X X X 0 K1 X X 0 0 1 X J0 0 0 1 X X X K0 X X X 0 0 1
76
Introduction
Logic equations:
J 2 = Q0 K 2 = Q0
J1 = Q2 K1 = Q2
J 0 = Q1 K 0 = Q1
Circuit implementation:
It needs self-correcting logic to correct itself whenever it gets into an invalid state.
Self-Correcting Johnson Counter

What should be shifted in so that the counter gets out of an invalid state.
When counter is in normal mode of operation we shift in . Counter is in invalid state when 0s and 1s do not form contiguous blocks.
Modify the circuit so that 0s are forced in until the counter gets to the all 0s state and then force 1 to ensure contiguous 1s and 0s.
Introduction
78
State diagram of a 3-bit self-correcting Johnson counter:
100 000 110
101
010
001 011
111
Introduction
79
Sequence Detectors
Sequence detectors are sequential networks used to detect if a given sequence of events have occurred on its input(s). These circuits form a necessary component in a number of applications, e.g., vending machines, telecommunication equipment, slot machines, etc. Two modes of operation:
Verify Mode: Start in a reset state and look for the given sequence. As soon as an input not in the sequence occurs assert a failure signal and wait for a signal to reset and begin again. Hunt Mode: Detector continuously looks for the specified sequence, when the sequence is found, success is indicated.
Introduction
80
Example: Sequence Detector

In verify mode, detect the sequence 00110. Start searching when start is asserted, assert found if the sequence occurs and failed if not. Return to the reset state when reset is asserted after finding or failing.
In the above state diagram note that reset input is not shown on all transitions (it is a dont care), and outputs indicated by - imply found=failed=0
Example: Sequence Detector

In hunt mode, detect a sequence of 4 consecutive 0s. Assert found and start searching for the next occurrence once a pattern is found.
Note: In hunt mode, to detect a sequence of length n we need states to remember last n-1 inputs.
Design Example: Tail Light Controller

Design a state machine to control tail lights of a car. On each side three lights are to be used for turn signaling and hazard. These are controlled by left, right and hazard signals.
Inputs: LEFT (L), RIGHT (R), HAZ (H) Outputs: (LC, LB, LA) and (RA, RB, RC) Operation:
LEFT HAZ RIGHT
1234
Texas
LC LB LA
RA RB RC
Introduction 83
Tail Light Controller: State Diagram

Condition of each tail lamp defines a unique state Use Moore machine since outputs are solely determined by the state.
Input bit order: L R H Output bit order: LC LB LA RA RB RC
111 111 XX1 XX1 001 000 L1 XX0 011 000 L2
011 001 H1 100
XX1 XX1 XXX 010 000 100 R1 XX0

111 110
XX1 100
101
000 IDLE 000 000 010
R2
000 110
XX0
XXX 000
Introduction
XXX
XX0 State Encoding

84
L3 111 000
R3 000 111
Tail Light Controller: State Table

Inputs L 0 1 0 X X X X X X X X X X X X R 0 0 1 X X X X X X X X X X X X H Q2 0 0 0 1 0 1 0 1 X 0 1 0 1 X X 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Present State Q1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 Q0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 (IDLE) (IDLE) (IDLE) (IDLE) (L1) (L1) (L2) (L2) (L3) (R1) (R1) (R2) (R2) (R3) (H1) 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 FF Inputs D2 D1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 D0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 Q2* 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 Next State Q1* 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 Q0* 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 (IDLE) (L1) (R1) (H1) (L2) (H1) (L3) (H1) (IDLE) (R2) (H1) (R3) (H1) (IDLE) (IDLE) LC 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 Outputs (Moore outputs) LB 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 LA 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 RA 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 RB 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RC 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Introduction
85
Tail Light Controller: Logic Equations

Flip-Flop Equations:
D2 = Q2Q0 + HQ0 + HQ2 Q1 + L RH Q2 Q1 Q0 D1 = H Q0 D0 = H Q1 Q0 + L RH Q2 Q1 Q0 + LR H Q2 Q1 Q0

Output Equations:
LA = Q2 Q1 + Q2 Q0 + Q2Q1 Q0 LB = Q2 Q1 + Q2Q1 Q0 LC = Q2 Q1Q0 + Q2Q1 Q0

Introduction
RA = Q2Q1 + Q2 Q0 + Q2Q1 Q0 RB = Q2Q1 + Q2 Q0 RC = Q2 Q0
86
Exam 2
Has been graded and recorded.
scores to be released today. PLEASE pick your paper after 1PM from either,
my office, or, if I am not around, my secretary Ms. Hines.
Introduction
87
State Minimization
To reduce the cost of sequential machines, it is necessary to eliminate redundant (equivalent) states. State minimization is the removal of redundant states. Two states are said to be equivalent if for each member of the set of inputs, they:
1. 2.
give exactly the same output, and send the circuit either to the same state or to an equivalent state.
Introduction
88
Example
Consider the following state diagram for state minimization
Introduction
89
Original state table

Present State 0 1 2 3 4 5 6 Next State x=1 1 3 3 5 3 5 3 5 5 x=0 0 2 0 4 0 6 4 0 0 0 0 1 1 1 1 Output x=1 x=0 0 0 0 0 0 0 0 Present State 0 1 2 3 4 Next State x=1 1 3 3 3 3 x=0 0 2 0 4 0 Output x=1 0 0 0 1 1 x=0 0 0 0 0 0
Reduced state table
1. Check for equivalent states. 2. States 4 and 6 are equivalent 3. Go to step 1. and check again.
replace state 6 by 4 everywhere.
Note: states 2 and 4 are not equivalent since the outputs are different.
Original state diagram
Reduced state diagram

Implication Table
If there are 2m states in a sequential machine we need m flip-flops Reduction in the number of states may or may not result in a reduction in the of flip-flops. Determination of equivalent states can be done using a tool called Implication Table. It is a more general technique compared to State Reduction by Inspection discussed earlier.
Introduction
92
State Minimization using Implication Table

1.
Using a table of present states, next states and outputs, construct an implication table as follows:
Each state is associated with a column and a row, i.e., list all states except the first in rows and all except the last in columns. Each cell in this table corresponding to the intersection of a row and column represents two states being tested for equivalence.
2.
3.
4.
Based on condition 1 for equivalent states place a cross in the cells corresponding to those state pairs whose outputs are not equal for every input. In each remaining cell, place the pairs of next states whose equivalence is implied by the two states corresponding to the cell, i.e., states in each state pair must be equivalent in order for the states labeling the row and column to be equivalent. Make successive passes through the entire table to determine if any more cells should be crossed off. Repeat this procedure until no additional cells can be crossed off.
Introduction 93
Example:
Reduce the following state machine using an implication table.
Introduction
94
Implication Table
AH DG
D-F
Introduction
95
Reduce the state diagram removing equivalent states (AH and DG).
Original State Diagram
Reduced State Diagram

Introduction 96
Example
Reduce the following state machine using an implication table.
Present State A B C D E F G H Next State x=1 C H D E A B H G x=0 D F E A C F B C Out 0 0 1 0 1 1 0 1
Introduction
97
Implication Table:
Present State A B C D E F G H
Next State x=1 x=0 C H D E A B H G D F E A C F B C
Out 0 0 1 0 1 1 0 1
AD CE
Introduction
98
Reduced State Table:
Present State A B C D E F G H
Next State x=1 C H D E A B H G x=0 D F E A C F B C
Out 0 0 1 0 1 1 0 1
Present State A B C F G H
Next State x=1 C H A B H G x=0 A F C F B C
Out 0 0 1 1 0 1
Introduction
99
State Assignment
State Assignment is a binary encoding used to represent states of a sequential machine in its digital circuit implementation. In our designs so far we have assumed some state assignment without considering any alternatives. Two different assignments may result in vast differences in hardware. Appropriate choice of state assignment may result in lower cost and improved performance.
State Assignment Example

Consider the following machine with 7 states.
Next State / Output
Present State A B C D E F G
Let us use the following assignments to encode the states A through G

Present State A B C D E F G State Assignments Assignment I Q1Q2Q3 000 001 011 010 101 110 111 Assignment II Q1Q2Q3 001 000 010 011 100 101 110
x=0
B/0 C/0 D/0 A/1 G/0 A/0 F/0
x=1
E/0 G/0 F/0 A/0 C/0 A/1 D/0
Introduction
101
Comparing Assignments I and II

If the state machine was implemented using JK flip-flops
Using Assignment I Using Assignment II
J 1 = q2 x + q 3 x J 2 = q3 J 3 = q2 z = q1 q2 q3 x + q1 q3 x
K 1 = q3 + x K 2 = q3 K 3 = q2
J 1 = q 3 x + q2 x J 2 = q1 q3 + q1 q3 J 3 = q2 + q1 x z = q1 q3 x + q2 q3 x
K 1 = q3 + x K 2 = q3 + q1 x + q1 x K 3 =1
2-input Gate Count

NOT AND OR Total 4 7 3 14
2-input Gate Count

NOT AND OR Total 4 11 7 22
Assignment II requires almost twice as many gates as Assignment I !

State Assignment Problem

What is the number of possible state assignments for a sequential machine with s states?
If total number of flip-flops needed for this machine is n, then
2 n 1 < s 2 n
Number of ways to select s combinations out of 2n combinations is,
C 2 n ,s
2n 2n ! = s = s! ( 2 n s )!
For each of these combinations, there are s! permutations for assigning s elements (binary encodings) to s states, making the Total number of possible assignments =
2 n ! s! s! ( 2 s )!
n
2n ! ( 2 n s )!
103
Lets try all possible assignments .

How many
s
2 3 6 8 12 16
n
1 2 3 3 4 4
# Assignments
2 24 20,160 40,320 871,782,912,0000 209,227,898,880,00
Introduction
104
State Assignment Problem

It is not practical to go through all possible assignments to determine the optimal assignment for machines with more than two or four states. Unfortunately, there is no simple technique to determine optimal state assignment. Reasonably good assignments can be obtained by using a few guidelines.
Introduction
105
State Assignment Guidelines

In order to reduce the complexity of logic equations, the state assignment should be such that it forces large groupings of the logic 1s in the binary transition table, or transition K-map.
The larger the group of 1s, simpler excitation and output equations reduced complexity of combinational circuit.
Minimum-Bit-Change Heuristic:
Minimize the number of bit changes for all state transitions.
Guidelines based on Next State and Input/Outputs:

Highest priority: States with the same next state for a given input should be given adjacent assignments in the state map. Medium priority: Next states of the same state should be given adjacent assignments in the state map. Lowest priority: States with the same output for a given input should be given adjacent assignments in the state map.
Introduction 106
Use of State Assignment Guidelines:

1.
Write down all sets of states which should be given adjacent assignments.
i/j
i/k
i/j
i/j
Lowest Priority
Highest Priority
Medium Priority
2.
3.
4.
Compare the adjacencies of states for different assignments by plotting the states on state assignment K-maps with each cell representing the state variable combination assigned to one state of the circuit. If all adjacencies suggested by the top two priorities are not satisfied due to some conflicting requirements, then resolve them in favor of conditions from highest priority and the adjacency conditions which are required two or more times. When guidelines require that 3 or 4 states be adjacent, these states should be placed within a group of 4 adjacent cells on the assignment K-map.
Introduction
107
Example:
Consider the following state machine having 4 states
Present State A B C D Next State / Out x=1 D/0 A/0 D/0 B/1 x=0 C/0 C/0 B/0 A/1
Adjacencies from medium priority guideline: for state A: {C, D} for state B: {A, C} for state C: {B, D} for state D: {A, B}
Adjacencies from highest priority guideline: for x=0: {A, B} for x=1: {A, C}
Adjacencies from lowest priority guideline: for 0/0: {A, B, C} for 1/0: {A, B, C}
Compare the adjacencies of states for the different assignments by plotting the states on state (assignment) maps. In general it is a good
idea to assign the reset state (state A in this example) to state map cell 0).
Adjacencies: {A,B}; {A,C} {C,D}; {A,C}; {B,D}; {A,B} {A,B,C}; {A,B,C}
It can be seen that assignment 3 fulfills most of the adjacencies and hence should produce the best results for this example. The state encoding (q1 q2) is A:00 C:10 B:01 D:11
Example:
Encode the states using the state assignment guidelines for the sequential circuit described by the following state machine
A Adjacencies from highest priority guideline: for x=0: {D, E}; {F, G} for x=1: {F, G} C 0/0 0/0 E 1/0 0/1 G 1/0 Adjacencies from medium priority guideline: for state A: {B, C} for states B and C: {D, E} 2x for state E: {F, G} (note: 2x next to an adjacency => it exists twice on the list)
0/0 B 0/0 D 0,1/0 F 0,1/0 1/0
1/0 1/0
Adjacencies from lowest priority guideline: for 0/0: {A, B, C, D, E, F} for 1/0: {A, B, C, D, E, F, G}
Introduction
110
Create state maps to satisfy the adjacencies

Assignment I Assignment II
Adjacencies: {D,E}; {F,G} {A,B}; {D,E}2x; {F,G} {A,B,C,D,E,F}; {A,B,C,D,E,F,G}
q2q3 q1 00 0 1 A
01 B C
11 D E
10 F G
q2q3 q1 00 0 1 A F
01 B C
11 D E
10
A = 000 B = 001 C = 101 D = 011
E = 111 F = 010 G = 110
A = 000 B = 001 C = 101 D = 011
E = 111 F = 100 G = 110
Both assignments satisfy all of the high- and medium-priority guidelines, as well as most of the lowest-priority ones.
Introduction
111
Example:
Find a state assignment for the sequential machine described below:
Adjacencies from highest priority guideline: for x=0: {A, C, E, G}; {D, F} for x=1: {A, B, D, F}; {E, G} Adjacencies from medium priority guideline: for state A: {B, C} for state B: {C, D} for state C: {B, E} for states D and F: {C, F} 2x for states E and G: {B, G} 2x (note: 2x next to an adjacency => it exists twice on the list) Adjacencies from lowest priority guideline: for 0/0: {A, B, C, D, E, G} for 1/0: {A, B, C, D, E, F}
Introduction 112
Present State A B C D E F G
Next State / Output x=1 C/0 C/0 E/0 C/0 G/0 C/0 G/1 x=0 B/0 D/0 B/0 F/0 B/0 F/1 B/0
Plot states on state maps.

Adjacencies: {A,C,E,G}; {D,F}; {A,B,D,F}; {E,G} {B,C}; {C,D}; {B,E}; {C,F}2x; {B,G}2x {A,B,C,D,E,G}; {A,B,C,D,E,F}
Assignment I
Assignment II
These assignments were done by first satisfying the guideline for 3 or 4 adjacent states and then conditions which are required two or more times. Based on the assignment I we get the following state encodings,
A:000, B:110, C:001, D:111 E:011, F:101, G:010
Introduction
113
State Assignment using One Hot Encoding

So far, our goal has been dense encodings: state encodings in as few bits as possible. One hot encoding is an alternative approach in which additional flip-flops are introduced in the hope of reducing the next-state and output logic complexity. improved performance For a machine with n states, one hot encoding uses exactly n flip-flops. One hot each state is represented by an n-bit binary code in which exactly 1 bit is asserted.
Example: One hot encoding

0/0 B 0/0 D 0,1/0 F 0,1/0 0/1 0/0 1/0 A 1/0 1/0 C 0/0 E 1/0 G 1/0 A B C D E F G Present State Next State / Output State Assignments Dense q1q2q3 000 001 101 011 111 010 110 One hot q1q2q3q4q5q6q7 1000000 0100000 0000100 0001000 0000001 0010000 0000010
x=0
B/0 D/0 E/0 F/0 F/0 A/0 A/1
x=1
C/0 E/0 D/0 F/0 G/0 A/0 A/0
Implementation using D flip-flops: with Dense Encoding

D 1 = q 2 (x q 1 )+ q 1 q 2 q 3 x D2 = q3 D 3 = q2 z = q1 q 3 x
with One Hot Encoding

D1 = q3 + q6 D2 = q1 x D3 = q 4 + q 7 x D4 = q 2 x + q 5 x
Introduction
D5 = q1 x D6 = q7 x D7 = q5 x + q2 x z = q6 x
115

Analysis and Design of Sequential Logic Circuits

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Analysis and Design of Sequential Logic Circuits

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Analysis and Design of Sequential Logic Circuits

Digital Logic Analysis & Design

Analysis and Design of Sequential Logic Circuits

ptb/dkb (March 20, 2006)

Sequential Logic Mealy Model

Input Forming Logic (IFL)

Output Forming Logic (OFL)

ptb/dkb (March 20, 2006)

Sequential Logic Moore Model

Input Forming Logic (IFL)

Output Forming Logic (OFL)

ptb/dkb (March 20, 2006)

Analysis of Sequential Logic Circuits

ptb/dkb (March 20, 2006)

State Table and State Diagram

Next State x=1 b c b x=0 a a c

Output (z) x=1 0 0 0 x=0 0 0 1

ptb/dkb (March 20, 2006)

We may use the following encoding: a = 01

Next State Present State x=1 x=0 01 10 00 10 00 10 01 01 00

Output (z) x=1 0 0 0 x=0 0 0 1

2 bits in state encoding

2 flip-flops are needed to store state information

State Table: Use the characteristic table for D flip-flop

Input/Output logic equations:

ptb/dkb (March 20, 2006)

ptb/dkb (March 20, 2006)

ptb/dkb (March 20, 2006)

Input/Output logic equations:

ptb/dkb (March 20, 2006)

ptb/dkb (March 20, 2006)

An alternate method for describing a state table:

Output (none) x=1 x=0

ptb/dkb (March 20, 2006)

Sequential Logic Synthesis

ptb/dkb (March 20, 2006)

Flip-flop Excitation Tables

ptb/dkb (March 20, 2006)

ptb/dkb (March 20, 2006)

ptb/dkb (March 20, 2006)

Mealy Machine Implementation:

Output (z) x=1 x=0 0 0 0

ptb/dkb (March 20, 2006)

000 001 010 100 101

Excitation table using D Flip-flops:

Next State Q2* Q1* 0 0 0 1 1 1 1 0 1 0 0 0 Q0* 0 1 0 0 1 0 1 0 1 1 0 1

101 1/1 100

ptb/dkb (March 20, 2006)

Excitation and output logic functions:

D2 = XQ2 + XQ1 Q0 D1 = X Q2 Q1 Q0 + XQ1 + Q1 Q0 + XQ2 Q0 D0 = XQ1 + XQ2 + Q2 Q0 + X Q1 Q0 S = XQ1 + XQ2 + Q2 Q0 + Q1 Q0

D2 = XQ2 + XQ1 Q0 D1 = X Q2 Q1 Q0 + XQ1 + Q1 Q0 + XQ2 Q0 D0 = XQ1 + XQ2 + Q2 Q0 + X Q1 Q0 S = XQ1 + XQ2 + Q2 Q0 + Q1 Q0

ptb/dkb (March 20, 2006)

Some Design Examples

ptb/dkb (March 20, 2006)

ptb/dkb (March 20, 2006)

Out (z) x=0 0 0 0 x=1 0 0 1

Moore Implementation (using D flip-flops)

Example (contd.): Output Waveforms

ptb/dkb (March 20, 2006)

Example: Moore Machine

even (0) odd (1)

even (0) odd (1)