Department of Computer Science & Engineering Indian Institute of Technology, Guwahati

CS223: COMPUTER ORGANISATION LABORATORY

LAB REPORT

4 BIT CPU
By Group 12
Chander Prakash Garg (03010108) Vikrant Chahar (03010132) Vinay Kumar Tibrewal (03010134)

Under the guidance of Dr. S. B. Nair & Dr. Pinaki Mitra

Date of Completion: 19th April, 2005 Date of Submission: 21st April, 2005

DESIGN CHARACTERISTICS
Hardwired control unit. 15 control signals. 4 bit data bus. 8 bit address bus. 14 instructions are supported. 256 bytes of usable memory to store the opcodes. 4 general purpose internal registers. 4 bit ALU. One internal register is used as memory buffer register (MBR). This register is also the default register for ALU operations. Only Load and Store operations access the memory. All ALU operations are register based. Out of 14 instructions, 8 require two clock pulses and remaining 6 require five clock pulses to be executed completely. An 8 bit register is used as program stack for use in Call and Return instructions.

INSTRUCTION SET
The CPU has an instruction set containing 14 instructions. So the opcode is of four bits. Following are the instructions along with their opcodes: INSTRUCTION NOT OR AND ADD SUB MOV JUMP JZERO LOAD STORE CALL HALT SET RET OPCODE 0000 0001 0010 0011 0100 0101 1000 1001 1010 1011 1100 1101 1110 1111

BLOCK DIAGRAM

HARDWARE DESIGN
1. CONTROL UNIT
The CPU has a hardwired control unit. The design is based on the sequence counter method. The control unit generates signals for synchronization of both the internal and external data buses. It also generates signals like gate control of tristate buffers, load signal for appropriate register, function selects for the ALU, increment signal for program counter etc. Inputs to the control unit are the opcode, operand and the master clock. The control unit uses a counter with synchronous clear along with these inputs to generate the sequence of controls.

2. ALU DESIGN
The ALU consists of a 74LS181 chip. All arithmetic / logical operation are done by this chip. 74181 is a 24 pin IC which acts as a 4-bit ALU. This chip has 6 control inputs which define the operation to be performed. These select inputs are generated by the control unit according to the opcode by the help of a combinational circuit. The ALU takes two operands. One of them comes from the default register and another can come from any of the four internal registers. The output of the ALU operation is stored back to the default register. A tristate buffer is provided between ALU output and register inputs to avoid bus contention at the time of LOAD operation. ALU is used for the following six operations: NOT, AND, OR, ADD, SUB and MOV. In all other cases the ALU remains unused.

3. PROGRAM STORE
There are two ways to execute instructions. One way is to load one instruction directly into the opcode and the operand register. When the CPU is used in this mode some operations like CALL, RET, JUMP and JZERO cease to have any relevance. The other way in which instruction can be executed is by placing them in a semiconductor storage medium such as RAM or EPROM which has at least a word length of 4-bits. The length of such medium is no constraint but the program counter can access only 255 locations. The program to be executed has to be stored in the chip and the CPU will start executing it starting with the instruction stored in the address #0000 and will continue execution until it encounters a HALT instruction.

4. MAIN MEMORY
The Main Memory consists of the RAM chip 2114. The actual size of the memory is 1024 x 4 bits. But in this architecture only 8 address lines are used so only 256 memory locations are accessed. The data bus is used for LOAD as well as STORE operations. Tristate buffers are used so that the same bus can be used for both read and write operations.

5. INTERNAL REGISTERS
Four internal registers have been used. They are designated as A, B, C and D. The registers have following addresses: A 00 B 01 C 10 D 11 The register A acts as accumulator for ALU operations and as MBR for LOAD and STORE operations. The results of ALU operations are stored back in the register A. Also value is loaded from or stored in memory from register A. The other three registers (B, C, D) are general purpose internal registers.

6. PROGRAM COUNTER, MAR and PROGRAM STACK REGISTER

Program counter is made by cascading two 74LS161 chips. 74LS161 is 4 bit binary counter with asynchronous clear. Asynchronous clear is used to reset the program counter to address #0000. This counter has synchronous parallel load facility which is utilized in case of CALL, RET, JUMP, JZERO operations. Memory Address Register (MAR) and program stack are made from two 74LS95 chips. 74LS95 is PIPO register. MAR is used to hold memory address in case of LOAD and STORE. In addition to this MAR is also used in CALL, RET, JUMP and JZERO to hold the address to be set in the program counter. The program stack is used to store the contents of the program counter in case of CALL operation. After storing the contents of program counter in program stack, program counter is loaded with the new address. This architecture supports single call. In case of multiple calls the returning addresses of previous calls are lost. Both Program counter and MAR can address the memory. Normally program counter addresses the memory. In case of LOAD and STORE, MAR addresses the memory. Who will provide the address is decided by the control unit and is controlled using a tristate buffer.

INSTRUCTION FORMAT & CYCLEWISE-EXECUTION 1. NOT (0000)

This is a logical ALU operation in which bit wise binary inversion of the contents of accumulator is done. Its format is Opcode: 0000 Operand: 00xx xx in the operand signifies that these bits are not used for this operation. As this is a unary operation only the two most significant bits of the operand are used. The result of this operation is stored back in the accumulator (register 00).

2. OR (0001)
This is another logical ALU operation. Its format is: Opcode: 0001 Operand: 00ab This performs bitwise OR operation on the contents of the accumulator (00) and the register specified by ab part of operand and stores the result of the operation back in the accumulator.

3. AND (0010)
This is another logical ALU operation. Its format is: Opcode: 0010 Operand: 00ab This performs bitwise AND operation on the contents of the accumulator (00) and the register specified by ab part of operand and stores the result of the operation back in the accumulator.

4. ADD (0011)
This is arithmetic ALU operation. Its format is: Opcode: 0011 Operand: 00ab This performs arithmetic addition operation on the contents of the accumulator (00) and the register specified by ab part of operand and stores the result of the operation back in the accumulator. The carry bit generated is not handled in this architecture. It is simply ignored.

5. SUB (0100)
This is arithmetic ALU operation. Its format is: Opcode: 0011 Operand: 00ab This performs arithmetic subtraction operation on the contents of the accumulator (00) and the register specified by ab part of operand and stores the result of the operation back in the accumulator. In other words it performs A X where X is any internal register. The carry bit generated is not handled in this architecture. For these five ALU operations various steps of execution process are shown in the following figure:

Thus it is clear that these ALU operations take two clock cycles to be executed.

6. MOV (0101)
This instruction is used to move the contents of one internal register to other. The contents are moved through the ALU. Format of this instruction is: Opcode: 0101 Operand: abxy where ab is the address of the destination register and xy is the address of the source register. The data is piped through the input B of ALU and is stored in required register. For this operation various steps of execution process are shown in the following figure:

Thus it is clear that this ALU operation also takes two clock cycles to be executed.

7. JUMP (1000)
This is the unconditional jump instruction. It is used to set the program counter to a value other than the succeeding location. Its format is: Opcode: 1000 Operand: abcd efgh where abcd is the lower nibble of destination address and efgh is the higher nibble. After opcode fetch, abch is fetched and stored in MARs lower four bits. Then efgh is stored in MARs higher four bits. Then these 8 bits are loaded in the program counter so that execution starts from desired location. For this operation various steps of execution process are shown in the following figure. This operation takes five clock cycles.

8. JZERO (1001)
This is the conditional jump instruction. It is used to set the program counter to a value other than the succeeding location on the condition that the contents of accumulator are zero. Its format is: Opcode: 1001 Operand: abcd efgh where abcd is the lower nibble of destination address and efgh is the higher nibble. After opcode fetch, abcd is fetched and stored in MARs lower four bits. Then efgh is stored in MARs higher four bits. Then these 8 bits are loaded in the program counter when the jump condition is satisfied so that execution starts from desired location. A four bit comparator 74LS85 chip has been used to compare the value of accumulator. For this operation various steps of execution process are nearly similar to that of JUMP instruction. It also takes five clock cycles to be executed.

9. LOAD (1010)
This is one of the two memory access instructions. This is used to bring the contents of a memory location into the registers of the CPU. Its format is: Opcode: 1000 Operand: abcd efgh where abcd is the lower nibble of address of memory location and efgh is the higher nibble. After opcode fetch, abcd is fetched and stored in MARs lower four bits. Then efgh is stored in MARs higher four bits. Then these 8 bits are then used to select the memory location from where the loading is to be done. The fetched value gets loaded in the accumulator cum MBR (register 00). For this operation various steps of execution process are shown in the following figure. This operation takes five clock cycles.

10. STORE (1011)

This is the other instruction that accesses the memory. This is used to store the content of accumulator into the main memory. The construct is similar to that of LOAD. Its format is: Opcode: 1000 Operand: abcd efgh where abcd is the lower nibble of address of memory location and efgh is the higher nibble. When this instruction is executed the contents of the accumulator is stored into the memory. For this operation various steps of execution process are shown in the following figure. This operation takes five clock cycles.

11. CALL (1100)

This is the instruction used to make a subroutine call. When this is done the current value of program counter (PC) is stored in the program stack register and then the program counter is set to the value depending on the location to which the call takes place. Its format is: Opcode: 1000 Operand: abcd efgh where abcd is the lower nibble of address of memory location where the subroutine is located and efgh is the higher nibble. In this architecture, only the value of program counter is saved. Neither of the internal registers are saved in program stack register. Since the program stack register can store only one address multiple calls in succession are not supported. It is the burden of programmer to take into account this limitation. Also if he wants to save the values of internal registers he has to do it manually using STORE and MOV instructions.

For this operation various steps of execution process are shown in the following figure. This operation takes five clock cycles.

12. HALT (1101)

This is the instruction used to signify the end of the program. It opcode is 1111. After this instruction the clock to the entire CPU is disabled. The state of the registers are frozen and they continue to store the value last held by them. This instruction is irreversible and execution cannot be continued without putting the power back on again. For this instruction the timing diagram is:

13. SET (1110)

This is an assignment operation. This is used to set a fixed 4 bit binary number into the accumulator. This instruction is not a register operation and the operand specifies the number to be stored in the accumulator rather than the register, as in other instructions. Its format is: Opcode: 1110 Operand: abcd where abcd is the value to be set in accumulator.

For this operation various steps of execution process are shown in the following figure. This operation takes two clock cycles.

14. RET (1111)

This is used to return from a subroutine call. When this instruction is executed the contents of the stack register is set into the program counter. Thus the program continues execution from the location following the one from which call took place. The contents of the operand register are immaterial in the case of this instruction. Its format is: Opcode: 1111 For this operation various steps of execution process are shown in the following figure. This operation takes two clock cycles.

IMPLEMENTATION
REGISTER ORGANIZATION
The registers in the architecture can be broadly divided into two categories, special registers and general purpose registers. This classification is by no means mutually exclusive and some registers seem to have characteristics of both especially the accumulator.

SPECIAL REGISTERS

1. Instruction Register
This actually consists of two registers one opcode register and the other called operand register. Opcode register is used to store the operation code of the instruction that is currently being executed. This forms the input for the instruction decoder. It is also because of this arrangement that it is possible to execute instructions one after the other by directly entering the opcode into the register. Operand register holds the operands of the instruction currently being executed. The output of this register is used for all ALU related instructions. The value stored here is send to two decoders which select appropriate internal registers for read and write operations. The two MSB are used to write enable accumulator (or some other register in case of MOV) and two LSB are used to read enable a register.

2. Program Stack Register

This is the register where the program counter is stored when a CALL instruction takes place. The stack register actually consists of two 4 bit registers. This register stores the program counter. The value stored in this register is used to reset the program counter in the case of RET.

3. Accumulator
This can be considered to be a general purpose register cum MBR. This is a register that is available to the programmer space. This is the register where all the results of all ALU operations are stored. This is also the only register which can interact with the RAM memory by means of LOAD and STORE. Assignment operation can also take place only into this register. This register is referred to by the code 00. Accumulator can perform all the functions that can be performed by all other registers and can be used for all manipulations by the programmer.

GENERAL PURPOSE REGISTERS

They are four in number including the accumulator. The programmer can use them for both data storage and manipulation. They can be used as input to the ALU; either as first operand or second, but the result of the ALU operation comes into the accumulator and has to be shifted to other register by means of MOV instruction.

 SUBROUTINE SUPPORT
The architecture has built in support for function call. A programmer may make a subroutine call to any location in the program store, execute instructions there and then jump back to the initial location. He is not required to handle to which location he has to jump back to. This is handled by the architecture. Only one level of subroutine call is supported. Thus recursion is not supported. At the heart of the subroutine call support is the program stack register. This register stores the value of the program counter whenever a function call takes place. Also in this case the incremented value of program counter is stored in the stack. This value is set back into the program counter whenever a return statement is encountered.

JUMP SUPPORT
The architecture supports two kinds of jump statements. In both cases the appropriate value as specified in the operands is set in the program counter. There are two types of jumps. An unconditional jump where the jump always takes place and a conditional jump in which case the jump takes place only if the contents of the accumulator are zero. For conditional jump a comparator is used. A flag register was not maintained thus ALU output could not be used for a jump.

CONTROL LOGIC 1. CLOCKING MECHANISM

A continuous clock pulse goes into the control unit. The control unit generates various signals based on the opcode and then uses AND and OR gates to generate clock signals for registers, program counter, sequence counter, MAR, Program stack etc. Both positive and negative edges of clock are used for instruction execution. The executions of various instructions are already shown above along with their timing diagrams.

2. HALT MECHANISM
Halt is the only instruction that is executed single clock cycle. When this instruction is executed the clock to the whole CPU is stopped. This is done by ANDing the output of the appropriate pin of the negative high instruction decoder with the clock. When a HALT instruction (#1101) is selected then the output of the decoder becomes 0 and this instruction cannot change as even for the instruction to change a clock pulse is required.

3. SEQUENCE COUNTER
The control unit uses a 4 bit counter with synchronous clear to keep track of number of cycles elapsed after opcode fetch. This counter is a 74LS163 chip which has synchronous clear facility. At the start this counter is initialized to 0000. The control unit is so designed that when output of this counter is 0000 then opcode fetch will take place on negative going edge of clock pulse. When the opcode corresponds to instructions being executed in two clock cycles, this counter is synchronously cleared at 0001. In other cases it is cleared at 0100. Thus next opcode is fetched either after two clock cycles or after five clock cycles. In this way execution takes place until a HALT is encountered.

ICs USED
Following chips have been used for realizing above the CPU design. Sr. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Chip No. 7404 7408 7432 7475 7485 7495 74153 74154 74155 74157 74161 74163 74181 74194 74367 2114 Description No. of chips used Hex Inverter 8 Quad 2 input AND 8 Quad 2 input OR 6 Quad latch 4 4 bit comparator 1 4 bit PIPO register 5 Dual 4 to 1 MUX 2 4 to 16 Decoder 2 Dual 2 to 4 decoder 3 Quad 2 to 1 MUX 3 4 bit counter 2 4 bit counter 1 4 bit ALU 1 4 bit register with clear 1 Hex tristate buffer 8 1K x 4 bit RAM 1

SAMPLE PROGRAM
The program given to us was swap the contents of two locations in the main memory. Following program was written for this: Memory Address 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 0001 0000 0001 0001 0001 0010 Contents (Program) 1010 0001 0001 0101 1100 1010 0010 0001 1011 0001 0001 0101 0011 1011 0010 0001 1101 1111 1001 Description * LOAD into A from first memory location * MOVE contents of A to D * LOAD into A from second memory location * STORE contents of A into first memory location * MOVE contents of D to A * STORE contents of A into second memory location * HALT * First memory location * Second memory location

The program was loaded in RAM. The program executed successfully. At the end of execution the contents of memory were: Memory Address 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 0001 0000 0001 0001 0001 0010 Contents (Program) 1010 0001 0001 0101 1100 1010 0010 0001 1011 0001 0001 0101 0011 1011 0010 0001 1101 1001 1111 Description

* First memory location * Second memory location

Thus the swapping took place and was demonstrated to the invigilator.

MERITS AND DEMERITS OF THE DESIGN

MERITS
1. It is a custom design. 2. Speed of execution is higher than that of microprogrammed design. 3. The instruction set resembles to that of a RISC architecture thus simplifying the implementation. 4. Four internal registers reduce the number of memory accessions. 5. The SET instruction enables direct assignment to accumulator thus reducing the need of LOAD instruction.

DEMERITS
1. 2. 3. 4. Upgradeability is poor and difficult to achieve No support for multiple successive calls. Lengthy design and implementation time. Large number of ICs used to make control unit.