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Jntu Hyd 2 2ece Eca Set 3
Jntu Hyd 2 2ece Eca Set 3
S.37
Set-3
Solutions
Max. Marks: 75
Time: 3 Hours Answer any FIVE questions All questions carry equal marks --1. (a) (b) 2. (a) (b) 3. (a)
When n-identical stages of amplifier are cascaded? Derive the expression for lower and upper cutoff frequencies. (Unit-II, Topic No. 2.1) Explain the effect of coupling capacitor in a CE amplifier on low frequency response of amplifier. [8+7] (Unit-II, Topic No. 2.1) A transistor supplies 0.8 W to a 5 k load. The zero signal DC collector current is 30 mA and the DC collector current with signal is 36 mA. Determine the percent second-harmonic distortion. (Unit-VII, Topic No. 7.4) Define conversion efficiency. Determine the maximum value of conversion efficiency for a series-fed class A power amplifier. [7+8] (Unit-VII, Topic No. 7.2) For the circuit shown in below figure, compute AI, AV, AVS, Ri and R'o. The transistor h-parameters are hie = 1.1 k, (hfe = 50, hre = 2.4 x and hoe = 25 A/V). (Unit-II, Topic No. 2.1)
VCC 100
8K 100 K
+ VS
500 VEE
3K V o
Ro
Figure (b) 4. (a) (b) 5. (a) (b) (c) Compare direct coupled amplifiers with RC coupled amplifier. [10+5] (Unit-II, Topic No. 2.4) Obtain CC h parameters interms of CE parameters. (Unit-I, Topic No. 1.3) For a CE amplifier, calculate the voltage gain, input impedance output impedance, current gain. If RL = 10 k, hie = 1.1 k, hre = 2.5 104, hfe = 50, hoe = 24 A/V. [7+8] (Unit-I, Topic No. I.3) Why a FET cannot be explained with h-parameters? (Unit-IV, Topic No. 4.1) Derive an expression for transconductance using FET model. (Unit-IV, Topic No. 4.1) Draw and explain the FET high frequency model. [3+6+6] (Unit-IV, Topic No. 4.1)
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6. (a) (b) 7. (a) (b) (c)
Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Sketch a circuit of a crystal-controlled oscillator and explain its function. (Unit-VI, Topic No. 6.5) Explain the frequency-stability criterion for a sinusoidal oscillator. [8+7] (Unit-VI, Topic No. 6.6) Compare neutralisation and unilaterlisation methods of tuned amplifiers. (Unit-VIII, Topic No. 8.7) What are the limitations of stagger tuned amplifiers? (Unit-VIII, Topic No. 8.6) What happens when number of stages is increased in single tuned cascaded amplifiers? [5+5+5] (Unit-VIII, Topic No. 8.4) What is negative feedback? Discuss how it can improve stability in an amplifier. (Unit-V, Topic No. 5.1) Find Avf, Rif, Rof, for the circuit shown in figure. Rs = 0, hfe = 50, hie = 1100 and hre and hoe are negligible. Assume identical transistors. [5+10] (Unit-V, Topic No. 5.4)
VCC 50 k 5 f Vi 50 k 2k Q1 50 k 2k 10 k Cb 50 k 10 k Cb
8.
(a) (b)
Q2
100
4.2 k
Figure
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(a)
Vi VS ~ +
R1 ||R2
Ri
hfe Ib
RL Vo
Figure (i): Low Frequency Model for CE Amplifier with Coupling Capacitor For large values of emitter bypass capacitor (CE), the low frequency gain does not experience any reduction in its value and the emitter resistance RE is effectively bypassed. The reactance of coupling capacitor (CC) is negligible for mid frequency range. The lower 3-dB frequency (f1) is given as,
1 f1 = 2( R + R ' )C s i C
... (1)
Where, R'1 = R1 || R2 || Ri Ri = hie (for ideal CE) and Ri ~ hie + (1 + hfe) RCE (when capacitors series resistance is considered). Therefore, inorder to achieve good low frequency response, the capacitors CC and CE must be maintained large. Q2. A transistor supplies 0.8 W to a 5 k load. The zero signal DC collector current is 30 mA and the DC collector current with signal is 36 mA. Determine the percent second-harmonic distortion. Answer : April/May-12, Set-3, Q2(a) M[7] Given that, For a transistor, AC power supplied (PA.C) = 0.8 W Load resistance, RL = 5 k DC collector current, ICQ = 30 mA Collector current with signal i.e., ICQ + B0 = 36 mA ... (1) Percentage in second-harmonic distortion, D = ? (a)
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Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Define conversion efficiency. Determine the maximum value of conversion efficiency for a series-fed class A power amplifier. Answer : April/May-12, Set-3, Q2(b) M[8] For answer refer Unit-VII, Q3, [Note: Exclude, Topic: Importance of Position of Operation point and Collector Efficiency]. Q3. (a) For the circuit shown in below figure compute AI, AV, AVS, Ri and R' o. The transistor h-parameters are hie = 1.1 K, hfe = 50, hre = 2.4 and hoe = 25 A/V.
VCC 100
(b)
B2 100 B1
... (2)
Where, B1 and B2 are constants. (i) Computation of B2 Since, B2 = B0 From equation (1), we have, B0 = 36 ICQ = 36 30 B0 = 6 mA (ii) B2 = 6 mA [Q From equation (3)] ... (4) ... (3)
8K 100 K
500 VEE
3K V o
1 2 2 R L [ B2 + B2 ] = 0.8 2
R o
1 2 5 103 [ B1 + (6 10 3 ) 2 ] = 0.8 2
2 B1 =
1. 6 5 10 3
(6 103)2
Figure April/May-12, Set-3, Q3(a) M[10] Answer : Note: In the given question value of the hre is incomplete. Given that, For a circuit, hie = 1.1 k hfe = 50 hre = 2.4 104 (Assume) hoe = 25 A/V AI = ?, AV = ?, AVS = ?, Ri = ?, R'o = ?
VCC
100
6 10 3 100 16.852 10 3
VS
500
3k V o VEE R o
% D = 35.6
D = 35.6%
Figure (1)
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I b1
RS=10 k +
+ 8 k
R E1 =
Ic2
VS + ~
V1
V2
R E2
=100
R1 =3 k
2
500
R 01
R i2
Vo
R i1
R 02
RO
Figure (2) Second Stage Analysis Here, RE2 = RL hoe RL = (25 106) 100 = 0.0025 < 0.1 Since, hoe RL < 0.1, approximate analysis method is used. Current Gain ( A i 2 )
Ai2 =
I E2 I b2
hfe
= 50
Ai2 = 50
Input Resistance ( R i )
2
Ri2 = h + (1 + h ) RE 2 ie fe
= 1.1 103 + (1 + 50)100 = 6.2 103
Ri2 = 6.2 k
Voltage Gain ( A V2 )
AV2 =
= 24.194
AV2 = 24.194
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First Stage Analysis
Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Output Resistance Output admittance,
h fe hre y o1 = h oe h + R
ie
R C1
R i2
R L1
RC1 ,
' Ro = RC1 || R o1 1
R L1 = 3.5 k
Current Gain ( A i1 )
RC1 Ro1 = R +R C1 o1
=
I c1 Ai1 = I b1 hfe
= 50
' Ro = 6.7 k 1 ' Ro is the source resistance for the second stage, 1
Ai1 = 50
Input Resistance ( R i1 )
Hence,
Ri1 = h + (1 + h ) R E1 ie re
= 1.1 10 + (1 + 50) 500 = 26.6 10
3 3
y o2 = h oe
Ri1 = 26.6 k
= 25 106 Voltage Gain ( A V1 ) = 2.35 105
A R V AV1 = 2 = i1 L1 V1 Ri1
=
= 6.58
AV1 = 6.58
Ro2 = 42.6 k
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Ro2 RE2
Q R o 2 || R E 2
Ri1 AVS = AV Ri + RS 1
Ro = 99.76
Overall Current Gain (Ai)
Ib Ai = Ai2 2 Ic 1 Ai 1
I b2
= 159.2
AVS = 115.7
Compare direct coupled amplifiers with RC coupled amplifier. Answer : April/May-12, Set-3, Q3(b) M[5] For answer refer Unit-II, Q31, Topics: RC Coupling, Direct Coupling. Q4. (a)
R i2
(b)
C1
Ic1
R C1
Answer :
I b2 I c1
Ib
hie + H V re ce hfe Ib
Ic
Vhe
hoe
Vce
I b2 I c1
Figure (1) = 0.563 The h-parameter model of CE configuration is redrawn in CC configuration is as shown in figure (2) with Vce = Vec
Ai = Ai2
I b2 I c1
Ai1
Ib
hie
hre Vce +
Ie
E +
Vbe
hfe Ib
hoe
Ai = 1407.5
Overall Voltage Gain (AV)
C
Vce
V2 Vo Vo AV = V = V = V 1 2 1
= AV2 AV1 = 24.194 ( 6.58) = 159.2
Figure (2) Applying KVL at the inner loop, we get, Vbc hie Ib hre Vce Vec = 0 Vbc = hieIb + hre Vce + Vec = hieIb hre Vec + Vec Vbc = hieIb +(1 hre)Vec (Q Vec = Vce) ... (1)
AV = 159.2
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Applying KCL at node E, we get, Ie = Ib hfeIb + hoe Vec Ie = (1 + hfe) Ib + hoe Vec For CC configuraton, Vbc = hic Ib + hrc Vec Ie = hfc Ib + hoc Vec hic in Terms of CE Configuration From equation (3),
Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 hfc in Terms of CE Configuration From equation (4), we get, ... (2) hfc =
Ie Ib
Vec = 0
(1 + h fe ) I b + hoeVec Ib
Vec = 0
(1 + h fe ) I b + 0 Ib
Vbc hic = I b
= (1 + hfe)
Vec = 0
h fc = (1 + h fe )
Vec = 0
hie I b + o = Ib
hic = hie
Ie Vec
I b =0
(1 + h fe ) I b + hoeVec Vec
Ib =0
hic = hie
hrc in Terms of CE Configuration From equation (3)
0 + hoeVec Vec
= hoe
hoc = hoe
Ib = 0
Ib =0
hrc = 1
For CE amplifier, calculate the voltage gain input impedance output impedance, current gain. If RL = 10 , hie = 1.1 k, hre = 2.5 104, hfe = 50, hoe = 24 A/V. Answer : April/May-12, Set-3, Q4(b) M[8] Given that, For a CE amplifier, RL = 10 k hfe = 50 hoe = 24 A/V = 24 106 A/V hre = 2.5 104 hie = 1.1 k = 1100 Current gain (AI) = ? Input impedance (Zi) = ? Voltage gain (AV) = ? Output impedance (Zo) = ? Assuming RS = 1 k.
(b)
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Figure (i): Hybrid Model for CE Amplifier Current Gain (AI) The expression for current gain, AI of a single stage CE amplifier is given by, AI =
h fe 1 + hoe .R L
50 1 + 24 10 6 10 10 3
AI = 40.32
= 403.6
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Output Impedance The expression for output admittance, Yo of a single stage CE amplifier is given by, Yo = hoe
h fe .hre hie + RS
Yo = (24 106)
1 Yo
1
Ib
hie
Ic
Vb
hreVc
1 h oe
hfeIb
VC
E
Figure (1) and the small signal model of FET is CS configuration is shown in figure (2).
Id
Vgs g mVgs
rd
Vds
S
Figure (2)
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From figure (1) it is clear that the output current generated depends on the input base current. But, FET being a voltage controlled device, the output current generated must depend on the input voltage, which is not possible using hparameter model. In addition to the above characteristic, the presence of feedback from output to input through hre parameter is also makes the h-parameter models invalid for FET as shown in figure (1). Thus, a FET amplifier cannot be analyzed using h-parameter model. However, the FET model shown in figure (2) is a low frequency model and is not valid in the high frequency range. (b) Derive an expression for transconductance using FET model. April/May-12, Set-3, Q5(b) M[6] Answer :
Transconductance gm is defined as the ratio of change of current at the output to the change in the input voltage and given by,
gm =
I D VGS
... (1)
Now, consider the relationship between ID and VGS is non-linear. Therefore, the Schokleys equation when the terms are non-linear is given by,
... (2)
... (3)
gm =
2 I DSS VP
VGS 1 V P
... (4)
gm =
2 I DSS VP
2 I DSS I DS I DS = VP I DSS
2 I DSS I DS VP
2 VP I DSS I DS
gm =
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Hence proved. Where, gm = Transconductance IDS = Saturation drain current
IDSS = It is the value when the gate is shorted to source i.e., VGS = 0 VP = Pinch-off voltage. (c) Answer : The high frequency model of FET is as shown in figure, Draw and explain the FET high frequency model. April/May-12, Set-3, Q5(c) M[6]
Cgd G D
Cgs
g mVgs
rd
Cds
S
Figure : High Frequency Model of FET
High frequency model of FET amplifier is obtained by adding capacitance between the nodes of FET low frequency model Cgs, Cds and Cds are the internal capacitances which are responsible for feedback from output to input and decrease of voltage amplification at higher frequencies. Where, Cgs Barrier capacitance between gate and source Cgd Barrier capacitance between gate and drain Cds Drain to source capacitance of the channel. The various parameters of FET with their corresponding magnitudes are as listed in table-1. Device Parameter JFET MOSFET gm 0.10-10 mA/VM 0.1-20 mA/V rd 0.1-1 pF 1-50 k Cds 0.1.1 pF 0.1.1 pF Cgs,Cgd 1-10 1-10 pF r gs >10
8
>1010
Table 1: Parameter Values of FET (JFET and MOSFET) Q6. (a) Sketch a circuit of a crystal-controlled oscillator and explain its function. April/May-12, Set-3, Q6(a) M[8]
Answer : For answer refer Unit-VI, Q21, Topic: Working of Quartz crystal.
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April/May-12, Set-3, Q6(b) M[7]
Answer : The comparison of between neutralization and unilateralisation are as follows, Neutralisation 1. Neutralisation is one of the technique used for reducing the feedback effect provided by inter junction capacitance Cb'C to obtain better stability. 2. Achieves stability only for a certain band of frequencies. 3. It removes only reactive feedback.
Unilateralisation 1. Unilateralisation is a special case of neutralisation where-in a bilateral network is converted into a unilateral network. 2. Achieves stability at almost all frequencies.
4. It is highly dependent on cancellations. 5. It attempts to eliminate feedback to maximum possible extent. 6. No miller effect is observed. (b) Answer :
What are the limitations of stagger tuned amplifiers? April/May-12, Set-3, Q7(b) M[5]
The following are the limitations of stagger tuned amplifiers, 1. 2. 3. 4. 5. It provides reduced selectivity. The tuning of most tank circuits is critical. It has low input impedance at high frequencies. Needs large number of IF stages. Simultaneous maintenance of broad bandwidth and high gain is required. (c) Answer : For answer refer Unit-VIII, Q24. Q8. (a) What is negative feedback? Discuss how it can improve stability in an amplifier. April/May-12, Set-3, Q8(a) M[5] What happens when number of stages is increased in single tuned cascaded amplifiers? April/May-12, Set-3, Q7(c) M[5]
Answer : Negative Feedback For answer refer Unit-V, Q1, Topic: Negative Feedback. Stability For answer refer Unit-V, Q6, Topic: Gain Stability.
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(b)
Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Find Avf, Rif, Rof, for the circuit shown in figure 9. Rs = 0, hfe = 50, hie = 1100 and hre and hoe are negligible. Assume identical transistors.
VCC 50 k 5 f Vi 50 k 2k Q1 50 k 2k 10 k Cb 50 k 10 k Cb
Q2
100
Figure Answer : Given that, For a circuit, with two-identical transistors, RS = 0 hfe= 50 hio = 1100 hre and hoe are negligible (i.e., hre = hoe = 0). The given circuit is as shown in figure (i).
4.2 k
VCC 50 k 5 f Vi 50 k 2k Q1 50 k 2k 10 k Cb 50 k 10 k Cb
Q2
100
4.2 k
Figure (i) The input circuit is obtained by making Vo = 0. Hence, the first emitter how consists of a in figure (ii). The output circuit is obtained by making Ii = 0. This provides a resultant circuit with the series combination of look and 4.2 k as shown at the output terminals of figure (ii).
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50 k
10 k
50 k
10 k V0
Vi 50 k
Q1 2k 4.2 k
Figure (ii)
100 k 50 k 2k 4.2 k
100 k
I b1
hie B1 + Vce Ib
Ic1
C1 hoe 10 k
BI b2
hie
C2
50 k||50 k VCC
Vi
V2
E1
E1
E2
Figure (iii) Analysis of Second Stage (CE Amplifier) As hoe RL = hoe RC2 = 0 < 0.1 (Q hoe is negligible)
Ai2 =
I E2 I b2
h fe
=
' 1 fhoe RL
hie = 1100
Ri2 = 1100
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Voltage Gain
' Ai2 RL Vo =V = Ri'2 2
AV2
Where, R'L = (100 k + 4.2 k) || 10.k = 104.2 k || 10 k = 9.12 103 R'L = 9.12 k
' And Ri2
AV2 =
Ri'2
AV2 = 433.3 First Stage Analysis CCE Amplifier with Unbypassed RE The net load resistance R L1 of this stage is obtained by,
R L1 = RC || Ri' 1 2
= 10 k || 1.05 k = 950.23 R L1 = 950.23 Current Gain ( A i1 )
I c1 h fe Ai1 = = I b1 1 + hoe R L1
hfe = 50 Ai1 = 50 Input Resistance ( R i1 )
Ri1 = h + (1 + h ) R E1 ie fe
= 1100 + (1 + 50) (100 k|| 4.2 k) = 1.30 103
Ri1 = 1.30 k
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50 950.213 1.30 10 3
= 36.54
AV1 = 36.54
y o1 = h oe
h fe hre hie + Rs
y o1 = 0
1 1 R o1 = y o1 = 0 =
Ro' 1 = Rc` || Ro = 10 k || = 10 k
1
y o2 = h oe
= h + R' 0 ie o1
h fe
y o2 = 0
1 1 Ro2 = y o2 = 0 =
= || 9.12 k = 9.12 k
Ro f = 9.12 k
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Overall Input Resistance
Ri f = Ri || R 1 B
= 1.30 k || (50 k || 50 k) = 1.30 || 25 k \ 3.47 103
Ri f = 1.235 k
Vo V0 Vo AV f = V1 = V2 V1
= AV2 AV1 = 433.3 36.54 = 15832.7
AV p = 15.83 103
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