7 AR 15

7 BR

0 Accumulators 0

0 Condition-Code Register Carry/Borrow Overow Zero

1 1 H I N Z V C

XR 15 PC 15 SP 0 0

Index Register

Program Counter

Negative Interrupt Mask Half Carry (from bit 3)

Stack Pointer

EmbeddedSystems Laboratory Motorola M6800 Microprocessor

BOOL/ARITH OPERATION CONDITION CODES1 5 H 4 I 48 58 2 2 1 1 C R R R R R R R R R R R R 2 2 2 2 2 2 R R R R R 2 2 2 R R R R R S S S 3 R R R S S S R R R R R R R R 2 2 2 2 2 2 R R 3 N 2 Z 1 V 0 C INHERENT # OP 1B 2 # 1 (Each register label refers to contents of register) A+BA A+M+CA B+M+CB A+MA B+MB AMA BMB

ADDRESSING MODES ACCUMULATOR and MEMORY OPERATIONS Add Accumulators Add with Carry MNEM. ABA ADCA ADCB Add ADDA ADDB And ANDA ANDB Arithmetic Shift Left ASL ASLA ASLB Arithmetic Shift Right ASR ASRA ASRB Bit Test BITA BITB Compare Accumulators Clear CBA CLR CLRA CLRB Compare CMPA CMPB Complement, 1s COM COMA COMB Decimal Adjust, A Decrement DAA DEC DECA DECB Exclusive Or EORA EORB Increment INC INCA INCB Load Accumulator LDAA LDAB Logical Shift Right LSR LSRA LSRB Negate NEG NEGA NEGB Or, Inclusive ORAA ORAB Push Data PSHA PSHB Pull Data PULA PULB Rotate Left ROL ROLA ROLB Rotate Right ROR RORA RORB Subtract Accumulators Subtract with Carry SBA SBCA SBCB Store Accumulator STAA STAB Subtract SUBA SUBB Transfer Accumulator TAB TBA Test Value TST TSTA TSTB Copyright c 2002, 2003 by David C. Pheanis, all rights reserved. 6D 7 2 7D 6 3 4D 5D 2 2 1 1 80 C0 2 2 2 2 82 C2 2 2 2 2 92 D2 97 D7 90 D0 3 3 4 4 3 3 2 2 2 2 2 2 A2 E2 A7 E7 A0 E0 5 5 6 6 5 5 2 2 2 2 2 2 B2 F2 B7 F7 B0 F0 4 4 5 5 4 4 3 3 3 3 3 3 16 17 2 2 1 1 66 7 2 76 6 3 46 56 10 2 2 2 1 1 1 69 7 2 79 6 3 49 59 2 2 1 1 8A CA 2 2 2 2 9A DA 3 3 2 2 AA EA 5 5 2 2 BA FA 4 4 3 3 36 37 32 33 4 4 4 4 1 1 1 1 60 7 2 70 6 3 40 50 2 2 1 1 86 C6 2 2 2 2 96 D6 3 3 2 2 A6 E6 64 5 5 7 2 2 2 B6 F6 74 4 4 6 3 3 3 44 54 2 2 1 1 88 C8 2 2 2 2 98 D8 3 3 2 2 A8 E8 6C 5 5 7 2 2 2 B8 F8 7C 4 4 6 3 3 3 4C 5C 2 2 1 1 6A 7 2 7A 6 3 4A 5A 2 2 1 1 81 C1 2 2 2 2 91 D1 3 3 2 2 A1 E1 63 5 5 7 2 2 2 B1 F1 73 4 4 6 3 3 3 43 53 19 2 2 2 1 1 1 6F 7 2 7F 6 3 4F 5F 2 2 1 1 85 C5 2 2 2 2 95 D5 3 3 2 2 A5 E5 5 5 2 2 B5 F5 4 4 3 3 11 2 1 67 7 2 77 6 3 47 57 2 2 1 1 89 C9 8B CB 84 C4 2 2 2 2 2 2 2 2 2 2 2 2 99 D9 9B DB 94 D4 3 3 3 3 3 3 2 2 2 2 2 2 A9 E9 AB EB A4 E4 68 5 5 5 5 5 5 7 2 2 2 2 2 2 2 B9 F9 BB FB B4 F4 78 4 4 4 4 4 4 6 3 3 3 3 3 3 3 IMMEDIATE OP # OP DIRECT # OP INDEXED # EXTENDED OP

 
b7 b0

 0 b0 C

b7 AM BM AB 00 M 00 A 00 B AM BM MM AA BB

Convert Binary Addition of BCD M1M A1A B1B AMA BMB M+1M A+1A B+1B MA MB

b7 00 M M 00 A A 00 B B AMA BMB b0

A MSP , SP 1 SP B MSP , SP 1 SP SP + 1 SP, MSP A SP + 1 SP, MSP B


C b7


b0

-- C b7
ABA AMCA BMCB AM BM AMA BMB AB BA M 00 A 00 B 00

b0

January 15, 2003

ADDRESSING MODES XR and SP OPERATIONS Compare XR Decrement SP Decrement XR Increment SP Increment XR Load SP Load XR Store SP Store XR SP + 1 XR XR 1 SP MNEM. CPX DES DEX INS INX LDS LDX STS STX TSX TXS 8E CE 3 3 3 3 9E DE 9F DF 4 4 5 5 2 2 2 2 AE EE AF EF 6 6 7 7 2 2 2 2 BE FE BF FF 5 5 6 6 3 3 3 3 30 35 4 4 1 1 IMMEDIATE OP 8C 3 # 3 OP 9C DIRECT 4 # 2 OP AC INDEXED 6 # 2 EXTENDED OP BC 5 # 3 34 09 31 08 4 4 4 4 1 1 1 1 INHERENT OP #

BOOL/ARITH OPERATION (Each register label refers to contents of register) XMS M, XLS (M + 1) SP 1 SP X1X SP + 1 SP X+1X M SPMS , (M + 1) SPLS M XMS , (M + 1) XLS SPMS M, SPLS (M + 1) XMS M, XLS (M + 1) SP + 1 X X 1 SP 5 H

CONDITION CODES1 4 I 3 N 4 2 Z 1 V 5 R R R R 0 C

JUMP and BRANCH OPERATIONS Branch if Carry Set Branch if Carry Clear Branch if Minus Branch if Plus Branch if Overow Set Branch if Overow Clear Branch if Equal Branch if Not Equal Branch if < (Signed) Branch if (Signed) Branch if (Signed) Branch if > (Signed) Branch if Lower or Same (Unsigned) Branch if Higher (Unsigned) Branch Always Branch to Subroutine Jump Jump to Subroutine No Operation Return From Interrupt Return From Subroutine Software Interrupt Wait for Interrupt MNEM. BCS BCC BMI BPL BVS BVC BEQ BNE BLT BLE BGE BGT BLS BHI BRA BSR JMP JSR NOP RTI RTS SWI WAI

RELATIVE OP 25 24 2B 2A 29 28 27 26 2D 2F 2C 2E 23 22 20 8D 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6E AD OP

INDEXED #

EXTENDED OP #

INHERENT OP # C=1 C=0 N=1 N=0 V=1 V=0 Z=1 Z=0 NV=1 Z (N V) = 1 NV=0 Z (N V) = 0 CZ=1 CZ=0 Branch Relative Push PC; Branch Relative BRANCH TEST

5 H

4 I

3 N

2 Z

1 V

0 C

4 8

2 2

7E BD

3 9

3 3 01 3B 39 3F 3E 2 10 5 12 9 1 1 1 1 1

Jump Absolute Push PC; Jump Absolute Only Advance Program Counter Pull Interrupt Stack Frame Pull PC Push Interrupt Stack Frame; Vector Push Interrupt Stack Frame; Wait

S 6

CONDITION-CODE OPERATIONS Clear Carry Clear Interrupt Mask Clear Overow Set Carry Set Interrupt Mask Set Overow AR CC CC AR MNEM. CLC CLI CLV SEC SEI SEV TAP TPA

INHERENT OP 0C 0E 0A 0D 0F 0B 06 07 2 2 2 2 2 2 2 2 # 1 1 1 1 1 1 1 1

BOOLEAN OPERATION 0C 0I 0V 1C 1I 1V A CC CC A

5 H

4 I R S

3 N

2 Z

1 V R S

0 C R S

Condition-Code Notes: 1. Bits 7 and 6 of CC are always set. 2. Sets CC.V = N C after shift has occurred. 3. CC.C = 1 if BCD result > 9910 ; otherwise, CC.C = 0. 4. CC.N = Sign bit from subtraction of MS bytes. 5. CC.V = Twos-complement overow from subtraction of MS bytes. 6. Sets CC.I when interrupt occurs. If previously set, a NonMaskable Interrupt is required to exit from the wait state.

Interrupt Vectors
FFF8 FFF9 FFFA FFFB FFFC FFFD FFFE FFFF IRQ IRQ SWI SWI NMI NMI Reset Reset MS LS MS LS MS LS MS LS

Interrupt Stack
SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 SP + 7 CC BR AR XRMS XRLS PCMS PCLS

Legend: OP Operation Code (Hexadecimal) Number of MPU Cycles # Number of Program Bytes + Arithmetic Plus Arithmetic Minus Arithmetic Multiply Boolean AND Boolean Inclusive OR Boolean Exclusive OR Transfer Into LS Least Signicant MS Most Signicant M Memory Operand MSP Mem. byte that SP addresses

M 0 00 CC R S H I N Z V C

Ones Complement of M Bit = Zero Byte = Zero Condition-Code register Set if true, cleared otherwise Not Aected Reset Always Set Always Half Carry from bit 3 Interrupt Mask Negative (sign bit) Zero (byte) Overow, Twos Complement Carry from bit 7

Powers of Two
n 0 1 2 3 4 5 6 7 2n 1 2 4 8 16 32 64 128 $2 n $01 $02 $04 $08 $10 $20 $40 $80 n 8 9 10 11 12 13 14 15 2n 256 512 1,024 2,048 4,096 8,192 16,384 32,768 $2 n $0100 $0200 $0400 $0800 $1000 $2000 $4000 $8000 n 16 17 18 19 20 21 22 23 2n 65,536 131,072 262,144 524,288 1,048,576 2,097,152 4,194,304 8,388,608 $2 n $01,0000 $02,0000 $04,0000 $08,0000 $10,0000 $20,0000 $40,0000 $80,0000 n 24 25 26 27 28 29 30 31 2n 16,777,216 33,554,432 67,108,864 134,217,728 268,435,456 536,870,912 1,073,741,824 2,147,483,648 $2 n $0100,0000 $0200,0000 $0400,0000 $0800,0000 $1000,0000 $2000,0000 $4000,0000 $8000,0000 n 32 33 34 35 36 37 38 39 2n 4,294,967,296 8,589,934,592 17,179,869,184 34,359,738,368 68,719,476,736 137,438,953,472 274,877,906,944 549,755,813,888 $2 n $01,0000,0000 $02,0000,0000 $04,0000,0000 $08,0000,0000 $10,0000,0000 $20,0000,0000 $40,0000,0000 $80,0000,0000