Proceedings

International Verilog HDL

Conference and VHDL
International Users Forum
March 16 - 19, 1998
Santa Clara, CA
Sponsored by

Open Verilog International

VHDL International
In cooperation with

IEEE Computer Society

Electronics Industries Association Japan

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Washington

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Table of Contents
International Verilog HDL Conference and VHDL International Users Forum
Preface ........................................................................................................................................

...

viii

1998 IVCMUF Conference ......................................................................................................

ix

Steering Committee ....................................................................................................................

Program Committee ..................................................................................................................

xi

IVC 1998 Best Paper Award Winners ...................................................................................

mi

MUF 1998 Best Paper Award Winners ...............................................................................

xiii

ISession 1: Technology or Compiler Technology Directions

Chair: P. George, ACE0 Technology, Inc.
1.1: Integrating of Verilog-HDL and VHDL Languages in the SMASH TM
Mixed-signal Multi-level Simulator......................................................................................
P. Sauge and G. Thuau
1.2: A Case Study of Compaqs Simulation Environment Migration to
Windows NT ............................................................................................................................
W.R. Stresau
1.3: Incremental Compilation in the VCS Environment ...........................................................
V.K. Sundar, A.V. Naik, and D.R. Chowdhury
1.4: Transitioning to the New PLI Standard .............................................................................
S. Sutherland
1.5: Implementing C Designs in Hardware: A Full-Featured ANSI C to RTL
Verilog Compiler in Action ...................................................................................................
D.Soderman and Y. Panchul

ISession 2: Language Issues

..

...

J
,2

7
14
20

22

Chair: S. Bailey, VeriBest, Inc.

2.1: A Procedural Language Interface for VHDL and Its Typical Applications ......................
F. Martinolle and A. Sherer
2.2: VHDL 200x - Requirements from Testbench-View ............................................................
M. Bauer, W. Ecker, and M. Heuchling
2.3: Considerations on System-Level Behavioural and Structural Modeling
Extensions to VHDL .............................................................................................................
P.J. Ashenden and P.A. Wilsey

:32

39

42

I Session 3: Silicon Centric RTL

~

Chair: T. OConnor, Avid Technology Inc.

3.1: Practical FSM Analysis for Verilog .....................................................................................
T.-H. Wang and T. Edsall

52

3.2: Guidelines for Safe Simulation and Synthesis of Implicit Style Verilog ..........................
M.G. Arnold, N.J. Sample, and J.D. Shuler
3.3: Verilog Nonblocking Assignments Demystified ................................................................
C.E. Cummings

59
.67

Chair: D. Barton, Intermetrics, Inc.

4.1: Process-Level Modeling with VHDL ................................................................................... 72
J. Armstrong
4.2: Tools for Rapid Construction of VHDL Performance Models for DSP Systems ............... 77
F.G. Gray, G.A. Frank, B. Clark, D.Ziegenbein,
S. Vuppala, and P. Balasubramanian
4.3; Modeling Communication with Objective VHDL ...............................................................
83
W. Putzke-Roming, M. Radetzki, and W. Nebel
4.4: Application of VHDL to Software Radio Technology ......................................................... 90
J . McCloskey

I Session 5: Customizing the Simulation Environment

Chair: B. Erickson, Compaq Computer Corp.
5.1: Verilog Plus C Language Modeling with PLI 2.0: The Next Generation
Simulation Language ...........................................................................................................
S. Meyer
5.2: EP3: An Extensible Per1 Preprocessor .............................................................................
G. Spiuey
5.3: A Mixed-Language Simulator for Concurrent Engineering ............................................
D.A. Burgoon
5.4: A Strategy for C-Based Verification ..................................................................................
P. Herman

98
106
114
120

ISession 6: Legacy and Reuse

Chair: L. Concha, United States Air Force
6.1: Reuse of Models and Testbenches at Different Levels of Abstraction ............................
G.A. Frank, F.G. Gray, S. Gopalakrishnan,
and W. Song
6.2: ModelMaker: A Tool for Rapid Modeling from Device Descriptions ..............................
W.R. Cyre and A. Gunawan
6.3: Improving VHDL Soft-Cores Reuse with Software-like Reviews
and Audits Procedures .......................................................................................................
S. Olcoz, A. Castellui, and M . Garcia

130

138

143

I Session 7: VerificationNalidationPTestbench Strategies

~

~~

Chair: A. Herbert, IKOS Systems, Inc.

7.1: Overcoming the Limitations of Self-checking Stimulus through the
Use of an ASIC Mirror ........................................................................................................
R.D. Benson

vi

148

7.2: A Pseudorandom Test Environment .................................................................................

R.F. Beckwith, B. Wood, B. Rioux, and B. Singer
7.3: Networked Object Oriented Verification with C++ and Verilog .....................................
G. Dearth, S. Meeth, and P. Whittemore
7.4: A Loosely Coupled CNerilog Environment for System Level Verification .....................
A.S. Meyer

153
158
165

7
Chair: J. Willis, FTL Systems, Inc.
8.1: A Functional Test Planning System for Validation of DSP Circuits
Modeled in VHDL ...............................................................................................................
M.-W. Lin, J.R. Armstrong, G.A. Frank,
and L. Concha
8.2: Scan Parallel Loading in VHDL ........................................................................................
J.P. Vo
8.3: STG Timing Extensions and Simulation...........................................................................
M.V. Goncharov, A.B. Smirnov, I.V. Klotchkov,
and N.A. Starodoubtsev
8.4: SAVANTPTYVISIWARPED:
Components for the Analysis and
Simulation of VHDL ...........................................................................................................
P.A. Wilsey, D.E. Martin, and K. Subramani
Author Index ............................................................................................................................

vii

1'72

1'78
1138

1!35

202