Digital Microelectronic Digital Microelectronic Circuits Circuits ( (

Digital Microelectronic Digital Microelectronic
Circuits Circuits
((361 361--1 1--3021 3021 ))
Presented by: Dr. Alexander Fish
Digital Microelectronic Circuits Digital Microelectronic Circuits The VLSI Systems Center The VLSI Systems Center -- BGU BGU Lecture Lecture 77: The CMOS Inverter : The CMOS Inverter 11
The CMOS The CMOS
Inverter Inverter
Lecture Lecture 77::
Motivation Motivation
The Inverter, or NOT gate, is truly the
nucleus of all digital designs.
We will analyze the inverter and find its
characterizing parameters.
Once its operation and properties are
clearly understood, designing and
In Out
0 1
1 0
In Out
Digital Microelectronic Circuits Digital Microelectronic Circuits The VLSI Systems Center The VLSI Systems Center -- BGU BGU Lecture Lecture 77: The CMOS Inverter : The CMOS Inverter
clearly understood, designing and
analyzing more intricate structures, such
as NAND gates, adders, multipliers and
microprocessors is greatly simplified.
This lecture focuses on the static CMOS
inverter the most popular at present and
the basis for the CMOS digital logic family.
22
What will we learn today? What will we learn today?
7.1 An Intuitive Explanation
7.2 Static Operation
7.3 Dynamic Operation
7.2.1 The Inverters VTC
7.2.2 Operating Regions
7.2.3 Switching Threshold
7.2.4 Noise Margins
7.3.1 Parasitic Capacitances
7.3.2 Propagation Delay
7.4 Power Consumption
7.5 Summary
7.3.3 Device Sizing -
7.3.4 Device Sizing S
7.3.5 Sizing a Chain of Inverters
7.4.1 Dynamic Power
7.4.2 Short Circuit Power
7.4.3 Static Power
7.4.4 Total Power Consumption
AN INTUITIVE EXPLANATION AN INTUITIVE EXPLANATION
As usual, well start with
44
+
-
V
An Intuitive Explanation An Intuitive Explanation
A Static CMOS Inverter is modeled on
the double switch model.
The basic assumption is that the
switches are Complementary, i.e.
when one is on, the other is off.
V0
When the top switch is on, the supply
voltage propagates to the output
node.
When the bottom switch is on, the
ground voltage is propagated out.
55
Now we will replace the model switches
with real voltage controlled switches
MOS Transistors.
We will use complementary transistors
one nMOS and one pMOS, and hook
them up to the same input voltage.
V =V
+
-
V
V
out
=0
V =0
V
out
=V
in
them up to the same input voltage.
Now, when we set a high input voltage,
the nMOS is on and the pMOS off. The
ground voltage propagates.
When we put a low input voltage, the
pMOS is on and the nMOS is off. The
supply voltage propagates.
Weve built an inverter!
66
V
in
=V V
in
=0
V
out
=V
in
The voltage connected to the Source of the pMOS is
known as the Supply Voltage or V
DD
.*
We mark the connection to V
DD
with a horizontal or
slanted bar.
Accordingly, V
DD
represents a logical 1 and GND
represents a logical 0.
represents a logical 0.
Inputting V
DD
to the CMOS inverter will present GND
at the output. Inputting GND will present V
DD
at the
output.
This characteristic is non-trivial and is one of the
advantages of CMOS design. It is known as Rail to
Rail Swing.**
77
* It can also be called V
CC
, regarding the Collector of BJT transistors.
** Rails are the supply voltages, i.e. V
DD
and GND. If a voltage is connected
to the nMOS Source instead of GND, we refer to this voltage as V
SS
.
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
STATIC OPERATION STATIC OPERATION
Now that we understand the principles,
well analyze
99
The Inverters VTC The Inverters VTC
To construct the VTC of the CMOS inverter,
we need to graphically superimpose the I-V
curves of the nMOS and pMOS onto a
common coordinate set.
We can see that: I
SDp
I I =
V
SGp V
SDp
Digital Microelectronic Circuits Digital Microelectronic Circuits The VLSI Systems Center The VLSI Systems Center -- BGU BGU Lecture Lecture 77: The CMOS Inverter : The CMOS Inverter 10 10
I
DSn
SDp DSn
I I =
GSn in
V V =
SGp DD in
V V V =
DSn out
V V =
SDp DD out
V V V =
V
GSn
V
out
V
in
V
DD
V
DSn
Since V
in
and V
out
are the input and output voltages of the
nMOS transistor, we will change the coordinates of the
pMOS.
V
SGp
=2.5
out DD SDp
V V V =
I
SDp
V =1.5
V
in
=0
I
DSn
V
SGp
=1
out DD SDp
V
SDp
V
in
=1.5
DSn SDp
I I =
V
out
in DD SGp
V V V =
For V
DD
=2.5V
Now, we will superimpose the modified pMOS I-V curves on
the nMOS I-V graphs:
I
DSn
V
in
=0 V
in
=V
DD
The intersection of corresponding load lines shows the DC
operating points, where the currents of the nMOS and pMOS
are equal.
V
out
V
in
=0
V
in
=V
DD
/2 V
in
=V
DD
/2
V
in
=V
DD
Putting all the intersection points on a graph with the
corresponding output voltage will give us the CMOS
inverters VTC:
V
out
V
DD
V
in
V
DD
/2
V
DD
/2
V
DD
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Operating Regions Operating Regions
Lets figure out what region of operation each transistor is in
throughout the VTC curve.*
V
out
V
DD
* Considering Long Channel Transistors
With V
TH
<V
DD
/2
in TH
V V <
GSn in TH
V V V Cutoff = <
V
SGp V
SDp
V
out
V
in
V
DD
/2
V
DD
/2
V
DD V
TH
GSn in TH
V V V Cutoff = <
V
GSn
SGp DD in TH
SDp DD out TH SGp
V V V V
Linear
V V V V V
= >
`
= <
)
So now, lets jump to the other side of the VTC.
V
out
V
DD
in DD TH
V V V >
SGp DD in TH
V V V V Cutoff = <
V
SGp
V
in
V
DD
/2
V
DD
/2
V
DD V
DD
-V
TH
V
GSn
GSn in DD TH TH
DSn out GSn TH
V V V V V
Linear
V V V V
= > >

`
= <
) V
DSn
V
out
Now, back to the VTC regions. Lets see what happens
when we raise the input voltage slightly past V
TH
.
V
out
V
DD
in TH
V V >
GSn in TH
V V V = >
V
SGp V
SDp
V
out
V
in
V
DD V
TH
+V
GSn in TH
DSn out DD GSn TH
V V V
Sat
V V V V V
= >
`
= >
)
V
GSn
0
SGp DD in TH
SDp DD out SGp TH
V V V V
Linear
V V V V V
= >
`
= <
)
The same when V
in
is a bit more than V
TH
lower than V
DD
.
V
out
V
DD
in DD TH
V V V V =
SGp DD in TH
V V V V = >
V
SGp V
SDp
V
in
V
DD V
DD
-V
TH
-V
SGp DD in TH
SDp DD out DD SGp TH
V V V V
Sat
V V V V V V
= >
`
= >
)
V
GSn
0
GSn in TH
DSn out GSn TH
V V V
Linear
V V V V
= >
`
= <
)
V
out
Finally, we have the middle area, where:
V
out
V
DD
2
in DD
V V V =
2
2
SGp DD in DD TH
SDp DD out DD SGp TH
V V V V V
Sat
V V V V V V
= >
`
= >
)
V
SGp V
SDp
V
in
V
DD V
DD
/2
V
GSn
V
out
2
2
GSn in DD TH
DSn out DD GSn TH
V V V V
Sat
V V V V V
= >
`
= >
)
To Sum it up:
V
out
V
DD
Towards the rails, one of the transistors
is cut off, and the other is resistive.
Once the cut off transistor starts
conducting, it immediately is saturated.
nMOS off
pMOS - res
nMOS sat
pMOS - res
V
in
V
DD
As we approach the middle input
voltages, both transistors are saturated.
The VTC slope is known as the Gain of
the gate.
pMOS - res
nMOS sat
pMOS - sat
nMOS res
pMOS - sat
nMOS res
pMOS - off
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Switching Threshold Switching Threshold
The Switching Threshold, V
M
, is the point where V
in
=V
out
.
This can be calculated:
Graphically, at the intersection of the VTC with V
in
=V
out
V
out
V
DD
Or analytically, by equating the nMOS and pMOS saturation currents
with V
in
=V
out
.
22 22
V
in
V
DD
V
M
Lets analytically compute V
M
.
Remember, the saturation current for a MOSFET is given by:
Lets assume =0 and well equate the two currents:
( ) ( )
2
2
p
n
k
k
I V V V V = =
( ) ( )
2
1
2
DS GS TH DS
k
I V V V = +
Now well substitute:
And well arrive at:
23 23
( ) ( )
2
2
2 2
p
n
D GSn Tn SGp Tp
k
k
I V V V V = =
GSn in M
V V V = =
SGp DD in DD M
V V V V V = =
( )
1
Tn DD Tp
M
V r V V
V
r
+
=
+
p
n
k
r
k

A similar analytic evaluation for short channel devices with
a current of:
Will bring us to:
2
DSAT
DS DSAT GS TH
V
I kV V V
| |
=
|
\
V
V | |
And assuming V
Tn
=V
Tp
and V
DD
is much larger than V
TH
and
V
DSAT
, we can estimate:
24 24
2 2
1
DSATp
DSATn
Tn DD Tp
M
V
V
V r V V
V
r
| |
+ + + +
|
\
=
+
p DSATp
short
n DSATn
k V
r
k V
2 1 1
DSAT short DD short DD
M T
short short
V r V r V
V V
r r

= + +
+ +
As we can see, r is an important factor in setting the
threshold voltage.
r is a design parameter, that is set by the drive strength
ratios of the nMOS and pMOS:
_
p
long channel
k
r
k
ox
W W
k k C
L L
=
Using the current equations again, we can find the drive
strength ratio for a desired V
M
:
25 25
_ long channel
n
r
k
ox
k k C
L L
=
2
p
M Tn
n DD M Tp
k
V V
k V V V
| |
= |
|

\
A symmetric VTC (V
M
=V
DD
/2) is often desired. In this case:
Generally, the same length (L) is taken for all transistors in
digital circuits, and so for a symmetric VTC:
n
p n p
W W
L L
| | | |
=
| |
\ \
( )
2 1
Tn DD Tp
DD
M
V r V V
V
V
r
+
= =
+
digital circuits, and so for a symmetric VTC:
26 26
2...4
p
n
n p
W
W
=
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Remember our definitions of Noise Margins from Lecture 3.
Noise Margins Noise Margins
V(y)
V
OHmin
Slope = -1
"1"
V
OHmin
V
IH
Undefined
Region
NM
H
V(x)
V
OLmax
V
IH
V
IL
Slope = -1
V
M
max
min
L IL OL
H OH IH
NM V V
NM V V
=
=
"0"
V
IL
V
OLmax
Region
NM
L
One of the CMOS logic familys advantages is a Full Rail to
Rail Swing. In other words:
To calculate the Noise Margins, we will need to find V
IL
and
V
IH
. These are the points where the gain is -1.
max
min
OH DD
OL
V V
V GND
=
=
V
IH
. These are the points where the gain is -1.
To do this we will equate the
currents:
V
IL
nMOS sat, pMOS res
V
IH
nMOS res, pMOS sat
29 29
V
out
V
in
V
DD
V
DD
1
out
in
dV
dV
=
1
out
in
dV
dV
=
nMOS sat
pMOS - res
nMOS res
pMOS - sat
Lets calculate V
IH
:
Assuming matching devices (k
n
=k
p
, V
Tn
=V
Tp
):
Differentiating and equating -1, we reach:
( ) ( ) ( ) ( )
2
2
2 2
p
DSn
DSn n GSn Tn DSn DSp GSp Tp
k
V
I res k V V V I sat V V
(
= = =
(

( ) ( )
2
2 1
2 2
out
IH TH out DD IH TH
V
V V V V V V =
Differentiating and equating -1, we reach:
Doing the same for V
IL
or using symmetry, we reach:
Accordingly, for a matched long-channel device, and
assuming V
OHmin
V
OHmax
and V
OLmax
V
OLmin
in CMOS, we get:
30 30
( )
1
5 2
8
IH DD TH
V V V =
( )
1
3 2
8
IL DD TH
V V V = +
( )
1
0 3 2
8
H L DD IH IL DD TH
NM NM V V V V V = = = +
A different approach is to use a piece-wise linear
approximation:
OH OL DD
IH IL
V V V
V V
g g
= =
V
out
V
DD
g
M
IH M
V
V V
g
=
DD M
IL M
V V
V V
g
= +
V
in
V
DD
V
IH
V
IL
g g
H DD IH L IL
NM V V NM V = =
With this approach, finding the inverters gain will show us
the noise margins with a very small error.
We will find the gain at the mid-point (both transistors are
saturated) of a short-channel device:
Differentiating, we get:
( ) ( )
1 1
2 2
DSATp
DSATn
D n DSATn in Tn n out p DSATp DD in Tp p DD p out
V
V
I k V V V V k V V V V V V
| |
| |
= + = +
| |
\
\
( ) ( )
+ + +
Ignoring some second order expressions and substituting
V
in
=V
M
, we arrive at:
32 32
( ) ( )
( ) ( )
1 1
/ 2 / 2
n DSATn n out p DSATp p DD p out
out
in n n DSATn in Tn DSATn p p DSATp DD in Tp DSATp
k V V k V V V
dV
dV k V V V V k V V V V V

+ + +
=
+
( ) ( )( )
1 1
/ 2
n DSATn p DSATp
D M n p M Tn DSATn n p
k V k V
r
g
I V V V V
+
+
=

DYNAMIC OPERATION DYNAMIC OPERATION
Now that we see how the inverter behaves in
steady state, we will analyze its transient:
33 33
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Parasitic Capacitances Parasitic Capacitances
Remember that our transistors have capacitance connected
to the output node.
Well calculate the capacitance values a bit later,
but for now, lets just use and equivalent
output capacitance.
When the input is low our pMOS is a
When the input is low our pMOS is a
non-linear resistor and our nMOS is
cut off, so we get a simple RC circuit.
Our capacitance is charged, bringing
the output voltage to V
DD
.
35 35
+
-
V
C
eq
V
DD
When the input is high, we essentially have closed the top
switch and opened the bottom one.
This creates a resistive path from the capacitor to GND, and
blocks the path from the supply to the output.
Again we have an RC network, though this time
we are just discharging the capacitance to GND.
we are just discharging the capacitance to GND.
We end up with an output equal to GND.
36 36
C
eq
0
So we saw that, a switching CMOS inverter charges and
discharges a parasitic output capacitance.
During the switching process, we can create a model that
will transform the circuit into a simple RC network.
In this way, we can easily derive a first order analysis of the
CMOS dynamic operation for propagation delay and power
consumption calculation.
Our first goal is to represent all the parasitic capacitances
by one output capacitance between the output node and
ground.
37 37
Lets remember the MOSFET capacitances that we learned
in Lecture 4:
G
C
GD
C
GS
GS GCS GSO
C C C = +
GD GCD GDO
C C C = +
D
S
B
C
SB
C
DB
C
GB
GB GCB
C C =
SB Sdiff
C C =
DB Ddiff
C C =
Well start with the obvious:
Taking the input step as ideal, the gate-to-source
and gate-to-body capacitances dont contribute
to the propagation delay.
The source-to-body capacitance is shorted to the
supply, so it doesnt switch.
C
GSP
+C
GBP
C
GDP
+C
GDN
What about the gate-to-drain capacitance?
While the gate voltage rises (V
in
), the drain
voltage drops (V
out
) and vice versa.
According to the Miller Effect, we can move this
capacitance relative to ground, doubling its
value.
39 39
C
GSN
+C
GBN
2(C
GDP
+C
GDN
)
And last we have diffusion capacitances:
Both drain-to-body capacitances have a
terminal with a constant voltage and the
other connected to the output.
For a simple computation, we will replace
them with an equivalent capacitance to ground.
C
DBP
them with an equivalent capacitance to ground.
These capacitances are very non-linear and
we will not go into their calculation in this
course.
40 40
C
DBN
C
DBP
+C
DBN
Now, to annotate the parasitics during switching, we will
cascade another inverter after the first.
We first add the Wire Capacitance.
Then we add the gate capacitances of
the second inverter.
These are approximately the oxide
P1
P2
C
GP2
These are approximately the oxide
capacitance times the area:
Again, we can just add the pMOS gate
capacitance to the general capacitance to
ground.
N1
P1
P2
N2
41 41
C
GN2
C
W
( )
2 2 2 2 2 2 GN GP OX N N P P
C C C W L W L + +
Altogether, as a very general approximation, we get:
An even more general approximation
with N fan-out gates gives us:
P1
P2
C
GP2
C
DBP1
( ) ( )
1 1 1 1 2 2
2( )
load GDP GDN DBP DBN GP GN W
C C C C C C C C = + + + + + +
C C C N C = + +
N1
P1
P2
N2
C
GN2
C
DBN1
+C
W
C
GDP1
+C
GDN1
C
DBP1
load out wire in
C C C N C = + +
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Propagation Delay Propagation Delay
Now that we know the load capacitance of the CMOS
inverter, we can write:
Assuming an ideal step at the input, the propagation delay, t
( ) ( )
0
1
t
out
load
V t i t dt
C
=

( )
( )
2
1
v
load
pd
v
C v
t dv
i v
=
Assuming an ideal step at the input, the propagation delay, t
pd
is the time it takes the output to (dis)charge 50% of its
voltage.
We will look at three ways to calculate the propagation
delay:
By solving the integral above.
By approximating the average current
By using equivalent resistance
44 44
Propagation Delay Propagation Delay Method Method 1 1
Well start with V
in
=0. Accordingly, P1 is
open and N1 is closed, causing the output
voltage to be held at V
out
=V
DD
At t=0, V
in
changes from 0 to V
DD
, closing
P1 and opening N1.
This causes the output to discharge
This causes the output to discharge
like a first order RC network.
45 45
V
DD
C
eq
t
V
in
t
V
out
t=0
V
DD
At this point V
DSn
=V
DD
>V
GS
-V
TH
, so N1 is in saturation and
the discharge current is given by:
Assuming =0 and integrating until N1 enters the linear
( ) ( )
2
1
2
n
DSn In TH out
k
I V V V = +
Assuming =0 and integrating until N1 enters the linear
region:
46 46
( )
( )
( )
1
2
2
DD TH
DD
V V
DD DD TH
load
p
V
n
D
DD TH
C V V V
C
t dv
k
i sat
V V
(

= =
t
V
out
V
DD
V
DD
/2
V
DD
-V
TH
t
p1
t
pHL
Now V
DSn
<V
GS
-V
TH
and so N1 goes into linear operation
with:
Well write an expression for the change in voltage:
( ) ( )
2
2
out
DSn n in TH out
V
I res k V V V
(
=
(

( )
2
2
DSn n out
out in TH out
i k V
dV dt V V V
C C
(
= =
(

And arrive at the following integral:
47 47
2
load load
C C
(

( )
( )
1
2
2
2
1
2
pHL DD
DD TH
t V
load out
p
t V V
n DD TH
out out
DD TH
C dV
t dt
k V V
V V
V V
= =

t
V
out
V
DD
V
DD
/2
V
DD
-V
TH
t
p1
t
pHL
t
p2
Using the equality:
We get:
2
1
ln 1
dx
ax x ax
| |
=
|
2
3 4
ln
load DD TH
p
C V V
t
| |
=
|
t
V
out
V
DD
V
DD
/2
V
DD
-V
TH
t t
t
p2
( )
( )
2
2
2
1
2
DD
DD TH
V
load out
p
V V
n DD TH
out out
DD TH
C dV
t
k V V
V V
V V
==
And putting together the two parts, we get:
For V
TH
=0.2V
DD
, we get:
48 48
2
ln
p
n DD
t
k V
=
|
\
( )
1 2
2 1 3 4
ln
2
load TH DD TH
pHL p p
n DD TH DD TH DD
C V V V
t t t
k V V V V V
( | |
= + = +
( |

\
1.6
load
pHL
n DD
C
t
k V
=
t
p1
t
pHL
As mentioned earlier, using a different approach, we can
approximate this delay using average currents.
We will find the average current between t=0 and t=t
pHL
and
calculate:
( ) ( )
2
1
0
DD
load
load
pHL
V
C
C V
t
i
i i t
=
(
+
Knowing that i
DSn
(0) is saturation current with V
DSn
=V
DD
and
i
DSn
(t
pHL
) is linear current with V
DSn
=0.5V
DD
, we get:
49 49
( ) ( )
1
0
2
DSn
avg
DSn DSn pHL
i
i i t
(
+

1.7
load
pHL
n DD
C
t
k V

As seen above, the derivation of the propagation delay in a
direct and accurate way is quite complex.
A general and more intuitive option is to derive a linear
equivalent resistance for a transistor that gives a good
estimation that is much simpler to analyze.
estimation that is much simpler to analyze.
The primary approach to deriving such an equivalent
resistance is to calculate the transistors average resistance
throughout its operation (ON) period.
50 50
( ) ( ) ( )
( )
( )
( ) ( )
2 2
1 2
1 1
... 1 2
2 1 2 1
1 1 1
2
t t
DS
eq t t t on on on on
DS t t
V t
R average R t R t dt dt R t R t
t t t t I t
=
= = = + (

Now, we will calculate the propagation delay of a short
channel inverter, by using the equivalent resistance to
discharge a capacitor from V
DD
to V
DD
/2.
Assuming V
DD
>>V
DSATn
, we can assume
that throughout the propagation delay,
that throughout the propagation delay,
the transistor is velocity saturated.
We can write:
51 51
( )
/ 2
1 3 7
1
/ 2 4 1 9
DD
DD
V
DD
eq DD
DD DSAT DSAT V
V V
R dV V
V I I V
| |
=
|
+
\
( )
2
2
DSAT
DSAT n DD TH DSAT
V
I k V V V
(
=
(

Now that we know the equal resistance, we can use a first
order RC network with a step function input for annotation:
0
out out in
load
eq
dV V V
C
dt R
+ =
( )
( )
1
t
out DD
V t e V
=
R C
For propagation delay computation, we will use V
1
(t)=V
DD
and V
2
(t)=V
DD
/2 and we arrive at:
52 52
( )
( )
1
out DD
V t e V =
eq load
R C
ln(2) 0.69 0.69
pHL n n eqn load
t R C = = =
Similarly for a Low to High transition, we arrive at:
The overall propagation delay is defined as the average of
the two:
0.69 0.69
pLH p eqp load
t R C = =
the two:
53 53
( )
0.69
2 2
load eqp eqn pLH pHL
pd
C R R t t
t
+ +
=
To calculate and analyze the parameters that affect the
propagation delay, we will take =0 and get:
Accordingly, we can minimize the delay in the following
3
0.69 0.52
4
2
DD DD load
pHL load
DSAT DSATn
n DSATn DD Tn
V V C
t C
V I
k V V V
= =
| |

|
\
Accordingly, we can minimize the delay in the following
ways:
Minimize C
load
.
Increase W/L
Increase V
DD
54 54
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Device Sizing Device Sizing --
Device Sizing is the Width to Length ratio (W/L) of the
transistor.
When discussing a CMOS logic gate, we relate to the the
pMOS/nMOS ratio ((W
p
/L
p
)/(W
n
/L
n
)). We will call this ratio .
To get a balanced inverter (i.e. V
m
=V
DD
/2) we usually will
need =3-3.5, mainly due to the mobility ratio of holes and
need =3-3.5, mainly due to the mobility ratio of holes and
electrons.
This generally equates the propagation delay of High-to-
Low and Low-to-High transitions.
However, this does not imply that this ratio yields the
minimum overall propagation delay.
56 56
How can this be?
To get a faster t
pLH
, we need to enlarge the pMOS width.
This increases the parasitic capacitance (C
load
), degrading t
pHL
.
We will now find the optimum ratio for sizing an inverter.
As usual, we will consider two identical cascaded CMOS
As usual, we will consider two identical cascaded CMOS
inverters. The load capacitance of the driving gate is:
Now we will mark the device size ratio as :
57 57
( ) ( )
1 2 1 1 2 2 load out in wire dp dn gp gn wire
C C C C C C C C C = + + = + + + +
( )( )
1 2
1
load dn gn wire
C C C C = + + +
( )
( )
p
n
WL
WL

Noting that we have reduced the equivalent resistance of
the pMOS by , we can write the first order RC propagation
delay:
( ) ( )( )
1 2
0.69
0.345 1
2
eqp
load
pd eqn eqp dn gn wire eqn
R
C
t R R C C C R
| |
(
= + = + + + +
|

\
Now we just need to find the minimum:
A typical optimum for is usually around 2.
58 58
0
pd
dt
d
=
( ) 1 2
1 2
1
dn gn wire
eqp eqp
wire
opt
eqn dn gn eqn
C C C
R R
C
R C C R
+ >>
| |
= + |
|
+
\
Conclusions:
A balanced inverter isnt usually the fastest possible
inverter.
A typical optimal pMOS/nMOS ratio for performance is
given by:
given by:
59 59
2
eqp
opt
eqn
R
R

7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Device Sizing Device Sizing -- SS
We saw how the ratio between the pMOS and nMOS can
be optimized to improve performance.
Now, we will take a balanced inverter and see how upsizing
affects the intrinsic or unloaded delay.
We will start by writing the delay as a function of the
intrinsic capacitance (diffusion and overlap) and the extrinsic
capacitances (fanout and wiring):
61 61
( ) ( )
load diff overlap fanout wire int ext
C C C C C C C = + + + +
( )
int
0.69 0.69
pd eq load eq ext
t R C R C C = = +
Now, we will mark the minimal intrinsic delay as t
p0
. This is
the delay of a minimum sized balanced inverter only loaded
by its own intrinsic capacitance (C
ext
=0):
We will now mark the sizing factor, S. This is the relative
upsizing of the inverter, i.e. C
int
=SC
ref
and accordingly
0
0.69
p ref ref
t R C
upsizing of the inverter, i.e. C
int
=SC
ref
and accordingly
R
eq
=R
ref
/S.
Now we can write the delay of an upsized inverter:
62 62
( ) ( )
int 0
0.69 0.69 0.69 1 1
ref
ext ext
pd eq ext ref ext ref iref p
ref ref
R
C C
t R C C SC C R C t
S SC SC
| | | |
= + = + = + = + | |
| |
\ \
Conclusions:
The intrinsic delay of an inverter (t
p0
) is independent of
the sizing of the gate and is purely determined by
technology. When no load is present, an increase in the
drive of the gate is totally offset by the increased
0
1
ext
pd p
ref
C
t t
SC
| |
= + |
|
\
drive of the gate is totally offset by the increased
capacitance.
To minimize a loaded inverters delay, S should be
enlarged, but at the expense of a substantial gain in
area.
63 63
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Sizing a chain of inverters Sizing a chain of inverters
As with everything in life, inverter sizing presents a number
of trade-offs:
The larger the load, the slower the driving gate.
To make the driving gate faster, upsizing is needed.
The more the gate is upsized, the higher the intrinsic capacitance,
which slows the gate down and presents a larger load capacitance
to the preceding gate.
To optimize this problem, instead of using one big inverter,
we will analyze the effect of a gradually increasing chain of
inverters.
65 65
To explore this problem, we must define a proportionality
factor, .
is a function of technology*, that describes the
relationship between a gates input gate capacitance (C
g
)
and its intrinsic output capacitance (C
int
):
int g
C C
Now, we will write the delay as a function of , and the
effective fanout, f:
We can see that the delay for a certain technology is only a
function of the effective fanout!
66 66
* is close to 1 for most submicron processes!
0 0
1 1
ext
pd p p
g
C f
t t t
C
| |
| |
= + = + |
|
|
\
\
ext
g
C
f
C

Now we will express the delay
of a chain of inverters:
Assuming a negligible wire capacitance, for the j-th stage,
we get:
( ) , 1
1 1
g j j
C
f
t t t
+
| |
| |
= + = + |
|
And we can write the total delay as:
67 67
( ) , 1
, 0 0
,
1 1
g j j
pd j p p
g j
t t t
C
+
| |
= + = + |
|
|
\
\
( ) , 1
, 0
1 1
,
1
N N
g j
pd pd j p
j j
g j
C
t t t
C
+
= =
| |
= = + |
|
\

We have N-1 unknowns, so we will derive N-1 partial
derivatives:
We receive a set of constraints:
( ) , 1
0
1 ,
1
N
g j
pd p
j g j
C
t t
C
+
=
| |
= + |
|
\
,
0
pd
g j
t
C
( )
( ) ( )
, 1 , g j g j
C
C
C C C
+
= =
This means that:
Each inverter is sized up by the same factor, f.
Each inverter has the same effective fanout, f
j
=f.
Each inverter has the same delay, t
p0
(1+f/ ).
68 68
( )
( ) ( ) , , 1 , 1
, , 1
g j g j g j
g j g j
C C C
C C
+
= =
We can now find the effective fanout, f:
( ) , 1 ,2 ,3 ,4 ,
1 1 , ,1 ,2 ,3 , 1 , ,1
N N
g j g g g g N N load load
j
j j g j g g g g N g N g
C
C C C C
C C
f f
C C C C C C C
+
= =
= = = =

,1
/
N
N
load g
f C C F = =
,1
load
g
C
F
C
We defined the overall effective fanout, F, between the input
and load capacitance of the circuit. Using this parameter,
we can express the total delay:
69 69
0
1
N
pd p
F
t N t
| |
= +
|
|
\
Starting with a minimum sized inverter with C
g,min
, and
driving a given load, C
load
, we can see that:
With a small number of stages, we get a large delay due to the
effective fanout (f, F).
With a large number of stages, we get a large delay due to the
intrinsic delay (Nt
p0
)
0
1
N
pd p
F
t N t
| |
= +
|
|
\
To find the optimal number of stages, we will differentiate
and equate to zero.
70 70
0
pd
dt
dN
=
ln
0
N
N
F F
F
N
+ =
This equation only has an analytical solution for the case of
=0. In this esoteric case we get:
If we take the typical case of =1, we can numerically solve
ln
0
N
N
F F
F
N
+ =
0
ln
opt
N F
=
=
0
2.718
opt
f e
=
= =
If we take the typical case of =1, we can numerically solve
the equation and arrive at:
71 71
1
3.6
opt
f
=

3.6
1
log
opt
N F
=

POWER CONSUMPTION POWER CONSUMPTION
And now that we fully understand the static and dynamic operation
of the CMOS Inverter, its time to take a look at
72 72
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Dynamic Power Dynamic Power
Assuming an ideal step input, we can analyze
the energy consumed from the supply of the
equivalent circuit during a Low-to-High transition
is given by:
( )
2
0 0 0
DD
DD DD
V
out
V V DD DD load load DD out load DD
dV
E i t V dt V C dt C V dV C V
dt

= = = =

Now, looking at the energy stored in the load
capacitance, we get:
74 74
( )
0 0 0
DD DD
V V DD DD load load DD out load DD
dt

( )
2
0 0 0
2
DD
DD
V
out load DD
Charge V out load out load out out
dV C V
E i t V dt C V dt C V dV
dt

= = = =

Analyzing these results, we see that the energy required to
charge the output capacitance is twice the energy stored on
the capacitor at the end of the transition.
2
DD
V load DD
E C V =
2
2
load DD
Charge
C V
E =
This is relatively surprising and very important.
It means that half of the energy was wasted on the pMOS
resistance independent of its size!
75 75
Assuming the input changes now from zero to one, we now
get a High-to-Low transition.
Here, the supply is disconnected, and the charge stored on
the capacitance flows through the nMOS to the ground.
The energy dissipated is the total energy stored on the
output capacitance, as no charge is left:
output capacitance, as no charge is left:
The sum of the charge and discharge
energy is obviously equal to the energy
supplied:
76 76
( )
2
0
0 0
2
DD
out load DD
discharge DSn out load out load out out
V
dV C V
E i t V dt C V dt C V dV
dt

= = = =

2
DD
charge discharge V load DD
E E E C V + = =
Conclusions:
Each charge and discharge cycle dissipates a fixed amount of
energy, independent of the size of the device.
The effective energy is the charge stored on the capacitance. The
rest of the energy is wasted as heat burned on the pMOS (charge)
and nMOS (discharge) resistance.
To compute the Power Dissipation, we calculate the total
To compute the Power Dissipation, we calculate the total
energy wasted per one second.
For a circuit that completes a Low-to-High transition f
0 1
times per second (and therefore a
High-to-Low transition as well),
the dynamic power consumption is:
77 77
2
0 1 dyn load DD
P C V f
=
We said that the Power Dissipation is a factor of the
switching frequency of the gate.
But the gate only switches when its input changes. In other
words, the switching activity is smaller than the circuit
frequency.
We can rewrite the Dynamic Power expression using the
We can rewrite the Dynamic Power expression using the
activity factor, of the inverter, expressing the probability of
the output to switch:
C
eff
is the effective capacitance of a complex circuit,
describing the average capacitance that actually switches
each cycle.
78 78
2 2
dyn load DD eff DD
P C V f C V f = =
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Short Circuit Power Short Circuit Power
During the above analysis, the input was an ideal step
function, immediately closing one transistor when the other
was opened.
In a real circuit, the input signal has a non-zero rise/fall time,
resulting in a time interval with both the pMOS and nMOS
transistors open.
transistors open.
This provides a direct path from V
DD
to GND, with a current
known as Short Circuit current.
This is shown in the following
waveforms:
80 80
The energy dissipated via short circuit power is the area
under the triangles:
And the average power consumption is:
2 2
peak sc peak sc
sc DD DD sc DD peak
I t I t
E V V t V I = + =
sc sc DD peak
P t V I f =
The short circuit interval, t
sc
, is the margin between the
threshold voltages of the transistors.
Assuming a linear input transition:
( )
2
0.8
rise fall
DD TH
sc
DD
t
V V
t
V
=
0.8
DD
V
What affects the short circuit power?
A short input rise time with a large output
capacitance (large fall time) minimizes
short circuit power, as the peak current is
very small.
A small output capacitance relative to the input rise time causes
A small output capacitance relative to the input rise time causes
extensive short circuit power, as the peak
current is maximal (saturation current of
the transistors).
Conclusion:
Try to keep the input and output rise/fall
times similar to maximize performance
and minimize short circuit power.
83 83
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Static Power Static Power
Ideally, a MOSFET transistor is a perfect switch.
In such a case, a CMOS inverter never has a conducting
path in steady state, resulting
in no static power dissipation.
However, in reality, MOSFET
transistors never completely
turn off.
85 85
Static Power Static Power
Since static power is constantly consumed, the power
dissipation can be simply expressed as:
Sources of static power are beyond the scope of this
course, however they are quickly becoming the dominant
static static DD
P I V =
course, however they are quickly becoming the dominant
source of power in advanced sub-micron technologies.
For further probing, see these subjects:
Subthreshold current
Hot Electrons
DIBL
Punchthrough
86 86
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
Total Power Consumption Total Power Consumption
As we saw above, there are three components to the power
dissipation of a CMOS inverter:
Dynamic Power
Short Circuit Power
Static Power
Putting them all together, we get the total power
consumption of a CMOS logic gate:
88 88
2
total dyn sc static load DD DD peak sc DD static
P P P P fC V fV I t V I = + + = + +
Total Power Consumption Total Power Consumption
We previously learned that the power-delay-product (PDP)
measures the average energy of a switching event:
Since both Power and PDP give a clear advantage to
2 2
max
1
2
dyn pd load DD pd load DD
PDP P t C V f t C V = = =
Since both Power and PDP give a clear advantage to
energy reduction versus performance, we measure the
energy-delay-product (EDP) as a combined measurement of
the two:
89 89
2
1
2
pd load DD pd
EDP PDP t C V t = =
7.2.4 Noise Margins
7.5 Summary
7.4.1 Dynamic Power
7.4.3 Static Power
7.5 Summary
SUMMARY SUMMARY
Okay, enough with the inverter. But
before we go on, lets go over a short
91 91
Summary Summary
The CMOS inverter is characterized by:
A pMOS Pull-Up device and an nMOS pull down device.
The pMOS is usually wider due to inferior current driving.
An almost ideal VTC with a full rail to rail swing.
Noise margins of a balanced inverter are close to V
DD
/2
The steady state response is not affected by fanout.
Propagation delay:
0.69
eqp eqn
R R
t C
+ | |
=
Propagation delay:
Can be approximated as:
Small loads make faster drivers.
Widening the transistors improves the delay.
Power Dissipation:
Dominated by dynamic power, given by:
Short circuit power can be reduced by equating input/output slopes.
Static Power is a problem out of the scope of this course.
92 92
0.69
2
eqp eqn
pd load
R R
t C
+ | |
=
|
\
2
dyn load DD
P fC V =
CMOS Advantages CMOS Advantages
Rail to Rail Swing, resulting in high Noise Margins
and low leakage.
Ratioless design, i.e. logic levels are independent
of transistor sizing.
Low Output Impedance, due to a finite resistance
Low Output Impedance, due to a finite resistance
path between output and one of the supplies. This
leads to lower noise sensitivities.
High Input Impedance, meaning no theoretical Fan
Out limit (no input current).
Low Static Power, due to no direct path between
rails in steady state.
93 93

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Switching Threshold Switching Threshold

Propagation Delay Propagation Delay Method Method 3 3

Sizing a chain of inverters Sizing a chain of inverters

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