MSP430

MSP430G2302-EP
www.ti.com SLAS868 JUNE 2012
MIXED SIGNAL MICROCONTROLLER

1
FEATURES
Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Active Mode: 220 A at 1 MHz, 2.2 V Standby Mode: 0.5 A Off Mode (RAM Retention): 0.1 A Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 s 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations Internal Frequencies up to 16 MHz With Four Calibrated Frequencies Internal Very-Low-Power Low-Frequency (LF) Oscillator 32-kHz Crystal External Digital Clock Source One 16-Bit Timer_A With Three Capture/Compare Registers Up to 16 Touch-Sense Enabled I/O Pins Universal Serial Interface (USI) Supporting SPI and I2C Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse On-Chip Emulation Logic With Spy-Bi-Wire Interface Family Members are Summarized in Table 1 Package Options TSSOP: 14 Pin For Complete Module Descriptions, See the MSP430x2xx Family Users Guide (SLAU144)

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SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

(1)
Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Extended (40C/85C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability
Custom temperature ranges available
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s. The MSP430G2302 series of microcontrollers are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, and up to 16 I/O touch sense enabled pins and built-in communication capability using the universal serial communication interface. The MSP430G2302 series have a 10-bit A/D converter. For configuration details, see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430 is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright 2012, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
MSP430G2302-EP
SLAS868 JUNE 2012 www.ti.com
Table 1. Available Options (1)

Device MSP430G2302IPW1REP (1) EEM 1 Flash (kB) 4 RAM (B) 256 Timer_A 1x TA3 ADC10 Channel USI 1 CLOCK LF, DCO, VLO I/O 10 Package Type 14-TSSOP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
Table 2. ORDERING INFORMATION (1)

TA 40C to 85C (1) PACKAGE TSSOP - PW ORDERABLE PART NUMBER MSP430G2302IPW1EP MSP430G2302IPW1REP TOP-SIDE MARKING G2302EP VID NUMBER V62/12623-01XE
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com.
Submit Documentation Feedback
MSP430G2302-EP
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE PINOUTS
PW PACKAGE (TOP VIEW)
DVCC P1.0/TA0CLK/ACLK/A0 P1.1/TA0.0/A1 P1.2/TA0.1/A2 P1.3/ADC10CLK/A3/VREF-/VEREFP1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/TCK P1.5/TA0.0/SCLK/A5/TMS
1 2 3 4 5 6 7 14 13 12 11 10 9 8
DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/SDI/SDA/A7/TDO/TDI P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK
NOTE: The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = 1.
MSP430G2302-EP
FUNCTIONAL BLOCK DIAGRAMS

Functional Block Diagram, MSP430G2302
XIN XOUT DVCC DVSS P1.x 8 ACLK Clock System Flash SMCLK 8KB 4KB 2KB 1KB MAB 256B 256B 256B 128B RAM Port P1 8 I/O Interrupt capability pull-up/down resistors Port P2 up to 8 I/O Interrupt capability pull-up/down resistors P2.x up to 8
MCLK
16MHz CPU incl. 16 Registers
MDB
Emulation 2BP JTAG Interface Spy-Bi Wire RST/NMI Brownout Protection
USI Watchdog WDT+ 15-Bit Timer0_A3 3 CC Registers Universal Serial Interface SPI, I2C
NOTE: Port P2: Two pins are available on the 14-pin package option. Eight pins are available on the 20-pin package option.
MSP430G2302-EP
TERMINAL FUNCTIONS
Table 3. Terminal Functions
TERMINAL NAME P1.0/ TA0CLK/ ACLK/ A0 P1.1/ TA0.0/ A1 P1.2/ TA0.1/ A2 P1.3/ ADC10CLK/ A3/ VREF-/VEREF P1.4/ TA0.2/ SMCLK/ A4/ VREF+/VEREF+/ TCK P1.5/ TA0.0/ A5/ SCLK/ TMS P1.6/ TA0.1/ A6/ SDO/ SCL/ TDI/ TCLK P1.7/ A7/ SDI/ SDA/ TDO/TDI (1) XIN/ P2.6/ TA0.1 13 I/O 9 I/O General-purpose digital I/O pin ADC10 analog input A7 USI: Data input in SPI mode USI: I2C data in I2C mode JTAG test data output terminal or test data input during programming and test Input terminal of crystal oscillator General-purpose digital I/O pin Timer0_A, compare: Out1 output 8 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O NO. PW14 General-purpose digital I/O pin Timer0_A, clock signal TACLK input ACLK signal output ADC10 analog input A0 General-purpose digital I/O pin Timer0_A, capture: CCI0A input, compare: Out0 output ADC10 analog input A1 General-purpose digital I/O pin Timer0_A, capture: CCI1A input, compare: Out1 output ADC10 analog input A2 General-purpose digital I/O pin ADC10, conversion clock output ADC10 analog input A3 ADC10 negative reference voltage General-purpose digital I/O pin Timer0_A, capture: CCI2A input, compare: Out2 output SMCLK signal output ADC10 analog input A4 ADC10 positive reference voltage JTAG test clock, input terminal for device programming and test General-purpose digital I/O pin Timer0_A, compare: Out0 output ADC10 analog input A5 USI: clk input in I2C mode; clk in/output in SPI mode JTAG test mode select, input terminal for device programming and test General-purpose digital I/O pin Timer0_A, compare: Out1 output ADC10 analog input A6 USI: Data output in SPI mode USI: I2C clock in I2C mode JTAG test data input or test clock input during programming and test I/O DESCRIPTION
(1)
TDO or TDI is selected via JTAG instruction. Submit Documentation Feedback 5
MSP430G2302-EP
Table 3. Terminal Functions (continued)

TERMINAL NAME XOUT/ P2.7 RST/ NMI/ SBWTDIO/ TEST/ SBWTCK DVCC AVCC DVSS AVSS NC QFN Pad (2) 11 1 NA 14 NA I NA NA NA NA NA NA 10 I NO. PW14 12 I/O Output terminal of crystal oscillator (2) General-purpose digital I/O pin Reset Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test Supply voltage Supply voltage Ground reference Ground reference Not connected QFN package pad connection to VSS recommended. I/O DESCRIPTION
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset.
MSP430G2302-EP
SHORT-FORM DESCRIPTION CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 4 shows examples of the three types of instruction formats; Table 5 shows the address modes.
General-Purpose Register General-Purpose Register General-Purpose Register
Table 4. Instruction Word Formats

FORMAT Dual operands, source-destination Single operands, destination only Relative jump, un/conditional EXAMPLE ADD R4,R5 CALL R8 JNE OPERATION R4 + R5 R5 PC (TOS), R8 PC Jump-on-equal bit = 0
Table 5. Address Mode Descriptions (1)

ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate (1) S = source, D = destination S D SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 R11 M(2+R5) M(6+R6) M(EDE) M(TONI) M(MEM) M(TCDAT) M(R10) M(Tab+R6) M(R10) R11 R10 + 2 R10 #45 M(TONI)
MSP430G2302-EP
Operating Modes
The MSP430 devices have one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: Active mode (AM) All clocks are active Low-power mode 0 (LPM0) CPU is disabled ACLK and SMCLK remain active, MCLK is disabled Low-power mode 1 (LPM1) CPU is disabled ACLK and SMCLK remain active, MCLK is disabled DCO's dc generator is disabled if DCO not used in active mode Low-power mode 2 (LPM2) CPU is disabled MCLK and SMCLK are disabled DCO's dc generator remains enabled ACLK remains active Low-power mode 3 (LPM3) CPU is disabled MCLK and SMCLK are disabled DCO's dc generator is disabled ACLK remains active Low-power mode 4 (LPM4) CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO's dc generator is disabled Crystal oscillator is stopped
MSP430G2302-EP
Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the CPU goes into LPM4 immediately after power-up. Table 6. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE Power-Up External Reset Watchdog Timer+ Flash key violation PC out-of-range (1) NMI Oscillator fault Flash memory access violation INTERRUPT FLAG PORIFG RSTIFG WDTIFG KEYV (2) NMIIFG OFIFG ACCVIFG (2) (3) SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Reset
0FFFEh
31, highest
(non)-maskable (non)-maskable (non)-maskable
0FFFCh 0FFFAh 0FFF8h 0FFF6h
30 29 28 27 26 25 24 23 22 20 19 18 17 16 15 to 0, lowest
Watchdog Timer+ Timer0_A3 Timer0_A3
WDTIFG TACCR0 CCIFG

(4)
maskable maskable maskable
0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh
TACCR2 TACCR1 CCIFG. TAIFGTable 4 (4)
USI I/O Port P2 (up to eight flags) I/O Port P1 (up to eight flags)
USIIFG, USISTTIFG (2) (4) P2IFG.0 to P2IFG.7 (2) (4) P1IFG.0 to P1IFG.7
(2) (4)
maskable maskable maskable
0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h
See (1) (2) (3) (4) (5)
(5)
0FFDEh to 0FFC0h
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges. Multiple source flags (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Interrupt flags are located in the module. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary.
MSP430G2302-EP
Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.
Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is reset or set by POR. SFR bit is not present in device.
Table 7. Interrupt Enable Register 1 and 2

Address 00h 7 6 5 ACCVIE rw-0 WDTIE OFIE NMIIE ACCVIE Address 01h 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable 7 6 5 4 3 2 1 0
Table 8. Interrupt Flag Register 1 and 2

Address 02h 7 6 5 4 NMIIFG rw-0 WDTIFG OFIFG PORIFG RSTIFG NMIIFG Address 03h 3 RSTIFG rw-(0) 2 PORIFG rw-(1) 1 OFIFG rw-1 0 WDTIFG rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault. Power-On Reset interrupt flag. Set on VCC power-up. External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up. Set via RST/NMI pin 7 6 5 4 3 2 1 0
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MSP430G2302-EP
Memory Organization
Table 9. Memory Organization
MSP430G2302 Memory Main: interrupt vector Main: code memory Information memory RAM Peripherals Size Flash Flash Size Flash Size 16-bit 8-bit 8-bit SFR 4kB 0xFFFF to 0xFFC0 0xFFFF to 0xF000 256 Byte 010FFh to 01000h 256 B 0x02FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. Segments 0 to n may be erased in one step, or each segment may be individually erased. Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory. Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required.
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MSP430G2302-EP
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144). Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 s. The basic clock module provides the following clock signals: Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A. Calibration Data Stored in Information Memory Segment A Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure. Table 10. Tags Used by the ADC Calibration Tags
NAME TAG_DCO_30 TAG_ADC10_1 TAG_EMPTY ADDRESS 0x10F6 0x10DA VALUE 0x01 0x10 0xFE ADC10_1 calibration tag Identifier for empty memory areas DESCRIPTION DCO frequency calibration at VCC = 3 V and TA = 30C at calibration
Table 11. Labels Used by the ADC Calibration Tags

LABEL CAL_ADC_25T85 CAL_ADC_25T30 CAL_ADC_25VREF_FACTOR CAL_ADC_15T85 CAL_ADC_15T30 CAL_ADC_15VREF_FACTOR CAL_ADC_OFFSET CAL_ADC_GAIN_FACTOR CAL_BC1_1MHz CAL_DCO_1MHz CAL_BC1_8MHz CAL_DCO_8MHz CAL_BC1_12MHz CAL_DCO_12MHz CAL_BC1_16MHz CAL_DCO_16MHz CONDITION AT CALIBRATION / DESCRIPTION INCHx = 0x1010, REF2_5 = 1, TA = 85C INCHx = 0x1010, REF2_5 = 1, TA = 30C REF2_5 = 1, TA = 30C, I(VREF+) = 1 mA INCHx = 0x1010, REF2_5 = 0, TA = 85C INCHx = 0x1010, REF2_5 = 0, TA = 30C REF2_5 = 0, TA = 30C, I(VREF+) = 0.5 mA External VREF = 1.5 V, f(ADC10CLK) = 5 MHz External VREF = 1.5 V, f(ADC10CLK) = 5 MHz SIZE word word word word word word word word byte byte byte byte byte byte byte byte ADDRESS OFFSET 0x0010 0x000E 0x000C 0x000A 0x0008 0x0006 0x0004 0x0002 0x0009 0x00008 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002
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MSP430G2302-EP
Main DCO Characteristics All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage = 32 fDCO(RSEL,DCO) fDCO(RSEL,DCO+1) MOD fDCO(RSEL,DCO) + (32 MOD) fDCO(RSEL,DCO+1)
Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. Digital I/O There are two 8-bit I/O ports implemented: All individual I/O bits are independently programmable. Any combination of input, output, and interrupt condition(port P1 and port P2 only) is possible. Edge-selectable interrupt input capability for all the eight bits of port P1 and port P2, if available. Read/write access to port-control registers is supported by all instructions. Each I/O has an individually programmable pullup/pulldown resistor. Each I/O has an individually programmable pin-oscillator enable bit to enable low-cost touch sensing. WDT+ Watchdog Timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.
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MSP430G2302-EP
Timer0_A3 Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 12. Timer0_A3 Signal Connections (1)
INPUT PIN NUMBER PW14 P1.0-2 DEVICE INPUT SIGNAL TACLK ACLK SMCLK PinOsc P1.1-3 TA0.0 ACLK VSS VCC P1.2-4 TA0.1 CAOUT VSS VCC P1.4-6 PinOsc TA0.2 TA0.2 VSS VCC (1) Only one pin-oscillator must be enabled at a time. MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 P1.4-6 CCR1 TA1 P1.2-4 P1.6-8 P2.6-13 CCR0 TA0 P1.1-3 P1.5-7 Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER PW14
USI The universal serial interface (USI) module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C.
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MSP430G2302-EP
Peripheral File Map Table 13. Peripherals With Word Access

MODULE Timer0_A3 REGISTER DESCRIPTION Capture/compare register Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Flash Memory Flash control 3 Flash control 2 Flash control 1 Watchdog Timer+ Watchdog/timer control REGISTER NAME TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV FCTL3 FCTL2 FCTL1 WDTCTL OFFSET 0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh 012Ch 012Ah 0128h 0120h
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MSP430G2302-EP
Table 14. Peripherals With Byte Access

MODULE USI USI control 0 USI control 1 USI clock control USI bit counter USI shift register Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control Port P2 Port P2 selection 2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 Port P1 selection 2 Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 REGISTER DESCRIPTION REGISTER NAME USICTL0 USICTL1 USICKCTL USICNT USISR BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL P2SEL2 P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1SEL2 P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN IFG2 IFG1 IE2 IE1 OFFSET 078h 079h 07Ah 07Bh 07Ch 053h 058h 057h 056h 042h 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 041h 027h 026h 025h 024h 023h 022h 021h 020h 003h 002h 001h 000h
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MSP430G2302-EP
Absolute Maximum Ratings (1)

Voltage applied at VCC to VSS Voltage applied to any pin (2) Diode current at any device pin Storage temperature range, Tstg (3) (1) (2) (3) Unprogrammed device Programmed device 0.3 V to 4.1 V 0.3 V to VCC + 0.3 V 2 mA 55C to 150C 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Information
MSP430G2302 THERMAL METRIC JA JCtop JB JT JB JCbot Junction-to-ambient thermal resistance (1) Junction-to-case (top) thermal resistance Junction-to-board thermal resistance (3) Junction-to-top characterization parameter (4) Junction-to-board characterization parameter (5) Junction-to-case (bottom) thermal resistance (6)
(2)
PW 14 PINS 98.7 26.8 41.2 1.1 40.5 N/A
UNITS
C/W
(1) (2) (3) (4) (5) (6)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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MSP430G2302-EP
Recommended Operating Conditions

MIN VCC VSS TA Supply voltage Supply voltage Operating free-air temperature VCC = 1.8 V, Duty cycle = 50% 10% fSYSTEM Processor frequency (maximum MCLK frequency using the USART module) (1) (2) VCC = 2.7 V, Duty cycle = 50% 10% VCC = 3.3 V, Duty cycle = 50% 10% (1) (2) -40 dc dc dc During program execution During flash programming/erase 1.8 2.2 0 85 6 12 16 MHz NOM MAX 3.6 3.6 UNIT V V C
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend : 16 MHz
System Frequency - MHz
Supply voltage range , during flash memory programming 12 MHz Supply voltage range , during program execution 6 MHz
1.8 V
2.7 V 2.2 V Supply Voltage - V
3.3 V 3.6 V
Note:
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Safe Operating Area
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MSP430G2302-EP
Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER TEST CONDITIONS fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 VCC 2.2 V MIN TYP 220 A MAX UNIT
IAM,1MHz
Active mode (AM) current (1 MHz)
3V
320
400
(1) (2)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics Active Mode Supply Current (Into VCC)

5.0 4.0
4.0 Active Mode Current mA
f DCO = 16 MHz Active Mode Current mA 3.0
TA = 85 C TA = 25 C
3.0 f DCO = 12 MHz 2.0
2.0
VCC = 3 V TA = 85 C TA = 25 C
1.0
f DCO = 8 MHz f DCO = 1 MHz
1.0 VCC = 2.2 V 0.0 0.0
0.0 1.5
2.0
2.5
3.0
3.5
4.0
4.0
8.0
12.0
16.0
VCC Supply Voltage V
f DCO DCO Frequency MHz
Figure 2. Active Mode Current vs VCC, TA = 25C
Figure 3. Active Mode Current vs DCO Frequency
19
MSP430G2302-EP
Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 TA VCC MIN
(2)
TYP
MAX
UNIT
ILPM0,1MHz
Low-power mode 0 (LPM0) current (3)
25C
2.2 V
55
ILPM2
25C
2.2 V
22
ILPM3,LFXT1
25C
2.2 V
0.7
1.0
ILPM3,VLO
Low-power mode 3 current, (LPM3) (4)
25C 25C 85C
2.2 V 2.2 V 2.2 V
0.5 0.1 0.8
0.7 0.5 1.5
A A A
ILPM4
(1) (2) (3) (4) (5)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.0
ILPM4 Lowpower mode current A 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 40.0 20.0 0.0
VCC = 1.8 V
1.8 ILPM3 Lowpower mode current A 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 40.0 20.0 0.0 VCC = 1.8 V VCC = 3.6 V VCC = 3 V VCC = 2.2 V
VCC = 3.6 V VCC = 3 V VCC = 2.2 V
20.0 40.0 60.0 80.0 100.0 120.0 TA Temperature C
20.0 40.0 60.0 80.0 100.0 120.0
TA Temperature C
Figure 4. LPM3 Current vs Temperature
Figure 5. LPM4 Current vs Temperature
20
MSP430G2302-EP
Schmitt-Trigger Inputs Ports Px (1)

PARAMETER VIT+ VIT Vhys RPull CI (1) Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ VIT) Pullup/pulldown resistor Input capacitance For pullup: VIN = VSS For pulldown: VIN = VCC VIN = VSS or VCC TEST CONDITIONS VCC 3V 3V 3V 3V MIN 0.45 VCC 1.35 0.25 VCC 0.75 0.3 20 35 5 TYP MAX 0.75 VCC 2.25 0.55 VCC 1.65 1 50 UNIT V V V k pF
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals shorter than t(int).
Leakage Current Ports Px

PARAMETER Ilkg(Px.x) (1) (2) High-impedance leakage current See TEST CONDITIONS
(1)
VCC 3V
MIN
MAX 50
UNIT nA
and
(2)
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input, and the pullup/pulldown resistor is disabled.
Outputs Ports Px
PARAMETER VOH VOL (1) High-level output voltage Low-level output voltage TEST CONDITIONS I(OHmax) = 6 mA
(1)
VCC 3V 3V
MIN
TYP VCC 0.3 VSS + 0.3
MAX
UNIT V V
I(OLmax) = 6 mA (1)
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed 48 mA to hold the maximum voltage drop specified.
Output Frequency Ports Px

PARAMETER fPx.y fPort_CLK (1) (2) Port output frequency (with load) Clock output frequency TEST CONDITIONS Px.y, CL = 20 pF, RL = 1 k (1) Px.y, CL = 20 pF
(2) (2)
VCC 3V 3V
MIN
TYP 12 16
MAX
UNIT MHz MHz
A resistive divider with two 0.5-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
21
MSP430G2302-EP
Typical Characteristics Outputs

TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE
30.0 I OL Typical Low-Level Output Current mA I OL Typical Low-Level Output Current mA VCC = 2.2 V P1.7 25.0 TA = 85C TA = 25C 50.0 VCC = 3 V P1.7 40.0 TA = 85C 30.0 TA = 25C
TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE
20.0
15.0
20.0
10.0
5.0
10.0
0.0 0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL Low-Level Output Voltage V
Figure 6.
Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE

0.0 I OH Typical High-Level Output Current mA I OH Typical High-Level Output Current mA VCC = 2.2 V P1.7 5.0 0.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE

VCC = 3 V P1.7 10.0
10.0
20.0
15.0 TA = 85C 20.0
30.0 TA = 85C 40.0 TA = 25C 50.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
25.0 0.0
TA = 25C 0.5 1.0 1.5 2.0 2.5 VOH High-Level Output Voltage V
VOH High-Level Output Voltage V
Figure 8.
Figure 9.
22
MSP430G2302-EP
Pin-Oscillator Frequency Ports Px

PARAMETER foP1.x foP2.x foP2.6/7 (1) (2) Port output oscillation frequency Port output oscillation frequency Port output oscillation frequency TEST CONDITIONS P1.y, CL = 10 pF, RL = 100 k
(1) (2)
VCC 3V 3V 3V
MIN
TYP 1400 900 1800 1000 700
MAX
UNIT kHz kHz kHz
P1.y, CL = 20 pF, RL = 100 k (1) (2) P2.0 to P2.5, CL = 10 pF, RL = 100 k (1) (2) P2.0 to P2.5, CL = 20 pF, RL = 100 k (1) (2) P2.6 and P2.7, CL = 20 pF, RL = 100 k (1) (2)
A resistive divider with two 100-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage oscillates with a typical amplitude of 700 mV at the specified toggle frequency.
Typical Characteristics Pin-Oscillator Frequency

TYPICAL OSCILLATING FREQUENCY vs LOAD CAPACITANCE
1.50 fosc Typical Oscillation Frequency MHz 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0.30 0.15 0.00 10 50 100 CLOAD External Capacitance pF P1.y P2.0 ... P2.5 P2.6, P2.7 fosc Typical Oscillation Frequency MHz VCC = 2.2 V 1.50 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0.30 0.15 0.00 10 50 100 CLOAD External Capacitance pF P1.y P2.0 ... P2.5 P2.6, P2.7 VCC = 3.0 V
TYPICAL OSCILLATING FREQUENCY vs LOAD CAPACITANCE
Figure 10.
Figure 11.
23
MSP430G2302-EP
POR/Brownout Reset (BOR) (1)

PARAMETER VCC(start) V(B_IT) Vhys(B_IT) td(BOR) t(reset) (1) See Figure 12 See Figure 12 through Figure 14 See Figure 12 See Figure 12 Pulse length needed at RST/NMI pin to accepted reset internally 2.2 V 2 TEST CONDITIONS dVCC/dt 3 V/s dVCC/dt 3 V/s dVCC/dt 3 V/s VCC MIN TYP 1.40 140 2000 MAX UNIT V V mV s s 0.7 V(B_IT)
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT) + Vhys(B_IT)is 1.8 V.
VCC Vhys(B_IT) V(B_IT) VCC(start)
0 t d(BOR)
Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage
24
MSP430G2302-EP
Typical Characteristics POR/Brownout Reset (BOR)

2 VCC = 3 V Typical Conditions VCC(drop) V 1.5 1 0.5 0 0.001 VCC(drop) VCC 3V t pw
1 t pw Pulse Width s
1000 1 ns 1 ns t pw Pulse Width s
Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC 2 VCC = 3 V VCC(drop) V 1.5 1 VCC(drop) 0.5 0 0.001 t f = tr 1 t pw Pulse Width s 1000 tf tr Typical Conditions 3V t pw
t pw Pulse Width s
Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
25
MSP430G2302-EP
DCO Frequency
PARAMETER RSELx < 14 VCC fDCO(0,0) fDCO(0,3) fDCO(1,3) fDCO(2,3) fDCO(3,3) fDCO(4,3) fDCO(5,3) fDCO(6,3) fDCO(7,3) fDCO(8,3) fDCO(9,3) fDCO(10,3) fDCO(11,3) fDCO(12,3) fDCO(13,3) fDCO(14,3) fDCO(15,3) fDCO(15,7) SRSEL SDCO Duty cycle Supply voltage DCO frequency (0, 0) DCO frequency (0, 3) DCO frequency (1, 3) DCO frequency (2, 3) DCO frequency (3, 3) DCO frequency (4, 3) DCO frequency (5, 3) DCO frequency (6, 3) DCO frequency (7, 3) DCO frequency (8, 3) DCO frequency (9, 3) DCO frequency (10, 3) DCO frequency (11, 3) DCO frequency (12, 3) DCO frequency (13, 3) DCO frequency (14, 3) DCO frequency (15, 3) DCO frequency (15, 7) Frequency step between range RSEL and RSEL+1 Frequency step between tap DCO and DCO+1 RSELx = 14 RSELx = 15 RSELx = 0, DCOx = 0, MODx = 0 RSELx = 0, DCOx = 3, MODx = 0 RSELx = 1, DCOx = 3, MODx = 0 RSELx = 2, DCOx = 3, MODx = 0 RSELx = 3, DCOx = 3, MODx = 0 RSELx = 4, DCOx = 3, MODx = 0 RSELx = 5, DCOx = 3, MODx = 0 RSELx = 6, DCOx = 3, MODx = 0 RSELx = 7, DCOx = 3, MODx = 0 RSELx = 8, DCOx = 3, MODx = 0 RSELx = 9, DCOx = 3, MODx = 0 RSELx = 10, DCOx = 3, MODx = 0 RSELx = 11, DCOx = 3, MODx = 0 RSELx = 12, DCOx = 3, MODx = 0 RSELx = 13, DCOx = 3, MODx = 0 RSELx = 14, DCOx = 3, MODx = 0 RSELx = 15, DCOx = 3, MODx = 0 RSELx = 15, DCOx = 7, MODx = 0 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) Measured at SMCLK output 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 4.30 6.00 8.60 12.0 16.0 1.35 1.08 50 0.54 0.80 1.6 2.3 3.4 4.25 7.30 9.60 13.9 18.5 26.0 TEST CONDITIONS VCC MIN 1.8 2.2 3 0.06 0.07 0.15 0.21 0.30 0.41 0.58 1.06 1.50 TYP MAX 3.6 3.6 3.6 0.14 0.17 UNIT V V V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ratio ratio %
26
MSP430G2302-EP
Calibrated DCO Frequencies Tolerance

PARAMETER 1-MHz tolerance over temperature (1) 1-MHz tolerance over VCC TEST CONDITIONS BCSCTL1= CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V BCSCTL1= CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V TA 0C to 85C VCC 3V MIN -3 TYP 0.5 MAX +3 UNIT %
30C
1.8 V to 3.6 V
-3
+3
1-MHz tolerance overall 8-MHz tolerance over temperature (1) 8-MHz tolerance over VCC
-40C to 85C
1.8 V to 3.6 V
-6
+6
0C to 85C
3V
-3
0.5
+3
30C
2.2 V to 3.6 V
-3
+3
-40C to 85C
2.2 V to 3.6 V
-6
+6
0C to 85C
3V
-3
0.5
+3
30C
2.7 V to 3.6 V
-3
+3
-40C to 85C
2.7 V to 3.6 V
-6
+6
0C to 85C
3.3 V
-3
0.5
+3
30C
3.3 V to 3.6 V
-3
+3
16-MHz tolerance overall (1)
-40C to 85C
3.3 V to 3.6 V
-6
+6
This is the frequency change from the measured frequency at 30C over temperature.
27
MSP430G2302-EP
Wake-Up From Lower-Power Modes (LPM3/4)

PARAMETER tDCO,LPM3/4 tCPU,LPM3/4 (1) (2) DCO clock wake-up time from LPM3/4 (1) CPU wake-up time from LPM3/4 (2) TEST CONDITIONS BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ VCC 3V MIN TYP 1.5 1/fMCLK + tClock,LPM3/4 MAX UNIT s
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics DCO Clock Wake-Up Time From LPM3/4
10.00 DCO Wake Time us
RSELx = 0...11 1.00 RSELx = 12...15
0.10 0.10
1.00 DCO Frequency MHz
10.00
Figure 15. DCO Wake-Up Time From LPM3 vs DCO Frequency
28
MSP430G2302-EP
Crystal Oscillator, XT1, Low-Frequency Mode (1)

PARAMETER fLFXT1,LF fLFXT1,LF,logic LFXT1 oscillator crystal frequency, LF mode 0, 1 TEST CONDITIONS XTS = 0, LFXT1Sx = 0 or 1 VCC 1.8 V to 3.6 V 1.8 V to 3.6 V 10000 MIN TYP 32768 32768 500 k 200 1 5.5 8.5 11 2.2 V 2.2 V 30 10 50 70 10000 % Hz pF 50000 MAX UNIT Hz Hz
LFXT1 oscillator logic level square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 LF mode Oscillation allowance for LF crystals XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 6 pF XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 12 pF XTS = 0, XCAPx = 0 XTS = 0, XCAPx = 1 XTS = 0, XCAPx = 2 XTS = 0, XCAPx = 3 XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
OALF
CL,eff
Integrated effective load capacitance, LF mode (2)
Duty cycle fFault,LF (1)
LF mode Oscillator fault frequency, LF mode (3)
(2)
(3) (4)
To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)

PARAMETER fVLO dfVLO/dT dfVLO/dVCC (1) VLO frequency (1) VLO frequency temperature drift VLO frequency supply voltage drift TA -40C to 85C -40C to 85C 25C VCC 3V 3V 1.8 V to 3.6 V MIN 4 TYP 12 0.5 4 MAX 20 UNIT kHz %/C %/V
Ensured by design on specified temperature.
Timer_A
PARAMETER fTA tTA,cap Timer_A input clock frequency Timer_A capture timing TEST CONDITIONS SMCLK Duty cycle = 50% 10% TA0, TA1 3V 20 VCC MIN TYP fSYSTEM MAX UNIT MHz ns
29
MSP430G2302-EP
USI, Universal Serial Interface

PARAMETER fUSI f(SCLK) VOL,I2C USI module clock frequency Serial clock frequency, slave mode Low-level output voltage on SDA and SCL TEST CONDITIONS External: SCLK, Duty cycle = 50% 10% SPI slave mode USI module in I2C mode, I(OLmax) = 1.5 mA 3V 3V VSS VCC MIN TYP fSYSTEM 6 VSS + 0.4 MAX UNIT MHz MHz V
Typical Characteristics USI Low-Level Output Voltage on SDA and SCL

5.0 VCC = 2.2 V I OL Low-Level Output Current mA 4.0 TA = 25C 3.0 TA = 85C 2.0
I OL Low-Level Output Current mA 4.0 5.0 VCC = 3 V TA = 25C
TA = 85C 3.0
2.0
1.0
1.0
0.0 0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.0
0.2
0.4
0.6
0.8
1.0
Figure 16. USI Low-Level Output Voltage vs Output Current
Figure 17. USI Low-Level Output Voltage vs Output Current
Flash Memory
PARAMETER VCC(PGM/ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock,
0
TEST CONDITIONS
VCC
MIN 2.2 257
TYP
MAX 3.6 476
UNIT V kHz mA mA ms ms cycles years tFTG tFTG tFTG tFTG
Program and erase supply voltage Flash timing generator frequency Supply current from VCC during program Supply current from VCC during erase Cumulative program time
(1)
2.2 V, 3.6 V 2.2 V, 3.6 V 2.2 V, 3.6 V 2.2 V, 3.6 V TJ = 25C See See See See
(2) (2) (2) (2)
1 1 20 104 100 30 25 18 6 105
5 7 10
Cumulative mass erase time Program and erase endurance Data retention duration Word or byte program time Block program time for first byte or word Block program time for each additional byte or word Block program end-sequence wait time
tBlock, 1-63 tBlock, (1) (2) 30

End
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word or byte write mode and block write mode. These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG). Submit Documentation Feedback
MSP430G2302-EP
Flash Memory (continued)

PARAMETER tMass Erase tSeg Erase Mass erase time Segment erase time TEST CONDITIONS See See
(2) (2)
VCC
MIN
TYP 10593 4819
MAX
UNIT tFTG tFTG
31
MSP430G2302-EP
RAM
PARAMETER V(RAMh) (1) RAM retention supply voltage
(1)
TEST CONDITIONS CPU halted
MIN 1.6
MAX
UNIT V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface

PARAMETER fSBW tSBW,Low tSBW,En tSBW,Ret fTCK RInternal (1) (2) Spy-Bi-Wire input frequency Spy-Bi-Wire low clock pulse length Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) Spy-Bi-Wire return to normal operation time TCK input frequency (2) Internal pulldown resistance on TEST TEST CONDITIONS VCC 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 15 0 25 60 MIN 0 0.025 TYP MAX 20 15 1 100 5 90 UNIT MHz s s s MHz k
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)

PARAMETER VCC(FB) VFB IFB tFB (1) Supply voltage during fuse-blow condition Voltage level on TEST for fuse blow Supply current into TEST during fuse blow Time to blow fuse TEST CONDITIONS TA = 25C MIN 2.5 6 7 100 1 MAX UNIT V V mA ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode.
32
MSP430G2302-EP
PIN SCHEMATICS Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
To ADC10 * INCHx = y *
ADC10AE0.y * PxSEL2.y PxSEL.y
PxDIR.y 0
0 1 2 3 Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC 0 1 2 0 TAx.y TAxCLK PxIN.y 3 Bus Keeper EN P1.0/TA0CLK/ACLK/A0* P1.1/TA0.0/A1* P1.2/TA0.1/A2* 0 1 1
PxSEL2.y PxSEL.y
PxOUT.y From Module
EN
To Module
D
PxIE.y
PxIRQ.y Q PxIFG.y PxSEL.y PxIES.y
EN Set
Interrupt Edge Select
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
33
MSP430G2302-EP
Table 15. Port P1 (P1.0 to P1.2) Pin Functions

PIN NAME (P1.x) P1.0/ TA0CLK/ ACLK/ Pin Osc P1.1/ TA0.0/ 1 0 x P1.x (I/O) TA0.TACLK ACLK Capacitive sensing P1.x (I/O) TA0.0 TA0.CCI0A Pin Osc P1.2/ TA0.1/ 2 Capacitive sensing P1.x (I/O) TA0.1 TA0.CCI1A Pin Osc Capacitive sensing FUNCTION CONTROL BITS / SIGNALS (1) P1DIR.x I: 0; O: 1 0 1 x I: 0; O: 1 1 0 X I: 0; O: 1 1 0 X P1SEL.x 0 1 1 0 0 1 1 0 0 1 1 0 P1SEL2.x 0 0 0 1 0 0 0 1 0 0 0 1
(1)
X = don't care
34
MSP430G2302-EP
Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger

SREF2 * To ADC10 VREF- * 0 1 VSS
ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0,2,3 1 Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC 0 1 2 3

Bus Keeper EN
PxSEL2.y PxSEL.y
0 1
PxOUT.y From ADC10 *
P1.3/ADC10CLK*/A3*/ VREF-*/VEREF-*
TAx.y TAxCLK PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN Q Set PxIFG.y Interrupt Edge Select
PxSEL.y PxIES.y
35
MSP430G2302-EP
Table 16. Port P1 (P1.3) Pin Functions

PIN NAME (P1.x) P1.3/ ADC10CLK/ A3/ VREF-/ VEREF-/ Pin Osc 3 CONTROL BITS / SIGNALS (1) x P1.x (I/O) ADC10CLK A3 VREFVEREFCapacitive sensing FUNCTION P1DIR.x I: 0; O: 1 1 X X X X P1SEL.x 0 1 X X X 0 P1SEL2.x 0 0 X X X 1 ADC10AE.x (INCH.x=1) 0 0 1 (y = 3) 1 1 0
(1)
X = don't care
36
MSP430G2302-EP

From/To ADC10 Ref+ * To ADC10 * INCHx = y * ADC10AE0.y * PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC 0 1 2 3 Bus Keeper EN P1.4/SMCLK/TA0.2/A4*/ VREF+*/VEREF+*/TCK 0 1 1
PxSEL2.y PxSEL.y PxOUT.y SMCLK from Timer TAx.y TAxCLK PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y PxIFG.y PxSEL.y PxIES.y From JTAG To JTAG
EN Q Set Interrupt Edge Select
37
MSP430G2302-EP

CONTROL BITS / SIGNALS (1) PIN NAME (P1.x) P1.4/ SMCLK/ TA0.2/ x FUNCTION P1.x (I/O) SMCLK TA0.2 TA0.CCI2A VREF+/ VEREF+/ A4/ TCK/ Pin Osc 4 VREF+ VEREF+ A4 TCK Capacitive sensing P1DIR.x I: 0; O: 1 1 1 0 X X X X X P1SEL.x 0 1 1 1 X X X X 0 P1SEL2.x 0 0 1 1 X X X X 1 ADC10AE.x (INCH.x=1) 0 0 0 0 1 1 1 (y = 4) 0 0 JTAG Mode 0 0 0 0 0 0 0 1 0
(1)
X = don't care
38
MSP430G2302-EP
Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger

ADC10AE0.y *
PxSEL2.y PxSEL.y PxDIR.y From Module
0 1 2 3 Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC 0 1 2 0 TAx.y TAxCLK PxIN.y 3 Bus Keeper EN P1.5/TA0.0/SCLK/A5*/TMS P1.6/TA0.1/SDO/SCL/A6*/TDI/TCLK P1.7//SDI/SDA/A7*/TDO/TDI 0 1 1
PxSEL2.y PxSEL.y PxOUT.y From Module
EN
To Module
D
PxIE.y
PxIRQ.y PxIFG.y PxSEL.y PxIES.y From JTAG To JTAG
EN Set
39
MSP430G2302-EP

PIN NAME (P1.x) P1.5/ TA0.0/ SCLK/ A5/ TMS/ Pin Osc P1.6/ TA0.1/ SDO/ SCL/ A6/ TDI/TCLK/ Pin Osc P1.7/ SDI/ SDA/ A7/ TDO/TDI/ Pin Osc 7 6 5 CONTROL BITS / SIGNALS (1) x FUNCTION P1.x (I/O) TA0.0 SPI mode A5 TMS Capacitive sensing P1.x (I/O) TA0.1 SPI mode I2C mode A6 TDI/TCLK Capacitive sensing P1.x (I/O) SPI mode SPI mode A7 TDO/TDI Capacitive sensing P1DIR.x I: 0; O: 1 1 from USI X X X I: 0; O: 1 1 from USI from USI X X X I: 0; O: 1 from USI from USI X X X P1SEL.x 0 1 1 X X 0 0 1 1 1 X X 0 0 1 1 X X 0 P1SEL2.x 0 0 0 X X 1 0 0 0 0 X X 1 0 0 0 X X 1 USIP.x 0 0 1 0 0 0 0 0 ! ! 0 0 0 0 1 1 0 0 0 JTAG Mode 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 ADC10AE.x (INCH.x=1) 0 0 0 1 (y = 5) 0 0 0 0 0 0 1 (y = 6) 0 0 0 0 0 1 (y = 7) 0 0
(1)
X = don't care
40
MSP430G2302-EP
Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger

PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 PxSEL2.y PxSEL.y 1 DVSS DVCC PxOUT.y 0 0 1 2 0 TAx.y TAxCLK 3 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 0 1 1
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y Q
EN Set PxIFG.y
PxSEL.y PxIES.y
41
MSP430G2302-EP

PIN NAME (P2.x) P2.0/ Pin Osc P2.1/ Pin Osc P2.2/ Pin Osc P2.3/ Pin Osc P2.4/ Pin Osc P2.5/ Pin Osc x P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing FUNCTION CONTROL BITS / SIGNALS (1) P2DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P2SEL.x 0 0 0 0 0 0 0 0 0 0 0 0 P2SEL2.x 0 1 0 1 0 1 0 1 0 1 0 1
(1)
X = don't care
42
MSP430G2302-EP
LF off PxSEL.6 & PxSEL.7 BCSCTL3.LFXT1Sx = 11
XOUT/P2.7
LFXT1CLK PxSEL.y PxDIR.y 0 1
0 1
Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC 0 1 2 0 TAx.y TAxCLK 3 XIN/P2.6/TA0.1 0 1 1
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y PxIFG.y PxSEL.y PxIES.y
EN Set

PIN NAME (P2.x) XIN/ P2.6/ 6 TA0.1/ Pin Osc Timer0_A3.TA1 Capacitive sensing 1 X CONTROL BITS / SIGNALS (1) x FUNCTION P2DIR.x 0 I: 0; O: 1 P2SEL.6 P2SEL.7 1 1 0 X 1 0 0 X P2SEL2.6 P2SEL2.7 0 0 0 0 0 0 1 X
XIN P2.x (I/O)
(1)
X = don't care Submit Documentation Feedback 43
MSP430G2302-EP
LF off PxSEL.6 & PxSEL.7 BCSCTL3.LFXT1Sx = 11
XIN/P2.6/TA0.1
LFXT1CLK PxSEL.y PxDIR.y 0 1
0 1
from P2.6
Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC 0 1 2 3 TAx.y TAxCLK XOUT/P2.7 0 1 1
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y Q PxIFG.y PxSEL.y PxIES.y
EN Set

PIN NAME (P2.x) XOUT/ P2.7/ Pin Osc 7 CONTROL BITS / SIGNALS (1) x FUNCTION P2DIR.x X I: 0; O: 1 X P2SEL.6 P2SEL.7 1 1 X 0 X 0 P2SEL2.6 P2SEL2.7 0 0 0 0 X 1
XOUT P2.x (I/O) Capacitive sensing
(1) 44
X = don't care Submit Documentation Feedback

PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2012
PACKAGING INFORMATION
Orderable Device MSP430G2302IPW1EP MSP430G2302IPW1REP
(1)
Status
(1)
Package Type Package Drawing TSSOP TSSOP PW PW
Pins 14 14
Package Qty 90 2000
Eco Plan TBD TBD
(2)
Lead/ Ball Finish Call TI Call TI
MSL Peak Temp Call TI Call TI
(3)
Samples (Requires Login)
ACTIVE ACTIVE
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF MSP430G2302-EP :
Catalog: MSP430G2302
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2012
Catalog - TI's standard catalog product
Addendum-Page 2
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitute TIs approval, warranty or endorsement thereof.

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MSP430G2302-EP

www.ti.com SLAS868 JUNE 2012

MIXED SIGNAL MICROCONTROLLER

SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

Table 1. Available Options (1)

Table 2. ORDERING INFORMATION (1)

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DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/SDI/SDA/A7/TDO/TDI P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK

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FUNCTIONAL BLOCK DIAGRAMS

16MHz CPU incl. 16 Registers

Emulation 2BP JTAG Interface Spy-Bi Wire RST/NMI Brownout Protection

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TDO or TDI is selected via JTAG instruction. Submit Documentation Feedback 5

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Table 3. Terminal Functions (continued)

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SHORT-FORM DESCRIPTION CPU

General-Purpose Register General-Purpose Register General-Purpose Register

Table 4. Instruction Word Formats

Table 5. Address Mode Descriptions (1)

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Interrupt Vector Addresses

(non)-maskable (non)-maskable (non)-maskable

0FFFCh 0FFFAh 0FFF8h 0FFF6h

Watchdog Timer+ Timer0_A3 Timer0_A3

WDTIFG TACCR0 CCIFG

maskable maskable maskable

0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh

TACCR2 TACCR1 CCIFG. TAIFGTable 4 (4)

maskable maskable maskable

0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h

See (1) (2) (3) (4) (5)

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Special Function Registers (SFRs)

Table 7. Interrupt Enable Register 1 and 2

Table 8. Interrupt Flag Register 1 and 2

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Table 11. Labels Used by the ADC Calibration Tags

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Peripheral File Map Table 13. Peripherals With Word Access

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Table 14. Peripherals With Byte Access

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Absolute Maximum Ratings (1)

PW 14 PINS 98.7 26.8 41.2 1.1 40.5 N/A