Code No: 07A80406

R07

Set No. 2

IV B.Tech II Semester Examinations,APRIL 2011 DSP PROCESSORS AND ARCHITECTURES Common to Bio-Medical Engineering, Electronics And Telematics, Electronics And Instrumentation Engineering, Electronics And Communication Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain the sampling process in DSP. For a signal sampled at 2KHz, 8 KHz and 10 KHz, what is the sampling frequency. [16] 2. Explain about the DSP Data addressing capabilities, with an example for each. [16] 3. What is hardware looping? Explain in detail the types of hardware looping. [16]

4. Compute the DFT for the sequence {1, 2, 0, 0, 0, 2, 1, 1} using radix -2 DIF FFT and radix -2 DIT- FFT algorithm. [16] 5. Explain the CPU architecture of TMS320C54XX. What is SXM, OVM,OVA/OVB with neat diagrams. [16] 6. Show that the dynamic range of a signal increases by 6dB for each additional bit used to represent its value. [16] 7. Implement the IIR lter represented by the following dierence equation on TMS320C54XX. Assume that Q15 notation is used to represent the values of coecients and Q0 to represent the signal samples Y(n) = b(0)x(n) + b(1)x(n 1) + a(0)y(n 1) + a(1)y(n 2) + a(2)y(n 3) [16] 8. What is the range of address that can be decoded if A19 is pulled low in a processor with 20 address lines. Describe the Basic memory map of TMS320 C 54 16. [16]

Code No: 07A80406

R07

Set No. 4

IV B.Tech II Semester Examinations,APRIL 2011 DSP PROCESSORS AND ARCHITECTURES Common to Bio-Medical Engineering, Electronics And Telematics, Electronics And Instrumentation Engineering, Electronics And Communication Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain 4 bit barrel shifter with shift left operation.

2. Design a basic IIR lter, with a block diagram and equation.

[16]
[16]

3. Explain the dierent number formats of signals and coecients used in DSP systems. [16] 4. Explain aobut program control unit of TMS 320 C 54XX. [16]

5. What is Pipeline depth, explain? Is this concept is an advantage or disadvantage in a processor? Explain. [16]

6. Find the output y(n) of a linear shift invariant system with unit sample impulse response h(n) given by h(0)=3,h(1)=2, h(2)=1 and h(n)=0, for all other values of n, if it is feed with an input x(n) that is non zero only for n=0 & x(0) =2 & x(1)=1. [16] 7. Implement 8 point FFT on C54 XX scale factor for butteries is 0.50. [16]

8. Write C54XX code to initialize the DMA Channel destination register to # 5555h without using auto increment. Rewrite the code using auto increment for the same operation. [16]

Code No: 07A80406

R07

Set No. 1

IV B.Tech II Semester Examinations,APRIL 2011 DSP PROCESSORS AND ARCHITECTURES Common to Bio-Medical Engineering, Electronics And Telematics, Electronics And Instrumentation Engineering, Electronics And Communication Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain how hardware architecture, parallelism and pipelining inuence the speed of a processor. [16] 2. Explain Interrupt handling in C5416, with owchart. [16]

3. Draw 4 point FFT implementation structure for scale factor for all butteries 1. [16] 4. For example a recursive function is called in a DSP program , Does this function calling eects the speed of operation . Explain this context with respect to pipelining. [16] 5. Explain the methods to minimize the errors in the implementation of DSP systems. [16] 6. What is 2D signal processing explain in detail with example. [16]

7. How will you congure a TMS320C5416 processor to have on chip memories? Specify the address range in: On chip DRAM, for a program. How much RAM for data will be available in the specied conguration. [16]
8. Find the number of the multiplications required for the performing the convolution of two sequences with identical length 8 using direct and indirect method using FFT. [16]

Code No: 07A80406

R07

Set No. 3

IV B.Tech II Semester Examinations,APRIL 2011 DSP PROCESSORS AND ARCHITECTURES Common to Bio-Medical Engineering, Electronics And Telematics, Electronics And Instrumentation Engineering, Electronics And Communication Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain how pipelining concept is applied in DSP devices with suitable examples.[16] 2. Design a data memory system with the address range 000800H-000FFFH for a C5416 processor. Use 2Kx8 M SRAM memory chips. [16] 3. Explain about the interrupt structure in DSP. Give the order of priority of software and hardware interrupts and which interrupt gets executed at the time of execution? [16] 4. Find the degradation in amplitude gain when a sine wave of unit amplitude and 50 Hz frequency , sampled at 40 Hz is reconstructed using a zero order hold. [16] 5. In TMS320C54XX write a program to multiply Q15 number with Q0 number to obtain the result in Q0 notation. [16] 6. Explain the window method and frequency sampling methods for design of FIR lter. [16] 7. Explain the memory architecture required for a DSP device to implement : 2 power M point FFT with neat diagram. [16]
8. A time domain sequence of 73 elements is to be convolved with another time domain sequence of 50 elements using DFT to transform the two sequences, multiplying them, and then doing IDFT to obtain the resulting time domain sequence. To implement DFT or IDFT DIT FFT Is used. This has to be implemented on a xed point DSP, That takes 10 ns to do a real integer multiplication. Determine the convolution computation time. [16]