Professional Documents
Culture Documents
L08 EC360 (19) - DSP Processors
L08 EC360 (19) - DSP Processors
Sonali chouhan
General-Purpose Features
Several DSPs now include features traditionally associated with generalpurpose processors
User modes Memory management units Compiler-oriented features such as specialized addressing modes
Enable more sophisticated OSs Ease implementation of non-signalprocessing tasks Often make processors better compiler targets
DSP processors
SHARC, BlackFin, TMS320C55x, TMS320C67x, TMS320C64x 16-32 bit word size Single program Lightweight, often real-time OS Super Harvard Architecture Support Improved throughput Audio, Image and Video processing, Coding and Decoding, Cellular Base Station, Adaptive Filtering, Real Time operations
Super Harvard architecture improves upon the Harvard architecture by adding an instruction cache and a dedicated I/O controller In Harvard architecture data memory bus is busier than the program memory bus
Shared architectures can encourage stability, price competition, and wide third-party support But proprietary architectures
May achieve faster technological advances May have market momentum, integration advantages
Status registers. Loop registers. Data address generator registers. Interrupt registers.
0x0
SHARC microarchitecture
Modified Harvard architecture.
Program memory can be used to store some data.
Multiplier
Fixed-point operations can accumulate into local MR registers or be written to register file.
Fixed-point result is 80 bits.
Floating-point results always go to register file. Status bits: negative, under/overflow, invalid, fixed-point underflow, floating-point underflow, floatingpoint invalid.
Shifter:
zero, overflow, sign
Flag operations
All ALU operations set AZ (zero), AN (negative), AV (overflow), AC (fixedpoint carry), AI (floating-point invalid) bits in ASTAT. STKY is sticky version of some ASTAT bits.
Reference