Simulation of Paged Memory System

Nitin Handa, RK3701B41 B. Tech. CSE Lovely Professional University

---------------------------------------------------------------------------------------------------------------------------------------Abstract To run a program it must be brought into memory. While the size of memory has been increasing steadily, and modern CPUs now use long address fields capable of generating very large address spaces, the amount of memory available and actually installed in most computers remains a limiting factor. Virtual memory addresses the problems of sharing limited memory through architectural and OS software mechanisms that hide the presence of physical memory and present instead an abstract view of main memory to all applications. This paper describes the paged memory system for virtual memory and describes the concept- how virtual address generated by CPU is mapped to physical address as seen by main memory.
Index Terms MMU, Logical Address, Virtual Address, Physical Address, Paging, Page Table, Page Offset, Frame number

Logical Vs Physical address space An address generated by the CPU is commonly referred to as a logical address, whereas an address as seen by the memory unit is commonly referred to as a physical address. The compile time and load-time address binding schemes result in an environment where the logical and physical addresses are the same. However, the execution-time address binding scheme results in an environment where the logical and physical addresses differ. The set of all logical addresses generated by a program is referred to as a logical address space; the set of all physical addresses corresponding to these logical addresses is referred to as physical address space. The run-time mapping from virtual to physical address is done by the memory-management unit (MMU), which is a hardware device.

I.

INTRODUCTION

Main memory is a large array of words or bytes. Each word or byte has its own address. For a program to be executed, it must be mapped to absolute addresses and loaded into memory. Usually a program resides on a disk as a binary executable file. The program must be brought into memory and placed in a process for it to be executed. Addresses in the source program are generally symbolic (such as count). A compiler will typically bind these symbolic addresses to re locatable addresses. The linkage editor or loader will in turn bind these re locatable addresses to absolute addresses (such as 74014). Each binding is a mapping from one address space to another. Classically, the binding of instructions and data to memory addresses can be done at any step along the way: Compile time: If it is known at compile time where the process will reside in memory, then absolute can be generated. Load time: if it is known at compile time where the process will reside in the memory, the compiler must generate re locatable code. In this case, final binding is delayed until load time. Execution time/Run time: If the process can be moved during execution from one memory segment to another, then binding must be delayed until runtime. Special hardware must be available for this scheme to work.

Relocation Register 14000 Logical address 346 Physical address

CPU

Memory

14346

MMU

Dynamic relocation using relocation register

Paging System In Paged Memory System: Physical memory is broken into fixed sized blocks called frames. Logical memory is broken into blocks of the same size called pages. The backing store is divided into fixed-sized blocks that are of the same size as the memory frames.

The user program views the memory as one single contiguous space containing only this one program. In fact,

the user program is scattered throughout the physical memory, which also holds other programs. When a process arrives in the system to be executed, its size expressed in pages, is examined. Each page of the process needs one frame. Thus if the process requires n pages, there must be at least n frames available in memory. If there are n frames available in the memory, they are allocated in this arriving process. A page table is maintained which stores the frame no: corresponding to each page. Every address generated by the CPU is divided into 2 parts: Page Number (p) Page Offset (d) The page no: is used to index into the page table. The page table contains the base address of each page in physical memory. This base address is combined with the page offset to obtain the physical memory address that is sent to the memory unit. Logical address Physical address

of the virtual pages of the address space, thus letting us know where in physical memory they live. For our simple example above, the page table would thus have the following entries: .

Page Table Consider 64 byte virtual address space with page size of 16 bytes. To translate this virtual address that the process generated, we have to first split it into two components: the virtual page number (VPN), and the offset within the page. For this example, because the virtual address space of the process is 64 bytes, we need 6 bits total for our virtual address (26 = 64). Thus, our virtual address:

CPU

p
d

f
d

______ ______ ______ f_____ ______

Physical memory Where Va5 is the highest-order bit of the virtual address, and Va0 the lowest order bit. Because we know the page size (16 bytes), we can further divide the virtual address as follows:

Page table
PAGING HARDWARE

The page size is defined by the hardware. The size of page is typically a power of 2, varying between 512 bytes and 16 MB per page Page Number Page Offset P m-n d n The page size is 16 bytes in a 64-byte address space; thus we need to be able to select 4 pages, and the top 2 bits of the address do just that. Thus, we have a 2-bit virtual page number (VPN). The remaining bits tell us which byte of the page we are interested in, 4 bits in this case; we call this the offset. When a process generates a virtual address, the OS and hardware must combine to translate this virtual address into a meaningful physical address. Consider virtual address 21. Converting 21 into binary form, we get 010101, and thus we can examine this virtual address and see how it breaks down into a virtual page number (VPN) and offset:

For given logical address space 2m (m bits) and page size 2n. Consider a logical address space of 64 pages of 1024 words each, mapped onto a physical memory of 32 frames Size of logical address space (2m) = no. of pages page size 2m = 64 1024 2m = 26 210 So number of bits required: 2m =216 m=16 bit Page Table To record where each virtual page of the operating system is placed in physical memory, the operating system keeps a per-process data structure known as a page table. The major role of the page table is to store address translations for each

Thus, the virtual address 21 is on the 5th (0101th) byte of virtual page 01 (or 1). With our virtual page number, we can now index our page table and find which physical page that virtual page 1 resides within. In the page table above the physical frame number or PFN is 7 (binary 111). Thus, we can translate this virtual address by replacing the VPN with the PFN and then issue the load to physical memory. The process is described in following figure:

The offset stays the same (i.e., it is not translated), because the offset just tells us which byte within the page we want. Our final physical address is 1110101 (117 in decimal), and is exactly where we want our load to fetch data from. The Simulation Program The Simulation characteristics: program, developed, has following

It has flexibility to get size of logical address space and page size from user input, then it calculates the number of pages according to that. It prompts user to enter page table entries. Using those page table entries the logical address is mapped to calculate physical address. It displays all the page table entries entered by the user in table format. It displays the corresponding page number and frame number calculated from logical address entered by the user. For extracting Virtual Page number from logical address entered by user, we divide the logical address with page size. For extracting Page Offset from logical address we take modulus with page size. Finally it displays the logical address.

void main() { int pagetab[100],i,j; int size, msize, cnt, pos, logadd, int frameno, m=0; printf("\nEnter the memory size (in bytes): "); scanf("%d", &msize); printf("Enter the page size (in bytes): "); scanf("%d", &size); cnt=(msize/size); //number of pages printf("\nThe number of pages is %d",cnt); printf("\nEnter the page table Entries\n"); //enter page table entries for(i=0;i<cnt;i++) { printf("Page %d: ",i); scanf("%d", &pagetab[i]); } printf("\n-------------Page table--------------\n"); printf("\nVirtual Page Number\tPhysical Frame number"); for(i=0;i<cnt;i++) { printf("\n %d\t\t\t %d",i,pagetab[i]); } printf("\nEnter the logical address: "); scanf("%d", &logadd); pos=(logadd/size); m=logadd%size; printf("\nPage number: %d", pos); frameno=pagetab[pos]; printf("\nFrame number: %d\n", frameno); //compute physical address and display printf("\nThe corresponding physical address is %d", (m+(frameno*size))); getch(); } A Runtime Instance An output instance of simulation of some test cases is as following: Enter the memory size (in bytes): 64 Enter the page size (in bytes): 16 The number of pages is 4 Enter the page table entries Page 0: 3 Page 1: 7 Page 2: 5 Page 3: 2 -------------Page table---------------

The simulation program is developed in only one function i.e. main() The following is the implementation of main function:

Virtual Page Number Physical Page Number 0 3 1 7 2 5 3 2 //Test Case 1: Enter the logical address: 21 Page number: 1 Frame number: 7 The 117 corresponding physical address is

Test Case 2: for the same page table Enter the logical address: 46 Page number: 2 Frame number: 5 The corresponding physical address is 94

II.

MATH

All calculation has been shared in the Body text. III. UNITS

No units to share on this Publication. IV. HELPFUL HINTS

a. Figures and Tables All figures and tables have already been shown in the Body Text. b. Equations All the algorithmic calculations have already been used in the Body Text. REFERENCES 1. Operating System Concepts, Avi Silberschatz, Peter Baer Galvin, John Wiley & Sons, Inc. Operating Systems: Three Easy Pieces, Remzi H. Arpaci-Dusseau and Andrea C. Arpaci-Dusseau http://en.wikipedia.org/wiki/Paging http://williams.comp.ncat.edu/addrtrans.htm

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