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    Anna University of Technology Coimbatore

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    Selvanathan Rathinam
    The document contains questions for an ASIC Design course exam with two parts. Part A contains 7 short answer questions about special routing, simulated annealing, floor-planning objectives, controllability vs observability, fault types, designing a zero-detector in VHDL, and bath tub curves. Part B asks to answer 3 of 5 longer questions about design flow, transistor parasitic capacitance, sequential logic cells, anti-fuses in FPGAs, or comparing Actel and Altera logic cells.

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    Anna University of Technology Coimbatore

    Uploaded by

    Selvanathan Rathinam
    309 views1 page
    The document contains questions for an ASIC Design course exam with two parts. Part A contains 7 short answer questions about special routing, simulated annealing, floor-planning objectives, controllability vs observability, fault types, designing a zero-detector in VHDL, and bath tub curves. Part B asks to answer 3 of 5 longer questions about design flow, transistor parasitic capacitance, sequential logic cells, anti-fuses in FPGAs, or comparing Actel and Altera logic cells.

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    The document contains questions for an ASIC Design course exam with two parts. Part A contains 7 short answer questions about special routing, simulated annealing, floor-planning objectives, controllability vs observability, fault types, designing a zero-detector in VHDL, and bath tub curves. Part B asks to answer 3 of 5 longer questions about design flow, transistor parasitic capacitance, sequential logic cells, anti-fuses in FPGAs, or comparing Actel and Altera logic cells.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    309 views1 page

    Anna University of Technology Coimbatore

    Uploaded by

    Selvanathan Rathinam
    The document contains questions for an ASIC Design course exam with two parts. Part A contains 7 short answer questions about special routing, simulated annealing, floor-planning objectives, controllability vs observability, fault types, designing a zero-detector in VHDL, and bath tub curves. Part B asks to answer 3 of 5 longer questions about design flow, transistor parasitic capacitance, sequential logic cells, anti-fuses in FPGAs, or comparing Actel and Altera logic cells.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
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    Download as doc, pdf, or txt
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    ANNA UNIVERSITY OF TECHNOLOGY COIMBATORE Dept : ECE ME-VLSI Design(PT) Date:24/11/2010 :ASIC Design Course: Subject

    PART A (Answer all Questions: 7 X2=14 Marks) 1.What is special routing? 2.What do you mean by simulated annealing? 3.Write the objectives of floor-planning. 4.Differentiate controllability and observability. 5.Distinguish prime fault and dominant fault. 6.Design a zero-detector using VHDL code . 7.What do you mean bath tub curve? PART B (Answer any three Questions:3 X12=36 Marks) 1.a.Discuss in brief about Design flow with neat flowchart?(8 Marks) b. Write short notes on Transistor parasitic capacitance?(4 Marks) 2.Explain in detail about sequential logic cells? 3. Discuss in detail about various anti-fuses used in Field programmable logic cells ? 4.Compare the performance and characteristics of Actel and Altera logic cells? 5. Explain in detail about Kerninghan-Lin algorithm?

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