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5 6
5 6
Course Goals
Deepen understanding of CMOS analog circuit design through a top-down study of a modern analog system
The lectures will focus on Delta-Sigma ADCs, but you may do your project on another analog system.
ADVANCED
Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca
Develop circuit insight through brief peeks at some nifty little circuits
The circuit world is lled with many little gems that every competent designer ought to know.
ECE1371
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Date 2008-01-14 RS 2 2008-01-21 RS 3 2008-01-28 TC 4 2008-02-04 2008-02-11 RS 5 2008-02-18 2008-02-25 RS 6 2008-03-03 TC 7 2008-03-10 TC 8 2008-03-17 TC 9 2008-03-24 TC 10 2008-03-31 2008-04-07 TC 11 2008-04-14 RS 12
Lecture Example Design: Part 1 Example Design: Part 2 Pipeline and SAR ADCs ISSCC No Lecture Advanced Comparator & Flash ADC SC Circuits Amplier Design Amplier Design Noise in SC Circuits Matching & MM-Shaping Switching Regulator
Highlights
(i.e. What you will learn today)
1 High-Order Modulation
NTF, SQNR, instability, H
,
3 Toolbox
S&T C Project Report Q-level sim
Project Presentation
Demos: NTF synthesis and simulation Examples: Lowpass and Bandpass, MASH ABCD: State-space representation
4 Continuous-Time
Inherent anti-aliasing
5-3 ECE1371 5-4
ECE1371
B 0
H (e j ) 2 S ee() d
STF (z ) = z 1 NTF (z ) = 1 z 1
MOD2:
U
z z1 1 z1 Q
STF (z ) = z 1 NTF (z ) = ( 1 z 1 ) 2
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1. MODN
N integrators
N1 non-delaying, 1 delaying 40 20
NTF Comparison
1 z 1
(dB) NTF(e j2 f)
z z 1
z z1 STF (z ) = z 1 NTF (z ) = ( 1 z 1 ) N
0 20 40 60 80
MOD1
MO
100 -3 10
M
10
-2
M O D5
D
MO
D2
D3
10
-1
Normalized Frequency (f )
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Predicted Performance
In-band quantization noise power
0.5 OSR
IQNP =
0 0.5 OSR
NTF (e j 2 f ) 2 S ee(f ) df
over the
H (f )
2N 2 = ------------------------------------------------------( 2 N + 1 ) ( OSR ) 2 N + 1 e Quantization noise drops as the (2N+1)th power of OSR (6N+3) dB/octave SQNR-OSR trade-off
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n = 2 n = 3 n = 4
1 a
a 1 fs/fB
1 1 x 2 ( x 2 1 1 ( x 2
2 ) 2 dx , a1
2 ) 2 ( x 2 a 2 ) 2 dx , a1 2
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Solutions Up to Order = 8
Order 1 2 3 4 5 6 7 8
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Topological Implication
Feedback around pairs integrators: 2 Delaying Integrators -g 1 z 1 1 z 1 z z 1 Non-delaying + Delaying Integrators (LDI Loop) -g 1 z1
0, 3 5
3 7 ( 3 7 ) 2 3 35
0, 5 9 ( 5 9 ) 2 5 21 [Y. Yang]
0.23862, 0.66121, 0.93247 0, 0.40585, 0.74153, 0.94911 0.18343, 0.52553, 0.79667, 0.96029
Poles are the roots of 1 2 1 + g ------------ = 0 z 1 i.e. z = 1 j g Not quite on the unit circle, but fairly close if g<<1.
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Poles are the roots of gz 1 + ------------------- = 0 ( z 1 )2 j i.e. z = e , cos = 1 g 2 Precisely on the unit circle, regardless of the value of g.
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Simulation of MOD3-1b
(MOD3 with a Binary Quantizer)
1
0 1 0 200 100
Quantizer input gets large, even if the input is small. 6 quantizer levels are used by a small input.
10 20 30 40
HUGE!
1 -1 -3 -5 -70
0 100 200 0 10 20 30 40
ECE1371
Multi-bit Quantization
A modulator with NTF = H and STF = 1 is guaranteed to be stable if u < u max at all times, h(i ) where u max = nlev + 1 h 1 and h 1 = i =0 In MODN H (z ) = ( 1 z 1 ) N , so h(n) = { 1, a 1, a 2, a 3, ( 1 ) N a N , 0 } , a i > 0 and thus h 1 = H ( 1) = 2 N nlev = 2 N implies u max = nlev + 1 h
1
= 1
MODN is guaranteed to be stable with an N-bit quantizer if the input magnitude is less than /2 = 1. This result is quite conservative.
Similarly, nlev = 2 N + 1 guarantees that MODN is stable for inputs up to 50% of full-scale
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M even: mid-tread
v e=vy y
M
2
y (n) = u (n) + h(i ) e (n i ) i =1 u max + h(i ) = u max + h i =1 Then u max = nlev + 1 h y (n) nlev e (n) 1
1
u max + h(i ) e (n i ) i =1
M 1 M
M +1
v: odd integers from M to +M
M 1 M
M +1
v: even integers from M to +M
Moving the poles away from z = 1 toward z = 0 makes the gain of the NTF approach unity.
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N=3
N=2
N=1
1.25
1.5
1.75
umax (dBFS)
10
20 ECE1371
16
32
64
128
256
512
1024 5-22
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OSR
5-21
OSR
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OSR
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Example Waveforms
7 -order 17-level modulator, H
16
Example Waveforms
th
= 2
th
= 8
SQNR = 55 dB @ OSR = 8
-16
50
100 5-25
-16
50
100
Time Step
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Time Step
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Simulated Spectra
0 20 40 120
SQNR Curves
100
dBFS/NBW
60 80 100 120
SNR (dB)
80
60
40
20 140 NBW = 1.8x104 160 0 ECE1371 0.1 0.2 0.3 0.4 0.5 5-27 0 120 100 80 60 40 20 0
Normalized Frequency
ECE1371
2. Feedback Topology
-g
U
Feedforward Topology
a1
V U
a2 I I -g I a3 Q
V
I a1 a2
I a3
N integrators precede the quantizer Feedback from the quantizer to the input of each integrator (via a DAC) Local feedback around pairs of integrators to control NTF zeros Multiple input feed-in branches are possible
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N integrators in a row Each integrator output is fed forward to the quantizer Local feedback around pairs of integrators to control NTF zeros Multiple input feed-in branches also possible
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L 0(z ) = L 1(z ) = L(z ) 1 1 - = -------------------NTF (z ) = ---------------------1 L 1(z ) 1 + L(z ) L(z ) STF (z ) = -------------------- =1 H (z ) 1 + L(z ) NTF (e j )
1
Y = L0 U + L1 V V = Y +E
V = STF U + NTF E , where 1 - & STF = L 0 NTF NTF = -------------1 L1 Inverse Relations: L1 = 1 1/NTF, L0 = STF / NTF
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NTF STF
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STF Comparison
10
Feedforward Feedback
dB
0 10 20 30 40 0 0.25 0.5
3. Toolbox
http://www.mathworks.com/matlabcentral/fileexchange
L1
Quantizer:
M=1 1
2 2
M=2 2 v v y
M=3 3 1 y e v y e
predictSNR, simulateDSM, simulateSNR Time-domain simulation and SNR measurements. ECE1371 Also mapCtoD simulateESL designHBF Manual is delsig.pdf 5-35
1 e
-1 -3
NTF Synthesis
synthesizeNTF Not all NTFs are realizable
Causality requires h(0) = 1 , or, in the frequency domain, H () = 1 . Recall H (z ) = h(0) z 0 + h(1) z 1 +
< 1.5
Can optimize NTF zeros to minimize the meansquare value of H in the passband The NTF and STF share poles, and in some modulator topologies the STF zeros are not arbitrary
Restrict the NTF such that an all-pole STF is maximally at. (Almost the same as Butterworth poles.)
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OSR = 32; H = synthesizeNTF(5); plotPZ(H); f = linspace(0,0.5); z = exp(2i*pi*f); H_z = evalTF(H,z); plot(f,dbv(H_z)); g = rmsGain(H,0,0.5/OSR)
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Lowpass NTF
Out-of-band gain = 1.5
0
dB
20
40
40
60
60 0 1/64
Zeros spread across the band-of-interest to minimize the rms value of the NTF.
0.5
80 0
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Improved NTF
0
Bandpass Example
OSR = 64; center frequency f0 = 1/6; H=synthesizeNTF(6,OSR,1,[],f0);... [] or NaN means use default value, i.e. Hinf = 1.5
dB
20
60
rms gain = 66 dB
40
70
60
80 0 1/64
80
0.5
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dB
20
NTF
40
60 0
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dBFS/NBW
0.5 5-46
OSR=32
80 Peak SNR is 85 dB. Max. input is 3 dBFS.
SQNR (dB)
60 0 40
20 1 0 100 80 60 40 20 0 0 50 100
dBFS/NBW
-40 -60 -80 -100 -120 NBW = 1.8x104 fs -140 0 0.1 0.2 0.3 0.4 0.5
x (k )
nn n2
= C x (k ) + D u (k ) v (k ) 1n 12 n 2 n A B ABCD = 1 C D
5-50
x (k + 1) = Ax (k ) + B u (k ) v (k )
ECE1371
1 x ------------ 3 z 1
1 x ------------ 2 z 1
a3
1 x ------------ 3 z 1
1 = 1 0 0
0 1 1 0
0 g1 1 1
1 1 0 0
0 1 1 0
0 0 1 1
a 1 a 2 a 3 0
u
b1
1 x ------------ 1 z 1
a1 a2
1 x ------------ 2 z 1
a3
1 x ------------ 3 z 1
1 = 1 0 0
0 1 1 0
0 0 1 1
b 1 a 1 b 2 a 2 b 3 a 3 b4 0
V1
= U + H 1E 1
Digital Cancellation
U
V = V 1 H 1V 2 = U H 1H 2E 2
V1
3-input, 2-output linear system
0.5
E1
Loop Filter
V2
= E 1 + H 2E 2
0.25 z -1
1 z -1
V2
H1
4. A Continuous-Time ADC
Sampler v v1 ContinuousTime Analog Input Loop Loop Filter Filter CK Coarse ADC Digital Out
PSD (dBFS/NBW)
50
Improved noise-shaping
100 40dB/decade
NBW = 4.5 10 1
Loop lter implemented with continuous-time circuitry Sampling occurs after the loop lter
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Example: MOD1-CT
Block Diagram
uc
Inherent Anti-Aliasing
ADC with CT Loop Filter
C
Schematic
v uc
R
uc v
L 0 c (s ) L 1 c (s)
CK
Q
DAC
DAC
IDAC CK
Equivalent system with DT feedback path uc L 0 c (s) L 1(z ) NTF (z ) Q v STF = L 0 c (s) NTF (z )
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= es
NTF = 1z1
dB
Zeros @ s = 2ki
STF =
1z1 s
20 30 40 50 0
Inherent Anti-Aliasing
Frequency (Hz)
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3 Toolbox
Demos: NTF synthesis and simulation Examples: Lowpass and Bandpass, MASH ABCD: State-space representation
The effective anti-alias lter is L 0 c (f ) STF ( f ) AAF (f ) = ----------------------------- = -------------------------STF (f alias) L 0 c (f alias)
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4 Continuous-Time
Inherent anti-aliasing
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Homework #5
1 0 1 1
3 Construct the block diagram of a 4th-order single-loop 9-level ADC employing the CRFB topology that achieves SQNR > 100 dB at OSR = 32 and verify it.
Choose H such that the stable input range is maximized. Plot the SQNR-versus-amplitude curve and note the value of u max . Compare with the h 1 criterion. Realize your NTF with a CRFB-style modulator having a single input feed-in. Ensure STF(dc) = 1. Do dynamic range scaling for umax = 1 dBFS and state maxima less than unity. You may use the toolbox function scaleABCD. Plot the state maxima as functions of the input amplitude. Implement your block diagram with C/Matlab code and verify that your coded modulator behaves the same as your MATLAB modulator.
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2 Obtain an NTF for MOD2b using synthesizeNTF with H = 2.5 , OSR = 128 and opt=1.
Plot the NTFs poles and zeros as well as its frequency response. Include those of MOD2. Compare MOD2bs SQNR-vs.-input-amplitude curve with MOD2s using simulateSNR.
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x 1c 1.5
vc
x 2c
Q
(clocked)
delay-free
DAC
It is sufcient to verify that the sampled pulse response of the loop lter is the same as MOD2s.
If this modulator is used at an oversampling ratio of 64, what is its minimum alias attenuation?
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