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A 24 Port 10G Ethernet Switch: Andrew Lines
A 24 Port 10G Ethernet Switch: Andrew Lines
AndrewLines
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Tahoe:FirstFocalPointFamilyMember
Tahoe
Thelowestlatencyfeaturerich10GEswitchchip
10GEthernetswitch 24Ports Linerateperformance 240Gb/sbandwidth 360Mframes/s Fullspeedmulticast Fullyintegratedsinglechip 1MBframememory 16KMACaddresses LowestlatencyEthernet 200nswithcoppercables RichFeatureSet Extensivelayer2features FlexibleSERDESinterfaces 10GXAUI(CX4) 1GSGMII
SPI
CPU
JTAG
LED
FrameProcessor (Scheduler)
Nexus
Nexus
XAUI(CX4)
RapidArray
(packetstorage)
AsynchronousBlocks 3
XAUI(CX4)
TahoeHardwareArchitecture
Modulararchitecture,centralizedcontrol
SPI Interface CPU Interface JTAG Interface LED Interface
Management
FrameControl
Lookup Handler Stats
LCI
RXPortLogic
Ser Des P C S
M A C
Scheduler
TXPortLogic
M A C P C S Ser Des
SwitchElementDataPath
Nexus
RXPortLogic
Ser Des P C S
Nexus
RapidArray (1MBSharedMemory)
M A C
TXPortLogic
M A C P C S Ser Des
TahoeChipPlot
FabricatedinTSMC0.13um
RapidArrayMemory 1MBshared EthernetPortLogic SerDes PCS MAC NexusCrossbars 1.5Tb/stotal 3nslatency
MACTable 16Kaddresses
BridgeFeatures
Robustsetoflayer2features
GeneralBridgeFeatures 16KMACentries STP:multiple,rapid,standard LearningandAgeing MulticastGMRPandIGMPv3 VLANTag(IEEE802.1Q2003) Add/Removetags Perportassociationdefault 4KentryVLANIDtable PerVLAN,perportSTP Scheduling,Pause,Congestion 16trafficclassesforWRED 4queuesperportscheduling WRRorstrictpriority Pausesupport Security 802.1x;MACAddressSecurity Monitoring Richmonitoringterms logicalcombinationofterms SrcPort,DstPort,VLAN, TrafficType,Priority,Src MA,DstMA,etc. Monitoringaction Drop,Mirror,Redirect, Count,ChangePriority 16rulesperframe Statistics RFC2819compliant Allcountersare64bits 13countergroups RMONandSMON Fulcrumextensions
LinkAggregationandFatTreeSupport
TrueIEEEcompliantLink Aggregationusedtogrouplinks betweenlineandfabricswitches Symmetrichashingguarantees aconversationresolvestothe samefabricswitch Ingressto fabrichop usesLink Aggregation hardwareto loadbalance
LinkAggregation chipfeatures
Configuration 12trunkgroups Anyportsinagroup Upto12members Hash:EthernetCRC ProgrammableInput SA,DA,Type,VLAN ID,Priority,Sourceport SADAhashsymmetry forcing Grouprenumbering OtherHWhooks Slowprotocoltraps
Fabri c Chip
Fabri c Chip
Line Chi p
Line Chi p
Line Chi p
MACA
MACB
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TwoVersionsSamplinginQ12006
AnnouncedpricingatSC|05 Firstcompanytobreakthrough$20/portfor10GE
FM2224 2410GEInterfaces 1433ballBGA 40mm $450
24PortReferenceDesign(NowShipping)
EvaluationPlatform
CSL
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ETH
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TahoeHardwareFeatures
MultipleFrequencyRequirements
Mixeddesignstyles
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TahoeChipStatistics
TSMC0.13umLVODFSG1.2V 105Mtransistors Over3000uniquecells 1.5MBtotalSRAM(allasynchronous) 0.51.5Wperportdependingonactivity(36Wpeak) FlipchipBGApackage
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SyncandAsynctogether?
Useexisting3rdpartyIPcoresforsynchronousI/O, suchashighspeedSERDESfromRAMBUS. Usestandardsynchronoussynthesis,place,and routeflowtoimplementlogicallycomplexunitswith lowerspeedrequirements. Useasyncflowonlywhereithasthebiggest advantagesSRAMs,crossbars,chipwide interconnect,FIFO's,andhighspeedblocks. MustpartitiontheprobleminArchitecture. SomedayeverythingwillbeAsync,butnotyet!
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SimpleSynctoAsyncConversion
SynchronousRequest/GrantFIFOprotocol
S2A A2S
Asynchronous Datapath
SeamlesslyBridgesDifferentClockDomains
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DigitalVerification
OftenoverlookedinAcademia,butcrucialinIndustry! Therearenearlyasmanyengineersinverificationasthere areindesign. Useindustrystandardapproachofafullchipsimulation withtestbench,testsuite,regressionengine. Trytogetfulllineandconjunctcoverage. ConvertCSP/PRSintoVerilogforchiplevelsimulation combinedwithsynchronousblocks. Alsousesimpleclosedenvironmentselfteststocheckthat differentlevelsofasyncdecompositionmatch,butthisis notsufficient.
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DesignForTest
Mustbeabletocheckformanufacturingdefectsin asyncblocks. Introducespecialscanbufferswhichintegratea serialshiftregisterintoanasyncbuffer. Connectthescanbuffersinto16serialscanchains. Canissueaninject,drain,orskipcommandtoeach scanbufferonascanchain. Externalclockedinterfacetostandardtesters. Commercialfaultgradingtool(ZOIX).
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AsyncSRAMinFocalPoint
SRAMTestandRepair
ScanbuffersintegratedintomostSRAMbanks. OnchipacceleratedtestingforlargestSRAM. Testerproducesadefectmap. Burnfuseboxtousespareaddressestorepairbitor addresslineerrors. InmanySRAMs,cansimplyremoveablockofbad segmentsofstoragefromthefreememorypool. Thiscanrepairmanymoretypesoferrors. Yieldlooksquitegoodsofar,asexpected.
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FocalPointTestPlatform
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FocalPointEPBoard
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FocalPointEPRack
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Wishlist
CSPvsCSPformalverification CSPvsPRSformalverification ATPGtoolsforasynccircuits Statictimingforasynccircuits AsyncsynthesisfromCSP 65nmadvice
Ifyou'veworkingonanyofthese,talktome!
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