SUCCESS STORY

CORPORATE PROFILE
Sound Design is a leading designer and manufacturer of ultralow-power semiconductor solutions for hearing instruments and a leading provider of advanced high-density interconnect technologies

CAD E N C E A N D S O U N D D E S I G N TEC H N O L O G I E S
Optimizing power and size for breakthrough mixed-signal chip

This type of complex mixed-signal design would typically take a year to complete, but with the help of Cadence, our in-house IC design team had high-quality results five months earlier.
Sean Lord, Corporate Vice President of Engineering, Sound Design Technologies

DESIGN CHALLENGES
Develop the industrys first monolithic, 4-core audio aid Shrink the die size to meet a 3.8mm limit for the human ear Meet ultra-low power targets with customized clock timing and advanced chip stacking

BREAKTHROUGH CHIP FOR MEDICAL INDUSTRY

Founded in 2007 via the acquisition of Gennum Corporations Audio Division and Manufacturing Operations, Sound Design Technologies Ltd. develops ultralow-power digital signal processors (DSPs), capacitors, and radio frequency (RF) components for wireless headsets, hearing devices, and professional audio equipment. Shortly after splitting from its parent company, Sound Design decided to launch an entirely new portfolio of DSP products featuring high-end hearing-aid algorithms with high bandwidth that deliver unprecedented sound quality and comfort to consumers. Their groundbreaking Wolverine series of system-on-chip programmable multi-processor DSPs would require a mixed-signal chip with an ultra-miniature footprint and the lowest power consumption of any DSP on the market.

BUSINESS CHALLENGES
Build an optimized design environment after splitting from parent company Launch a new product portfolio without high-end digital implementation expertise Meet an ambitious 7-month tapeout deadline for a groundbreaking chip Achieve an aggressive power target while reducing overall cost per chip

CADENCE SOLUTIONS
Provide a complete, productionproven, advanced digital design, implementation, and verification flow Mitigate risk and optimize time to productivity with expert design consulting services

CADENCE PRODUCTS
Cadence Services Encounter digital implementation and low-power verification technologies Encounter RTL Compiler synthesis

The Cadence team was an important part of our success and through their collaboration, we were able to meet these extremely aggressive goals.
Such a bold project presented Sound Design with a number of challenges. As a new company, they would first have to quickly build a complex design flow and environment. This would also be the teams first major chip in five or six years, so their knowledge base was incomplete. Sound Design was ready to tackle the front end, but they lacked the expertise required for back-end digital design and implementation for this level of complexity. Under the pressure of an ambitious 7-month tapeout deadline, Sound Design needed to optimize their time to productivity by outsourcing parts of the project to experts. Familiar with Cadence technology and comfortable using Cadence products for the front end, Sound Design approached the Cadence Services group to handle the back end and collaborate on advanced power management and clocking strategies. The Cadence team had the level of expertise required for this kind of next-generation chip, explains Sean Lord, Corporate Vice President of Product Development at Sound Design. Its rarely a clean experience to go through a split. Cadence smoothed that transition for us by delivering a holistic, production-proven CAD environment and expert design consulting services. these goals required creative engineering and close collaboration between Cadence and Sound Design. A unique aspect of this collaboration was that the entire engagement process was remote. In fact, the teams never met face-to-face until just before tapeout. The Cadence team, comprising experts in digital design and implementation and analog design, was based in Carey, North Carolina. Sound Designs team, who handled the logic design, was based in Ontario, Canada. But with frequent team meetings, video conferencing, and clear and continuous communication, we stuck to the schedule and met all the goals we aspired to hit, says Sean Lord. When designing chips for hearing aids, in which so many complex analog and digital components must be integrated on one die, power consumption and area the two biggest challenges. Sound Design knew there would be an area advantage to using a 65nm process, but the cost would not be feasible, nor would there be any analog benefit. And so throughout project, the two teams employed the TSMC 90nm Low-Power process and relied on chip stacking for the passive components. The ceramic substrates were complicated, but allowed them to stack the chip layers to optimize size while keeping heat in check. Sound Design also had strict clocking requirements and relied on Cadence for a low-power clocking strategy. In digital cores, typical place-and-route is not practical, and this design in particular comprised hundreds of individual clocks rather than one large clock tree. This required handscripting and clock customization by Cadence Services, plus the integration of several Cadence lowpower technologies.

Using the Cadence Encounter Timing System, the teams had access to a special low-power memory IP library and were able to optimize the clock trees for ultra low-power through manual tweaks and expert placement. Encounter Conformal Low Power verified any problems in the constraints and identified multi-cycle paths where the design was constrained to a single-cycle path. To optimize the flow, the teams relied heavily on Encounter RTL Compiler to easily manage constraints between the geographically dispersed teams and to achieve timing closure. The teams also used Cadence VoltageStorm Power Analysis to ensure accuracy; as a result, the final chip was within 5% of the low-power margin engineers had budgeted for leakage and dynamic power. In portable devices for which ultralow-power means 100200mW total power consumption, hitting the predicted power target within 5% (within 5-10mW) is a huge achievement. Sean Lord comments, We were not only very pleased with the low-power margin we achieved with the real silicon, but we were also blown away by how closely the models and simulation environment actually came to the real silicon. I was very impressed with the tools. Well done, Cadence. The amount of hand-optimization required to meet the power targets was intensive, but ultimately Cadence helped Sound Design achieve the lowest power consumption of any DSP on the market.

OPTIMIZING POWER, SIZE, AND COST

Blowing away the competition in a new market space meant hitting aggressive power and performance targets. But to ensure the end product would fit comfortably in the human ear, shrinking the die size would be crucial. And to make their DSPs viable for a wider global market, they would also have to minimize costs. A complex 90-nm mixed-signal chip with such stringent requirements typically takes a whole year to complete; Sound Design had just 7 months. Achieving

END RESULTS AND FUTURE PROJECTS

Because of the narrow market window, there wasnt time to perform as much functional verification as they had wanted. A lot of late-stage engineering change orders (ECOs) meant the teams were finding digital bugs within weeks of their tapeout deadline. Sean Lord explains, Without Cadence and their ability to manage churn and change, we may not have met our very aggressive schedule goals. The Cadence team created the chip in just 21 daysit was

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CADENCE AND SOUN D D E S I G N

amazing. We had estimated 40 days. When the chip first came back, it was up and running in 24 hours. Although it had some bugs, the team performed all the necessary tweaks before mass production, and with just one metal spin. By collaborating with Cadence Services, Sound Design was able to meet its ambitious launch date for the Wolverine series of DSPs. And this was achieved while still meeting the die size, power, and performance requirements for the industrys first 4-core audio aid. In just 7 months, the collaborating teams created a 90nm multi-million-gate chip with just 4 metal layers. These technologies now offer all electronic product developers innovative and cost-effective means for extreme miniaturization, helping Sound Design move into much broader markets. This experiencethe knowledge we gainedmakes it feasible for us to use Cadence technologies and services again for the next generation of the chip, concludes Sean Lord. With a goal of enhancing the verification process, Sound Design Technologies will be using Cadence verification tools and services for two upcoming chip projects.

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