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    MEVD-203 VLSI Test and Testability Dec-2012

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    Prakash Sinha
    The document appears to be an exam for a graduate course on VLSI Test and Test Ability. It contains 8 questions testing students' knowledge on topics like CMOS circuit testing, different levels of testing, system and field testing, delay models, event driven simulations, fault detection using Boolean difference, primitive and propagation cubes, sequential circuit testing, controllability and observability, random testing, ad-hoc testability methods, full and partial scan design, RAMBIST, IDDQ testing, path sensitization, fan out oriented test generation, and boundary scans. Students are instructed to attempt two sections from each question, with section (a) being compulsory.

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    MEVD-203 VLSI Test and Testability Dec-2012

    Uploaded by

    Prakash Sinha
    152 views1 page
    The document appears to be an exam for a graduate course on VLSI Test and Test Ability. It contains 8 questions testing students' knowledge on topics like CMOS circuit testing, different levels of testing, system and field testing, delay models, event driven simulations, fault detection using Boolean difference, primitive and propagation cubes, sequential circuit testing, controllability and observability, random testing, ad-hoc testability methods, full and partial scan design, RAMBIST, IDDQ testing, path sensitization, fan out oriented test generation, and boundary scans. Students are instructed to attempt two sections from each question, with section (a) being compulsory.

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    The document appears to be an exam for a graduate course on VLSI Test and Test Ability. It contains 8 questions testing students' knowledge on topics like CMOS circuit testing, different levels of testing, system and field testing, delay models, event driven simulations, fault detection using Boolean difference, primitive and propagation cubes, sequential circuit testing, controllability and observability, random testing, ad-hoc testability methods, full and partial scan design, RAMBIST, IDDQ testing, path sensitization, fan out oriented test generation, and boundary scans. Students are instructed to attempt two sections from each question, with section (a) being compulsory.

    Copyright:

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    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    152 views1 page

    MEVD-203 VLSI Test and Testability Dec-2012

    Uploaded by

    Prakash Sinha
    The document appears to be an exam for a graduate course on VLSI Test and Test Ability. It contains 8 questions testing students' knowledge on topics like CMOS circuit testing, different levels of testing, system and field testing, delay models, event driven simulations, fault detection using Boolean difference, primitive and propagation cubes, sequential circuit testing, controllability and observability, random testing, ad-hoc testability methods, full and partial scan design, RAMBIST, IDDQ testing, path sensitization, fan out oriented test generation, and boundary scans. Students are instructed to attempt two sections from each question, with section (a) being compulsory.

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    Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal MEVD-203 M.E./M.Tech.

    (Second Semester) EXAMINATION, Dec 2012


    (Grading/Non-Grading)

    VLSI TEST AND TEST ABILITY


    Time: Three Hours Maximum Marks: GS:70 Note: Attempt two sections from each question. Section (a) is compulsory.

    1. (a) How is the testing of CMOS circuits done ? (b) Discuss different levels of testing. 2. (a)What do you understand by system and field testing? (b) Discuss about the Delay Models. 3. (a) What is meant by Event Driven Simulations ? (b) How is fault detected using Boolean Difference ? 4. (a) What do you understand by primitive and propagation cubes? (b) How is testing of sequential circuits done as iterative combinational circuits? 5. (a) What is meant by Controllability and Observability? (b) What do you understand by random testing? 6. (a) What are the Ad-hoc methods for designing and testability? (b) Explain briefly about Full scan and Partial scan design. 7. Explain briefly: (a) RAMBIST (b) IDDQ Test pattern 8. Write short notes on the following: (a) Path Sensitization (b) Fan out oriented test generation (c) Boundary scans

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