LAB MANUAL

Subject: Digital system design Class: Third Year Pre-requisite: DSD

Subject Code: BET4205 C Semester: V Faculty:

CONTENTS

LAB 1 .................................................
IMPLEMENTATION OF 8:1 MULTIPLEXER ............................

LAB 2 .................................................
IMPLEMENTATION OF 2:4 DECODER ................................

LAB 3 ................................................
IMPLEMENTATION OF 8:3 ENCODER ...............................

LAB 4 ................................................
IMPLEMENTATION OF 2 BIT COMPARATOR ..........................

LAB 5 ................................................
IMPLEMENTATION OF BINARY TO GRAY CODE CONVERTER .............

LAB 6 ................................................
IMPLEMENTATION OF T FLIP FLOP ...............................

LAB 7 ................................................
IMPLEMENTATION OF J-K FLIP FLOP .............................

LAB 8 ................................................
GENERATE RAMP WAVEFORM USING DAC. ...........................

LAB 9 ................................................
SCROLLING OF DATA ON SEVEN-SEGMENT DISPLAY USING KEYBOARD. ..

LAB 10 ...............................................
DESIGN OF 4-BIT ARITHMETIC LOGIC UNIT .......................

LAB 11 ...............................................
GENERATE RAMP WAVEFORM USING DAC. ...........................

LAB 12 ...............................................
IMPLEMENTATION OF STEPPER MOTOR CONTROLLER ...............

LAB 1
Implementation of 8:1 Multiplexer
Introduction:The Multiplexer is a combinational circuit that is the most widely used circuit in Digital Design. Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. A Digital Multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. In this lab, you will learn how to implement an 8:1 Multiplexer using Xilinx ISE Tool. Write the functionality in the Xilinx project navigator. Run a functional HDL simulation. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying different inputs and verify the outputs.

Objectives:After completing this lab, you will be able to implement the multiplexer in FPGA and verify it on Mechatronics make Spartan-II Protoboard.

Design Description:For selecting one out of n inputs for connection to the output, a set of m select inputs are required. 2m = n (n= Number of inputs, m = Number of select lines) Depending upon the digital code applied at the select inputs one out of 8 data sources is selected & transmitted to a single output Channel. Truth Table of 8:1 Mux: Select Inputs A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Output Y I0 I1 I2 I3 I4 I5 I6 I7

Steps to implement the 8:1 multiplexer in the Spartan-II FPGA

Step 1: Step 2: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go to FILE New projectSelect Device.

Step 3:

Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the name 8_1_MultiplexerDefine portsFinish.

Step 4:

Generate the Behavioral VHDL Code for the 8_1_Multiplexer.

Step 5: Step 6:

Step 7:

Check syntax, and remove errors if present. Simulate the design using Modelsim. Highlight 8_1_Multiplexer.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right click Click on new sourceClick on test bench waveformGive file nameSelect entityFinishGive inputs Click on simulate behavioral model see the output. Click on test bench file. Test bench file will open in main window. Assign all the signals and save File. From the source of progress window.click on Simulate Behavioral Model. Modelsim window will open. Verify your design in wave window by seeing behavior of output signal with respect to input signal. Close the Modelsim window.

Step 8:

Synthesize the design using XST. Highlight 8_1_Multiplexer.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

If there are any errors, you can view the error through the console window otherwise continue on to the next step. Step 9: Step 10: Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Run the Xilinx Implementation Tools.
1

Step 11: Step 12:

Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-II 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Double click on Configure Device to download the bit stream. Apply input through DIP Switches (IL3 to IL10) and select lines are mapped to (IL0 to IL2) output is displayed on LEDs.

Experimental Set up:-

Conclusion:Design of 8:1 Multiplexer is implemented in Spartan-II Protoboard and is verified according to the truth Table.

VHDl Code for 8:1 Multiplexer:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( I0, I1, I2, I3, I4, I5, I6, I7: in std_logic; sel : in std_logic_vector(3 downto 0); Y : out std_logic); end mux; architecture Behavioral of mux is begin Y <= I0 when sel="000" else I1 when sel="001" else I2 when sel="010" else I3 when sel="011" else I4 when sel="100" else I5 when sel="101" else I6 when sel="110" else I7; end Behavioral;

UCF for 8:1 Multiplexer:net net net net net net net net net net net net sel<0> loc = p4; sel<1> loc = p5; sel<2> loc = p6; I0 loc = p7; I1 loc = p8; I2 loc = p9; I3 loc = p10; I4 loc = p22; I5 loc = p21; I6 loc = p20; I7 loc = p18; Y loc = p46;

1. Design a 16:1 mux using 4:1 mux. 2. Design a 32:1 mux using 16:1 mux and 2:1 mux as basic components. 3. Design a xor Gate using mux. 4. Design a Half adder and Full adder using Mux. 5. Design a customized multiplexer with five input buses [A, B, C, D, E]. Three bit select line [S] decides which input bus should drive 4-bit output bus, according to the table given below
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 T A B A C A D A E

LAB 2
Implementation of 2:4 Decoder
Introduction:Discrete quantities of information are represented in digital systems with binary codes. A binary code of n bits is capable of representing up to 2n distinct elements of the coded information. A Decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. Decoder is similar to a Demultiplexer except that there is no data input. The only inputs are the control inputs A and B. In this lab, you will learn how to implement a 2:4 Decoder using Xilinx ISE Tool. Write the functionality in the Xilinx project navigator. Run a functional HDL simulation. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying binary inputs and verify the outputs.

Objectives:After completing this lab, you will be able to implement the Decoder in FPGA and verify it on Mechatronics make Spartan-II Protoboard.

Design Description:The Truth Table of 2:4 decoders is as below. Control Lines B 0 1 0 1 Output Lines Y1 Y2 0 0 1 0 0 1 0 0

A 0 0 1 1

Y0 1 0 0 0

Y3 0 0 0 1

The Block Diagram of 2:4 decoder is as shown below.

Steps to implement the 2:4 Decoder in the Spartan-II FPGA

Step 1: Step 2: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go to FILE New projectSelect Device.

Step 3: Step 4: Step 5: Step 6:

Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the name 2_4_DecoderDefine portsFinish. Generate the Behavioral VHDL Code for the 2_4_Decoder. Check syntax, and remove errors if present. Simulate the design using Modelsim. Highlight Decoder_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right click Click on new sourceClick on test bench waveformGive file nameSelect entityFinishGive inputs Click on simulate behavioral model see the output.

Step 7:

Synthesize e design using XST.

Highlight 2_4_Decoder.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can view the error through the console window otherwise continue on to the next step.

Step 8: Step 9:

Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Run the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-II 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Double click on Configure Device to download the bit stream. Apply input through DIP Switches (IL0 to IL1) and output is displayed on LEDs.

Step 10: Step 11:

Experimental Set up:-

Conclusion:Design of 2:4 Decoder is implemented in Spartan-II Protoboard and is verified according to the truth Table.

VHD Code for 2:4 Decoder:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Decoder is Port ( D_in : in std_logic_vector(1 downto 0); D_out : out std_logic_vector(3 downto 0)); end Decoder; architecture Behavioral of Decoder is begin D_out <= "0001" when D_in = "00" else "0010" when D_in = "01" else "0100" when D_in = "10" else 1000; end Behavioral;

UCF for 2:4 Decoder:net D_in<0> loc = p4; net D_in<1> loc = p5; net D_out<0> loc = p46; net D_out<1> loc = p47; net D_out<2> loc = p48; net D_out<3> loc = p49;

1. Design 3:8 decoder and implement it in FPGA 2. Design a full adder using 3:8 decoders. 3. Design 4 Bit BCD to Seven-Segment Decoder for common cathode /common anode display. o If the input number is greater than 9 o Dont care for these inputs. o Indicate the error by displaying a letter E. o Compare the simulation result for above cases.

LAB 3
Implementation of 8:3 Encoder
Introduction:An Encoder is a digital circuit that performs the inverse operation of a decoder. An Encoder has 2n input lines and n output lines. The output lines generate the binary code corresponding to the input value. In this lab, you will learn how to implement a 8:3 Encoder using Xilinx ISE Tool. Write the functionality in the Xilinx project navigator. Run a functional HDL simulation. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying eight inputs and verify the binary outputs.

Objectives:After completing this lab, you will be able to implement the Encoder in FPGA and verify it on Mechatronics make Spartan-II Protoboard.

Design Description:The Truth Table of 8:3 Encoder is as shown below. Y0 Y1 Y2 Y3 Y4 Y5 Y6 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 The Block diagram of the 8:3 Encoder is as below.
Y7 0 0 0 0 0 0 0 1 C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1

Steps to implement the 8:3 Encoder in the Spartan-II FPGA

Step 1: Step 2: Step 3: Step 4: Step 5: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go to FILE New projectSelect Device. Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the name 8_3_EncoderDefine portsFinish. Generate the Behavioral VHDL Code for the 8_3_Encoder. Check syntax and remove errors if present.

Step 6:

Step 7:

Step 8: Step 9:

Step 10: Step 11:

Simulate the design using Modelsim. Highlight Encoder_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right click Click on new sourceClick on test bench waveformGive file nameSelect entityFinishGive inputs Click on simulate behavioral model see the output. Synthesize the design using XST. Highlight 8_3_Encoder.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or doubleclick on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfullcompleted. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can view the error through the console window otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Run the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-II 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Double click on Configure Device to download the bit stream. Apply input through DIP Switches (IL0 to IL7) and output is displayed on LEDs.

Experimental Set up:-

Conclusion:Design of 8:3 Encoder is implemented in Spartan-II Protoboard and is verified according to the truth Table.

1. Design 8:3 Priority encoder with Y7 having highest priority 2. Give application of encoders.

LAB 4
Implementation of 2 Bit Comparator
Introduction:The comparison of two numbers is an operation that determines if one number is greater than, less than or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The output of the comparison is specified by the three binary variables that indicate whether A is greater than B (A>B), A is less than B (A<B) or A is equal to B (A=B). In this lab, you will learn how to implement a 2 Bit Comparator using Xilinx ISE Tool. Write the functionality in the Xilinx project navigator. Run a functional HDL simulation. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying inputs and verify the outputs.

Objectives:After completing this lab, you will be able to implement the 2 Bit Comparator in FPGA and verify it on Mechatronics make Spartan-II Protoboard.

Design Description:A and B are two 2 bit numbers. As the two numbers are binary, the digits are either 0 or 1. So the numbers are equal only when the pairs of the significant digits are equal. In terms of equation, A=B only when X i = 1 Where X i = A I B i + A i B i To determine as to whether A is greater than B or less than B see the relative magnitudes of pairs of significant digits starting from Most Significant position. If the two digits are equal then we check the digits at lower significant position. This comparison continues till a pair of unequal digits is reached. If corresponding digit of A is 1 and that of B is 0, then A>B and vice versa. Truth Table of Comparator:Input Lines A B 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 11 01 11 10 11 11 Output Lines A=B A>B A<B 1 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0
1

A and B are 2 bit numbers which can be applied through switches IL0, IL1, IL2, IL3. Output can be checked on OL0, OL1, and OL2.

Steps to implement the 2 Bit Comparator in the Spartan-II FPGA

Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go to FILE New projectSelect Device. Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the name comparatorDefine portsFinish. Generate the Behavioral VHDL Code for the Comparator. Check syntax and remove errors if present. Simulate the design using Modelsim. Highlight Comparator_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right click Click on new sourceClick on test bench waveformGive file nameSelect entityFinishGive inputs Click on simulate behavioral model see the output. Synthesize the design using XST. Highlight Comparator.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can view the error through the console window otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-II 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Double click on Configure Device to download the bit stream. Apply input through DIP Switches (IL0 to IL3) and output is displayed on LEDs.

Step 7:

Step 8: Step 9:

Step 10: Step 11:

Experimental Set up:-

1. Design Generalized Comparator VHDL (Ex. n bit comparator).

2. See

using Generic statements place and route report

in and

the synthesis report observe the hardware.

and

LAB 5
Implementation of binary to gray Code Converter
Introduction:The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B. A combinational circuit performs this transformation by means of logic gates. Sometimes it is convenient to use the Gray code to represent the digital data when it is converted from analog data. The advantage of the Gray code over binary numbers is that only one bit in the code group changes when going from one number to the next. The gray code is used in applications where the normal sequence of binary numbers may produce an error or ambiguity during the transition from one number to the next. In this lab, you will learn how to implement a Binary to gray Code Converter using Xilinx ISE Tool. Write the functionality in the Xilinx project navigator. Run a functional HDL simulation. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying inputs and verify the outputs.

Objectives:After completing this lab, you will be able to implement the binary to gray code converter in FPGA and verify it on Mechatronics make Spartan-II Protoboard.

Design Description:After preparing K maps for all four outputs, simplified equations are G3 = B3. G2 = B2 xor B3. G1 = B1 xor B2. G0 = B0 xor B1.

Truth Table for Binary to Gray Code :B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Binary Inputs B2 B1 B0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

Outputs G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

Steps to implement the Binary to Gray code converter

Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go to FILE New projectSelect Device. Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the name bintograyDefine portsFinish. Generate the Behavioral VHDL Code for the Bintogray. Check syntax and remove errors if present. Simulate the design using Modelsim. Highlight bintogray_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right click Click on new sourceClick on test bench waveformGive file nameSelect entityFinishGive inputs Click on simulate behavioral model see the output. Synthesize the design using XST. Highlight bintogray.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can view the error through the console window otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-II 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Double click on Configure Device to download the bit stream.

Step 7:

Step 8: Step 9:

Step 10:

Step 11

Apply Binary inputs (B3, B2, B1, B0) through DIP Switches (IL0, IL1, IL2, IL3) and 4 bit Gray Code outputs are observed on Output LEDs (OL0 TO OL3)

Experimental Set up:-

Conclusion:Design of Binary to Gray code converter is implemented in Spartan-II Protoboard and is verified according to the truth Table.

1. Design a gray to binary converter and write the VHDL code to implement it in FPGA. 2. Design controllable Binary to Gray/Gray to Binary converter. 3. List the applications wherein gray code is used.

LAB 6
Implementation of T Flip Flop
Introduction:The T flip-flop is a single input version of the JK flip-flop. It is obtained from the JK flip-flop when both the inputs are tied together. The designation T comes from the ability of the flip flop to toggle or complement, its state. Regardless of the present state, the flip-flop complements its output when the clock pulse occurs while input T=1. The characteristic table and characteristic equation show that when T=0, Q (t+1)=Q, that is, the next state is the same as the present state and no change occurs. When T=1, then Q (t+1)=Q, and the state of the flip-flop is complemented. In this lab, you will learn how to implement a T Flip Flop using Xilinx ISE Tool. Write the functionality in the Xilinx project navigator. Run a functional HDL simulation. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying inputs and verify the outputs.

Objectives:After completing this lab, you will be able to implement the T Flip Flop in FPGA and verify it on Mechatronics make Spartan-II Protoboard.

Design Description:Here T and CLK are the input signals and Q is the output signal.

Truth Table of T flip-flop:-

Steps to implement the T Flip Flop

Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go to FILE New projectSelect Device. Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the name TFlipFlopDefine portsFinish. Generate the Behavioral VHDL Code for the T Flip Flop. Check syntax and remove errors if present. Simulate the design using Modelsim. Highlight TflipFlop_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right click Click on new sourceClick on test bench waveformGive file nameSelect entityFinishGive inputs Click on simulate behavioral model see the outp ut. Synthesize the design using XST.
1

Step 7:

Step 8: Step 9:

Step 10: Step 11:

Highlight TFLipFlop.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can view the error through the console window otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-II 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Double click on Configure Device to download the bit stream. Apply input through DIP Switches (IL0) and output is displayed on LEDs.

Experimental Set up:-

Conclusion:Design of T Flip Flop is implemented in Spartan-II Protoboard and is verified according to the truth Table.

1. Design JK, D and SR flip-flop to implement it in FPGA. 2. Design 3-Bit synchronous counter using component Instantiation (D-Flip Flop/ T Flip Flop) 3. Design 8-bit addressable latch. 4. Give the difference between a latch and a flipflop.

LAB 7
Implementation of JK Flip Flop
Introduction:In this lab, you will learn how to implement a J K Flip Flop using Xilinx ISE Tool. Write the functionality in the Xilinx project navigator. Run a functional HDL simulation. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying inputs and verify the outputs.

Objectives:After completing this lab, you will be able to implement the J K Flip Flop in FPGA and verify it on Mechatronics make Spartan-II Protoboard.

Steps to implement the JK Flip Flop

Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go to FILE New projectSelect Device. Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the name JK FlipFlopDefine portsFinish. Generate the Behavioral VHDL Code for the T Flip Flop. Check syntax and remove errors if present. Simulate the design using Modelsim. Highlight J K flipFlop_tb.vhd file in the Sources in Project window. To run the Functional Simulation, Click on the symbol of FPGA device and then right click Click on new sourceClick on test bench waveformGive file nameSelect entityFinishGive inputs Click on simulate behavioral model see the output. Synthesize the design using XST. Highlight JK FLipFlop.vhd file in the Sources in Project window. To run the synthesis, right-click on Synthesize, and choose the Run option, or doubleclick on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can view the error through the console window otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan-II 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Double click on Configure Device to download the bit stream.
1

Step 7:

Step 8: Step 9:

Step 10:

Step 11:

Apply input through DIP Switches (IL0) and output is displayed on LEDs.

Experimental Set up:-

Conclusion:Design of JK Flip Flop is implemented in Spartan-II Protoboard and is verified according to the truth Table.

1. Design D and SR flip-flop to implement it in FPGA. 2. Design 3-Bit synchronous counter using component Instantiation (D-Flip Flop/ T Flip Flop) 3. Design 8-bit addressable latch. 4. Give the difference between a latch and a flipflop.

LAB 8
Scrolling of data on seven-segment display using keyboard.
Introduction:In this lab we will learn how to interface keyboard, seven-segment display and Input Output LEDs to FPGA using Xilinx ISE Tool. Write the functionality in Xilinx Project Navigator, synthesize the design with XST, and take the synthesized design through the Xilinx implementation tools. Download the bit stream file into Spartan-II kit and see the scrolling display using keyboard.

Objective:After completing this lab, you will be able to Use the keyboard, Input / Output LEDs to perform various functions that can be implemented using FPGA. Observe the output on the display / LEDs.

Procedure:Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Start the Xilinx Project Navigator by using the desktop shortcut or by using theStart Programs Xilinx ISE Project Navigator In the Project Navigator window go on FILE New projectSelect Device. Click on symbol of FPGA device and then right click Click on new source VHDL module and give name keydis_scrollDefine portsFinish. Generate the Behavioral VHDL Code for the scrolling display. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight keydis_scroll.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or doubleclick on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan2 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream. Apply input through SW1, SW2, SW3 & SW4 switches. Observe input/output LEDs. LEDs should glow with proper brightness. Observe the scrolling of hexadecimal numbers by pressing respective keys.
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Experimental Set up:-

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Write a code for up down counter and display the result on a. Output LEDs. b. Seven segment display. Design a circuit that will increment the count from 1 to F only when Key1 is pressed. Ex Press Key 1 : 0001 on Output LEDs. Press Key 1 : 0010 on Output LEDs and so on. Implement Q2. to display results on any one of the seven segments. This lab is for common anode display. What will be the change if you use a common cathode display?

LAB 9
Design of 4-bit Arithmetic Logic Unit
Introduction:In this lab, Design of 4 bit Arithmetic and Logic Unit can be verified / implemented in the FPGA using the Xilinx ISE Tool. The Arithmetic Logic Unit is the heart of the microprocessor. It is used to perform certain arithmetic operations, such as addition, subtraction etc. and logical operations such as AND, OR, EX-OR, etc. Accumulator Register - For arithmetic operations, such as addition, subtraction, etc. and logical operations, such as AND, OR, EX-OR etc, one of the operands is in the accumulator. The result of the operations is also stored in the accumulator.

Objective:After completing this lab, you will be able to Observe the logical and arithmetic operation output. Implement and verify the design using the Mechatronics Make VLSI protoboard.

Design Description:Below given is the block diagram of 4-bit Arithmetic Logic Unit.

It has four inputs (A, B, Opcode and Enable) and a single output (Out). A and B: 4 bit Binary Data inputs. Opcode: 4 Bit Opcode used to select the operation Enable: ALU should pass the result to the output bus when enable line is High, and Tri-state the output bus when the Enable line is Low. ALU should use combinational logic to calculate an output based on the four-bit Opcode input. ALU should decode the 4 Bit Opcode according to the table given below ALU Opcode ALU Operation A AND 0001 A+B A OR 0010 AB A NAND 0011 A Complement A XOR 0100 A*B A and B operand can be applied through input switches. Output can be observed on 7 segment Display. Operand A (IL0 to IL3) Operand B (IL4 to IL7) Opcode can be applied through (IL8 to IL11)

Addition When Opcode is 0001 then Addition is performed. Output of addition as well as the carry generated can be displayed on output LEDs. Subtraction When Opcode is 0010 then Binary subtraction is performed. Output of subtraction as well as the borrow can be displayed on Output LEDs If operand A is less than operand B (A < B) answer of subtraction is Answer (A - B) = - (2s complement of final answer) Multiplication Multiplication is done by normal shift & adds method.

Procedure:Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go on FILE New projectSelect Device. Click on symbol of FPGA device and then right click Click on new source VHDL module and give name ALU_checkDefine portsFinish. Generate the Behavioral VHDL Code for the scrolling display. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight ALU_check.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run Option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan2 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream Apply operand A, B & Opcode control signal through input switches. Observe output of Arithmetic & Logical operation on 7-segment display.

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Experimental Set up:-

Conclusion:Design of Arithmetic & logic Unit is implemented in FPGA and is verified according to the truth Table.

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Design a 6-bit ALU and verify it on the Mechatronics make Protoboard. Whether latches are inferred for this code? If yes, give the number of latches inferred? What will happen if following change is done in the UCF net dis1<0> loc = p114; net dis1<1> loc = p120;

LAB 10
Generate Ramp waveform using DAC.
Introduction:Analog signals represent real physical parameters with accuracy, but it is difficult to process or store them. It is necessary to translate an Analog signal into a digital signal. Similarly, a digital signal needs to be translated into an analog signal to represent a physical quantity. Quite often it is also necessary to decode any digital signal, the most obvious method is to use D/A converter for each signal. Therefore it is necessary to study the behaviour of DAC. For that waveform generation using DAC is done. Various waveforms such as square, sine, triangular, ramp etc. can be generated. In this lab ramp waveform is being generated. For that you will design a counter .This will help you to understand behavior of DAC & interfacing of DAC with FPGA to generate waveforms of different amplitude and frequency. This lab is conducted using the Xilinx Tool. Write the functionality in the Xilinx project navigator. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file. Check the performance of your design by applying counter input and verify the DAC output. DAC:- Digital to analog conversion involves translation of digital signal into equivalent analog signal. Applications of DACs include digital voltmeters, peak detectors, panel meters, programmable gain and attenuation, and stepping motor drive. Specifications of DAC AD7541: DAC type Monolithic Multiplying DAC structure. Resolution - 12 bits Conversion time - 100 ns Settling time 600 nSec Output Range - 0 to 5 Volts, Single ended (Unipolar) The two important aspects of the D/A converter are the Resolution & Accuracy of the conversion. ACCURACY:-Accuracy is a measure of how close the actual output voltage is to the theoretical output voltage. RESOLUTION:-Resolution is the smallest increment in output voltage and is determined by the LSB. Figure shows a block diagram of a 3-bit DAC and digital input vs analog output

Objective:After completing this lab you will be able to Perform the basic design flow for generating Counter It will help you to understand the behavior of a DAC it should show a proper RAMP signal at the output. Synthesize a design using Xilinx Tool. Implement a design using the Xilinx implementation tools.

Design Description:You can design a counter, which will give you a ramp waveform of Amplitude: 5V at the output of DAC. Hence a counter, that is applied as an input to get equivalent analog (ramp) signal at the output. If the full scale Analog voltage is 5 V, the smallest unit or the LSB is equivalent to 1/2n of 5 V. This is defined as resolution. In this example, DAC is 12 bit so that (5V/212) Note:- Full scale voltage is 5V For 5 V, LSB = 5/212 MSB= full scale = 2.5V Full scale output =(Full scale Value(1 LSB)) 12 = 5V-(5V/2 ). ------For AD7541 = 4.988V.

Procedure:Step 1: Step 2: Step 3: Start the Xilinx Project Navigator by using the desktop shortcut or by using theStart Programs Xilinx ISE Project Navigator In the Project Navigator window go on FILE New projectSelect Device. Click on symbol of FPGA device and then right click Click on new source VHDL module and give name dac_cntrDefine portsFinish. Generate the Behavioral VHDL Code for the counter. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight dac_cntr.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan2 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design.
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Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream. Connect the CRO probe to the DAC Out terminal to observe Ramp waveform as shown in figure below. Thus the digital input applied (counter) is converted into an analog ramp waveform.

Experimental Set up:-

Conclusion: You should now know the basic design flow for taking VHDL through the design process. You have: Realized some challenges in writing the VHDL counter. Run a piece of VHDL code through simulation. Run synthesis using XST. Run a synthesized design through the Xilinx implementation tools. After downloading check output of DAC on output analog channel.

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What is the Implementation Result See the Place and Route report file and fill in the information below a Number of slices: b Number of global buffers (BUFGMUXs): c Number of IOBs:

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Open the Post Place and Route Timing report and fill in the information. a Maximum clock frequency: Generate square and triangular wave. (Hint: Change the counter direction waveform) Design counter which will give Ramp output waveform of amplitude 2.5V. (Hint Refer graph of digital input Vs analog output and modify the counter. Modify the design to change the frequency of Ramp wave) What will be the change in the functionality if we want an inverted ramp at the output? How will you change the step size? What will happen if the time scale is changed? Draw the waveform and write down the observations for two different time scales. Write a code to generate sine triangular wave at the output different values of frequency in mind the specifications of wave, square wave and of the DAC. Try for and amplitude keeping DAC.

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How 4MHz clock frequency can be divided to see counter response on LEDs.If clock is applied directly what would you observe? Define Resolution Time & Settling Time.

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LAB 11
Implementation of Stepper Motor Controller
Introduction:The stepper motor is an electrical motor, which converts digital electric input into a rotary motion. Stepper Motor is the one that revolves through a fixed angle for each pulse applied to the logic sequences. By controlling pulse rate stepper motor speed can be controlled. Stepper Motor is also called as a Single Stack Variable Reluctance Motor. If the switching is carried out in a sequence, the rotor will rotate with stepped motion. The unipolar stepper motor, both permanent magnet and hybrid stepping motors with 5 or 6 wires has two coils, simple lengths of wound wire. Each coil has a centre tap - a wire coming out from the coil that is midway in length between its two terminals.Because of the long length of the wound wire, it has a significant resistance (and inductance). You can identify the center tap by measuring resistance with a suitable ohm-meter. The resistance from a terminal to the center tap is half the resistance from the two terminals of a coil. As shown in the figure, the current flowing from the center tap of winding 1 to terminal A1 causes the top stator pole to be a north pole while the bottom stator pole is a south pole. This attracts the rotor into the position shown. If the power to winding 1 is removed and winding 2 is energised, the rotor will turn 30 degrees, or one step. The motor cross section shown in Figure is of a 30 degree per step permanent magnet or hybrid motor. Motor winding number 1 is distributed between the top and bottom stator pole, while motor winding number 2 is distributed between the left and right motor poles. The rotor is a permanent magnet with 6 poles, 3 south and 3 north, arranged around its circumference.

The switching process can also control the average speed. In this lab, you are shown one way of implementing a Stepper Motor Controller using the Spartan-II protoboard. Write the functionality for stepper Motor Controller in the Xilinx project navigator. Synthesize your design with XST. Take the synthesized design through the Xilinx implementation tools. Download the bit stream file.

Objective:After completing this lab, you will be able to Implement a Stepper Motor Controller in an FPGA and verify it on Mechatronics make protoboard. Verify & change speed of Stepper Motor by varying input frequency. Verify & change the direction of rotation of Motor. Use Spartan-II protoboard for implementation of various Experiments. Initialize and test Spartan-II protoboard before using for your application.

Design Description:The design example in this lab is stepper motor controller that is implemented in FPGA. Stepper Motor speed & Direction of rotation is programmable with the use of DIP switches.

To rotate the motor continuously, we just apply power to the two windings in sequence. Assuming positive logic, where a 1 means turning on the current through a motor winding, the following two control sequences will spin the motor. Step A1 Coil B1 Coil A2 Coil B2 Coil 1 1 0 0 0 2 0 1 0 0 3 0 0 1 0 4 0 0 0 1 1 1 0 0 0 The sequence above produces the smoothest movement and consumes least power. Step A1 Coil B1 Coil A2 Coil B2 Coil 1 1 1 0 0 2 0 1 1 0 3 0 0 1 1 4 1 0 0 1 1 1 1 0 0 This sequence uses more power and but produes greater torque. The step positions produced by the two sequences above are not the same; as a result, combining the two sequences allows half stepping, with the motor stopping alternately at the positions indicated by one or the other sequence. The combined sequence is as follows. Step 1 2 3 4 5 6 7 8 1 Specifications of motor Voltage Rating 12 V DC Step Angle 1.80. Steps/Revolution-200 A1 Coil 1 1 0 0 0 0 0 1 1 B1 Coil 0 1 1 1 0 0 0 0 0 A2 Coil 0 0 0 1 1 1 0 0 0 B2 Coil 0 0 0 0 0 1 1 1 0

Procedure:Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator In the Project Navigator window go on FILE New projectSelect Device. Click on symbol of FPGA device and then right click Click on new source VHDL module and give name stepper_motor_hsDefine portsFinish. Generate the Behavioral VHDL Code for the stepper motor controller. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight stepper_motor_test.vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK. If there are any errors, you can View Synthesis Report by expanding Synthesis, rightclick and choose the View option, otherwise continue on to the next step. Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan2 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream. Connect stepper motor to the protoboard as shown below.

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the DIP switch IL0 to change the direction of rotation. clockwise rotation : IL0 = 0. anticlockwise rotation : IL0 = 1. the DIP switches IL1 and IL2 to change the speed of motor.

Experimental Set up:-

Conclusion: Thus stepper motor is implemented in FPGA for different speeds and the direction of the motor is changed and verified.

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What is the hardware created due to the functionality written? Open the Place and Route report and fill in the information. Number of slices consumed: Number of IOBs:_ Number of GBUFs:_