Differential Amplifiers 10

1
Differential Amplifiers
1. General Considerations
2. Bipolar Differential Pair
3. MOS Differential Pair
4. Cascode Differential Amplifiers
5. Offset Voltage
6. Common-Mode Rejection
7. Distortion in Differential Pairs
8. Differential Pair with Active Load
Francisco Duque
E.I.I., UEx
2012-2013

2
Linear
System
Linearity principle
) (
1
t v
) (
2
t v
) ( ) (
2
t v k t v
o
=
) (
1
t v a
) (
2
t v b
) ( ) (
1
t v k t v
o
= ) ( ) (
1
t v a k t v
o
=
) ( ) (
2
t v b k t v
o
=
) ( ) (
2 1
t v b t v a +
| | ) ( ) ( ) (
2 1
t v b t v a k t v
o
+ =
Linear
System
Linear
System
Linear
System
Linear
System

3
Two-signals representation: CM and DM components
2
) ( ) (
) (
2 1
t v t v
t v
cm
+
=
) ( ) ( ) (
2 1
t v t v t v
dm
=
2
) (
) ( ) (
1
t v
t v t v
dm
cm
+ =
2
) (
) ( ) (
2
t v
t v t v
dm
cm
=
) (
2 ,
t v
i
) (
1 ,
t v
i
) (
1 ,
t v
o
) (
2 ,
t v
o
) (
,
t v
dm i
) (
,
t v
cm i
) (
,
t v
cm o
) (
,
t v
dm o
The response of any linear system with two input signals
can be described in terms of its response to CM input
signals (common-mode response) and its response to DM
input signals (differential response).
Linear
System
Linear
System

4
An audio amplifier is constructed above that takes on a
rectified AC voltage as its supply and amplifies an audio
signal from a microphone.
Audio amplifier example to understand the need
for differential circuits

5
(1) Humming Noise in Audio Amplifier Example
However, V
CC
contains a ripple from rectification that leaks
to the output and is perceived as a humming noise by the
user. V
out
is measured respect to ground and differs by R
C
I
C

from V
CC
.
C C CC out
I R V V =

6
(1) Supply Ripple Rejection
Now V
out
is not referenced to ground. Instead, is measured
respect to another point that itself experiences the same
supply ripple.
Since both node X and Y contain the ripple, their difference
will be free of ripple.

in v Y X
r Y
r in v X
v A v v
v v
v v A v
=
=
+ =
Perfect symmetrical circuit
(Q
1
=Q
2
and R
C1
=R
C2
).

7
(1) Ripple-Free Differential Output
Since the signal is taken as a difference between two nodes,
an amplifier A
1
that senses differential signals is needed.

8
(1) Common Inputs to Differential Amplifier
Signals cannot be applied in phase to the inputs of a differential
amplifier, since the outputs will also be in phase, producing
zero differential output.
0 =
+ =
+ =
Y X
r in v Y
r in v X
v v
v v A v
v v A v

9
(1) Differential Inputs to Differential Amplifier
When the inputs are applied differentially, the outputs are
180 out of phase; enhancing each other when sensed
differentially.
Of course, all CM signals still being removed.
in v Y X
r in v Y
r in v X
v A v v
v v A v
v v A v
2 =
+ =
+ =

10
(1) Differential Signals
A pair of differential signals can be generated, among other
ways, by a transformer.
Differential (DM) signals have the property that they share
the same average value to ground and are equal in
magnitude but opposite in phase.

11
(1) Single-ended vs Differential Signals
Single-ended signals (referenced to ground)
Differential (balanced) signals
CM
CM
V t V V
V t V V
+ =
+ =
e
e
si n
si n
0 2
0 1

12
(1) Differential Pair
With the addition of a tail current (I
EE
or I
SS
), the circuits
above operate as an elegant, yet robust differential pair.
Ideally, differential pairs are perfectly symmetric structures.
Bipolar differential pair
(Q
1
=Q
2
and R
C1
=R
C2
)
MOS differential pair
(M
1
=M
2
and R
D1
=R
D2
)

13
2. Bipolar Differential Pair
2
2
2 1
2 1
EE
C CC Y X
EE
C C
BE BE
I
R V V V
I
I I
V V
= =
= =
=
Q
1
and Q
2
operate in the active region
Qualitative Analysis: Common-Mode Rejection
If the circuit is perfectly symmetric (matched) there is not
response (differential output signal) to any common-mode
signal (input signal, supply noise, etc.).
CM
EE
C CC
V
I
R V >
2

14
(2) Common-Mode Rejection and Common-Mode
Voltage Range
Due to the fixed tail current source (ideal), the input common-
mode value can vary without changing the output common-
mode value. That is, the circuit rejects input CM variations.
To avoid saturation (Q
1
and Q
2
), the collector voltages must not
fall below the base voltages

CM
EE
C CC
V
I
R V >
2

15
(2) Differential Response (I)
CC Y
EE C CC X
C
EE C
V V
I R V V
I
I I
=
=
=
=
0
2
1
Response to a large positive input difference
EE C C
I I I = +
2 1

16
(2) Differential Response (II)
CC X
EE C CC Y
C
EE C
V V
I R V V
I
I I
=
=
=
=
0
1
2
Response to a large negative input difference
EE C C
I I I = +
2 1

17
(2) Differential Pair Characteristics
None-zero differential input produces variations in output
currents and voltages, whereas common-mode input
produces no variations.
2
EE
C CC
I
R V is called the output CM level.


18
(2) Small-Signal Analysis
Since the input (base) to Q
1
and Q
2
rises and falls by the same
amount, and their emitters are tied together, the rise in I
C1
has the
same magnitude as the fall in I
C2
.
I
I
I
I
I
I
EE
C
EE
C
A =
A + =
2
2
2
1
Response to small input differences (qualitatively
analysis)

19
For small changes at inputs, the g
m
s are the same, and the
respective increase and decrease of I
C1
and I
C2
are the same,
node P must stay constant to accommodate these changes.
Therefore, node P can be viewed as AC ground node.
V g I
V g I
V
m C
m C
P
A = A
A = A
= A
2
1
0
AC ground

20
(2) Small-Signal Differential Gain
Since the output changes by -2g
m
AVR
C
and input by 2AV, the small
signal gain is g
m
R
C
, similar to that of the CE stage. However, to
obtain same gain as the CE stage, power dissipation is doubled.
C m
C m
in
out
v
R g
V
R V g
V
V
A =
A
A
=
A
A
=
2
2

21
(2) Large Signal Analysis (I)
T
in in
EE
C
T
in in
T
in in
EE
C
V
V V
I
I
V
V V
V
V V
I
I
2 1
2
2 1
2 1
1
exp 1
exp 1
exp
+
=
=
EE C C
C
C
T in in
I I I
I
I
V V V
= +
=
2 1
2
1
2 1
l n
|
|
.
|
\
|
=
T
BE
S C
V
V
I I exp

22
(2) Large Signal Analysis (II)
T
in in
EE C
out out
V
V V
I R
V V
2
tanh
2 1
2 1

=
Input/Output Characteristics
Linear Region
(almost)

23
(2) Linear/Nonlinear Regions
The left column operates in linear region, whereas the right column
operates in nonlinear region.
EE C CC
I R V
CC
V
( ) 2
EE C CC
I R V

24

25
(2) Equivalent Half Circuit
Since V
P
is grounded, we can treat the differential pair as two CE
half circuits, with its gain equal to one half circuits single-ended
gain.
C m
in in
out out
R g
v v
v v
=
2 1
2 1

26
(2) Example: Intrinsic Differential Gain
O m
in in
out out
r g
v v
v v
=
2 1
2 1
The intrinsic gain of any circuit or device is the theoretical
maximum gain that it can provide. This is achieved when the load
has an infinite resistance (ideal current source).

27
(2) Extension of AC Ground Concept
It can be shown that if R
1
= R
2
, and points A and B go up and
down by the same amount respectively, V
X
does not move.
By extension, any node in the axis of symmetry of a perfectly
matched circuit is an AC Ground Node.
0
2 1
= A =
X
V R R

28
(2) Half Circuit (Example I)
( )
1 3 1 1
|| || R r r g A
O O m v
=
Equivalent half circuit
Application of the concept of AC ground

29
(2) Half Circuit (Example II)
( )
1 3 1 1
|| || R r r g A
O O m v
=

30
(2) Half Circuit (Example III)
m
E
C
v
g
R
R
A
1
+
=

31
(2) Half Circuit (Example IV)
m
E
C
v
g
R
R
A
1
2
+
=

32
3. MOS Differential Pair
Similar to its bipolar counterpart, MOS differential pair produces
zero differential output as V
CM
changes.
2
SS
D DD Y X
I
R V V V = =
Qualitative Analysis: Common-Mode Rejection

33
(3) Equilibrium Overdrive Voltage
The equilibrium overdrive voltage is defined as the overdrive
voltage (V
OV
= V
GS
V
TH
) seen by M
1
and M
2
when both of them
carry a current of I
SS
/2.
( )
|
SS
equil
TH GS
I
V V =
L
W
C
ox n
| =
( )
2
2
TH GS D
V V I =
|

34
(3) Minimum Common-Mode Output Voltage
In order to maintain M
1
and M
2
in saturation, the common-
mode output voltage cannot fall below the value above.
This value usually limits voltage gain.
TH CM
SS
D DD
V V
I
R V >
2

35
(3) Differential Response

36
(3) Small-Signal Response
Similar to its bipolar counterpart, the MOS differential pair
exhibits the same AC ground node (P) and small signal gain.
D m v
P
R g A
V
=
= A 0

37
(3) MOS Differential Pairs Large-Signal Response (I)
( )
SS D D
in in D D
I I I
V V I I
= +
=
2 1
2 1 , 2 1
2
|
( )
( )
( )
( )
2 , 1 , ,
2
2
, ,
2
2
2
, ,
1
2 /
1
2 2
2 /
1
2 2
in in dm i
equil
TH GS
dm i dm i
SS
SS
D
equil
TH GS
dm i dm i
SS
SS
D
V V V
V V
V V
I
I
I
V V
V V
I
I
I
=

=
+ =
|
|

38
(3) MOS Differential Pairs Large-Signal Response
(II)
( )
( )
2
2
,
, 2 1
2 /
1
equil
TH GS
dm i
dm i SS D D
V V
V
V I I I
= |

39
(3) Maximum Differential Input Voltage (III)
There exists a finite differential input voltage that completely
steers the tail current I
SS
from one transistor to the other. This
value is known as the maximum differential input voltage.
( )
equil
TH GS in in dm i
V V V V V = = 2
max
2 1
max
,
( )
equil
TH GS dm i
V V V > 2
,
) ; 0 (

2 1 SS D D
I I I
ZONE RATE SLEW
= =


40
(3) Contrast Between MOS and Bipolar Differential
Pairs
In a MOS differential pair, there exists a finite differential
input voltage to completely switch the current from one
transistor to the other, whereas, in a bipolar pair that
voltage is infinite.
MOS Bipolar

41
(3) The effects of Doubling the Tail Current
Since I
SS
is doubled and W/L is unchanged, the equilibrium
overdrive voltage for each transistor must increase by
to accommodate this change, thus AV
in,max
increases by
as well. Moreover, since I
SS
is doubled, the differential
output swing will double.

2
2

42
(3) The Effects of Doubling W/L
Since W/L is doubled and the tail current remains unchanged,
the equilibrium overdrive voltage will be lowered by

to
accommodate this change, thus AV
in,max
will be lowered by
as well. Moreover, the differential output swing will remain
unchanged since neither I
SS
nor R
D
has changed.
2
2

43
(3) Small-Signal Analysis of MOS Differential Pair
When the V
i,dm
is small compared to (V
GS
-V
TH
)
equil
=(I
SS
/|)
1/2
, the
output differential current is linearly proportional to it, and
small-signal model can be applied.
( )
( )
dm i SS
equil
TH GS
dm i
dm i SS D D
V I
V V
V
V I I I
,
2
2
,
, 2 1
2 /
1 ~
= | |

44
(3) AC Ground and Half Circuit
Applying the same analysis as the bipolar case, we will
arrive at the same conclusion that node P will not move for
small input signals and the concept of half circuit can be
used to calculate the gain.
C m v
P
R g A
V
=
= A 0

45
(3) MOS Differential Pair Half Circuit Example I
|
|
.
|
\
|
=
=
1 3
3
1
|| ||
1
0
O O
m
m v
r r
g
g A


46
(3) MOS Differential Pair Half Circuit Example II
3
1
0
m
m
v
g
g
A =
=

47
(3) MOS Differential Pair Half Circuit Example III
m SS
DD
v
g R
R
A
1 2
2
0
+
=
=

48
4. Cascode Differential Pair
( ) | |
1 3 3 1 3 1
||
O O O m m v
r r r r g g A + =
t
Bipolar Case

49
(4) Bipolar Telescopic Cascode
( ) | | | | ) || ( || ||
5 7 5 5 3 1 3 3 1 t t
r r r g r r r g g A
O O m O O m m v
~

50
(4) Example: Bipolar Telescopic Parasitic Resistance
| |
op O O m m v
O O m O op
R r r r g g A
R
r r
R
r r g r R
|| ) || (
2
|| ||
2
|| || 1
3 1 3 3 1
1
5 7
1
5 7 5 5
t
t t
=
+
(
|
.
|
\
|
+ =

51
(4) MOS Cascode Differential Pair
1 3 3 1 O m O m v
r g r g A ~

52
(4) MOS Telescopic Cascode
( ) | | ) ||(
7 5 5 1 3 3 1 O O m O O m m v
r r g r r g g A ~

53
(4) Example: MOS Telescopic Parasitic Resistance
( )
) || (
] 1 [ ||
1 3 3 1
7 7 5 1 5
O m O op m v
O O m O op
r g r R g A
r r g R r R
~
+ + =

54
5. Offset Voltage
Offset voltage is due to mismatches between components or
devices that ideally should be identical.
0
2 1
2 1
2 1
= =
=
= =
out out out
in in
D D D
V V V
V V
R R R
R
I
V V V
V V
R
R R
R
R R
SS
out out out
in in
D
D D
D
D D
A = =
=
A
=
A
+ =
2
2
2
2 1
2 1
2
1
Output offset voltage

55
(5) Input referred offset voltage
Input referred offset voltage (V
OS
) is the output offset voltage
divided by the small-signal gain.
V
OS
means the dc input differential voltage necessary to
compensate all the circuit mismatches and therefore, fix V
out
= 0.
D
D SS
D m
D
SS
v
out out
OS
R
R I
R g
R
I
A
V V
V
A
=
A
=
=
|
1
2 1 2
0
2 , 1 , .
= = =
out out out OS dm in
V V V V V

56
6. Common-Mode Rejection
If the tail current source is not ideal, then when a input CM
voltage is applied, the currents in Q
1
and Q
2
and hence output
CM voltage, will change.
m EE
C
CM in
CM out
g R
R
V
V
2 / 1
2 /
,
,
+
=
A
A
Effect of Finite Tail Impedance

57
(6) Input CM Noise with Ideal and Non-Ideal Tail
Current
As it can be seen, the differential output voltages for both cases
are the same. So, for small input CM noise the differential pair is
not affected.
=
EE
R =
EE
R

58
(6) CM to DM Conversion, A
CM-DM

If finite tail impedance and asymmetry are both present, then
the differential output signal will contain a portion of input
common-mode signal.
SS m
D
CM
out
R g
R
V
V
+
A
=
A
A
2 / 1

59
(6) Common-Mode Rejection Ratio (CMRR)
CMRR defines the ratio of wanted amplified differential input
signal to unwanted converted input common-mode noise that
appears at the output.
DM CM
DM
A
A
CMRR
=

60
General considerations for harmonic distortion
Transfer characteristic (input vs output) is not a straight line in
circuits with active devices.
Both, small-signal and large-signal, have nonlinearity problems.
7. Distortion in Differential Pairs
Nonlinear
System
) (t v
in
) (t v
out
2
2 1 in in out
v G v G v + =
Let us assume:
where G
1
and G
2
are constant.
( ) ( ) ( )
( ) ( ) t B t B B
t V G t V G v t V v
out in
1 2 1 1 0
1
2 2
1 2 1 1 1 1 1
2 cos cos
cos cos cos
e e
e e e
+ + =
= + = =
2
nd
harmonic distortion is introduced:
1
2
2
B
B
HD =
( ) o o 2 cos 1
2
1
cos
2
+ =

61
(7) High order harmonic distortion
Nonlinear
System
) (t v
in
) (t v
out
( )
( ) ( ) ( ) + + + + =
=
+ + + =
t B t B t B B v
t V v
v G v G v G v
out
in
in in in out
1 3 1 2 1 1 0
1 1
3
3
2
2 1
3 cos 2 cos cos
cos
e e e
e
- n
th
harmonic distortion:
1
B
B
HD
n
n
=
- Power delivered at the fundamental frequency:
L
R
B
P
=
2
2
1
1
- Total power output:
( ) ( )
1
2
3
2
2
2
3
2
2
2
1
1
2
1
P HD HD
R
B B B P
L
+ + + =
+ + + =
- Total Harmonic Distortion:
+ + + =
2
3
2
2
1 HD HD THD

62
(7) Distortion in MOS Differential Pair
|
|
.
|
\
|
= =
SS
i
i SS
SS
i
i SS D D D
I
V
V I
I
V
V I I I I
4 2
1
4
1
3 2
2 1
|
|
|
|
( ) x x x x x ~ =
2
1
1
16
1
8
1
2
1
1 1
3 2 5 . 0
( ) o o o 3 cos cos 3
4
1
cos
3
+ =

63
(7) Distortion in MOS Differential Pair
(

|
|
.
|
\
|
= =
=
t
I
A
t
I
A
A I I I I
t A V
SS SS
SS D D D
i
1
3
1
3
2 1
1
3 cos
16 2
1
cos
16 2
3
cos
e
|
e
|
|
e
0
1
2
2
= =
B
B
HD
( )
2
2
1
3
3
32
1
32
1
(
(
= =
equil
TH GS SS
V V
A
I
A
B
B
HD
|
Cancellation of even harmonics is a typical performance feature
of differential circuit structures.

64
Differential to Single-ended Conversion
Many circuits require a differential to single-ended
conversion, however, the above topology is not very good.
8. Differential Pair with Active Load

65
(8) Supply Noise Corruption
The most critical drawback of this topology is supply noise
corruption, since no common-mode cancellation mechanism
exists. Also, we lose half of the signal.

66
(8) Better Alternative
This circuit topology performs differential to single-ended
conversion with no loss of gain.

67
(8) Active Load
With current mirror used as the load, the signal current
produced by the Q
1
can be replicated onto Q
4
.
This type of load is different from the conventional static
load and is known as an active load.

68
(8) Differential Pair with Active Load
The input differential pair decreases the current drawn from
R
L
by AI and the active load pushes an extra AI into R
L
by
current mirror action; these effects enhance each other.


69
(8) Active Load vs. Static Load
The load on the left responds to the input signal and
enhances the single-ended output, whereas the load on the
right does not.

70
(8) MOS Differential Pair with Active Load
Similar to its bipolar counterpart, MOS differential pair can
also use active load to enhance its single-ended output.

71
(8) Asymmetric Differential Pair
Because of the vastly different resistance magnitude at the
drains of M
1
and M
2
, the voltage swings at these two nodes
are different and therefore node P cannot be viewed as a
virtual ground.

72
(8) Thevenin Equivalent of the Input Pair
oN Thev
in in oN mN Thev
r R
v v r g v
=
=
2
) (
2 1

73
(8) Simplified Differential Pair with Active Load
) || (
2 1
OP ON mN
in in
out
r r g
v v
v
=

74
I
A
(8) Proof of V
A
<<

V
out

OP mP
out
A
r g
v
v
2
~
A m
O
out
v g
r
v
I
4
4
=

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Equivalent half circuit

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