Final Report

Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler
Chapter 1 Introduction
1.1 Introduction and Motivation
Over the last two decades, the continuous shrinking in the feature size of MOSFETs has increasingly attracted the research and development of low-power radio frequency CMOS integrated circuits. For mobile wireless communications, low-power operations are of crucial importance for the mobile units as the battery lifetime is limited by the power consumption and the low power consumption also helps to reduce the operating temperature resulting in more stable performance. For the modern transceiver architecture, a fully integrated frequency synthesizer with low power voltage-controlled oscillators (VCO) for quadrature signal generation and low power frequency dividers with multi-channel selection is always a topic of interest in research. The existing wireless standards like Bluetooth and 802.11a/b/g offer relatively high data rates at the expenses of high power consumption and high cost. The IEEE 802.15.4 standard has been specifically designed to cater for the needs of low cost, low power, low data rate and short range wireless networks. Few frequency synthesizers based on this standard have been reported in literature and the frequency synthesizer reported in has the power consumption of 2.4 mW at 1.2V power supply. Most synthesizers have not scaled down the supply voltage to reduce the power consumption of digital blocks. It is believed that power consumption of the frequency synthesizer (mainly frequency divider) can be reduced significantly by further simplifying the circuit structures, and adapting some power saving techniques to the digital blocks such as frequency dividers.
1.2
Approach
The project gives detailed analysis, specifications and design of low power fully
programmable integer-N frequency divider which a critical block of frequency synthesizers for IEEE 802.15.4. The approach of the project is as follows:
Dept of Electronics & Communication, SIT Tumkur 2012-13
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Design and Analysis of ultra-low power 2/3 TSPC prescaler A detailed analysis of power consumption and propagation speed of the dynamic logic flip-flops is carried out and an ultra-low power True-single-phase clock (TSPC) 2/3 prescaler is proposed which is verified in the design of TSPC 32/33 prescaler in 180nm CMOS technology. A low power TSPC 47/48 prescaler The design of a fully programmable 1 MHz resolution divider for the 2.4 GHz frequency synthesizer using a 32/33 prescaler, a 7-bit programmable P-counter and a 5-bit swallow S counter results in 1 MHz output with duty cycle less than 25%. In order to improve the duty cycle, a low power TSPC 47/48 prescaler is implemented without an additional flip-flop. This new design is similar to the design of 32/33 prescaler with an additional inverter.
1.3 Applications:
Frequency divider is a critical block of frequency synthesizer which has major applications in, Local oscillators for modulation and demodulation Phase locked loop (PLL) synthesizers and other counting circuits Radio receivers Mobile telephones GPS systems
1.4
Organization of the report

Chapter 1 gives an introduction about the programmable frequency dividers and its
principle in brief. Chapter 2 provides in detail the literature survey of CMOS logic family and also its electronic analysis. Chapter 3 describes steps in cadence tool to build the schematics and layouts and their verification using gpdk180 library of the EDA tool. Chapter 4 describes the implementation of the prescalers using cadence tools demonstrating the difference between the traditional and modified designs. Chapter 5 gives an exhaustive account of how the traditional prescaler is modified to obtain new designs. Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 2
Chapter 2 Literature Survey

2.1 Logic family
A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family were produced as individual components, each containing one or a few related basic logical functions, which could be used as building blocks to create systems or as so called glue to interconnect more complex integrated circuits. A logic family may also refer to a set of techniques used to implement logic within VLSI integrated circuits such as central processors, memories, or other complex functions. Packaged building block logic families which are compatible to the proposed design are CMOS (complementary metal oxide semiconductor logic) and TTL (Transistor Transistor Logic).
2.2 Comparison between TTL and CMOS logic families

TTL stands for Transistor-Transistor Logic. It is a classification of integrated circuits. The name is derived from the use of two Bipolar Junction Transistors or BJTs in the design of each logic gate. CMOS is also another classification of ICs that uses Field Effect Transistors in the design. A brief comparison between these logic families highlights the advantage of CMOS as follows:
2.2.1 Characteristics of CMOS logic family

Some important characteristics of the CMOS logic family are as given below Dissipates low power - The power dissipation is dependent on the power supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is typically 10 nW per gate [1]. Short propagation delays - Depending on the power supply, the propagation delays are usually around 25ns to 50ns.
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Rise and fall are controlled - The rise and falls are usually ramps instead of step functions, and they are 20 to 40% longer than the propagation delays. Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so high.
2.2.2 Characteristics of TTL logic family

Some important characteristics of the TTL logic family are as given below Power dissipation is usually 10 mW per gate. Propagation delays are 10 ns when driving a 15 pF/400 ohm load [2]. Voltage levels range from 0 to Vcc is typically 4.75V to 5.25V. Voltage range 0V to 0.8V creates logic level 0. Voltage range 2V to Vcc creates logic level 1.
2.2.3 Advantages of CMOS over TTL

Some important advantages of the CMOS over TTL logic family are as given below CMOS components are typically more expensive that TTL equivalents. However, CMOS technology is usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation. CMOS allows much higher density of logic functions in a single chip compared to TTL. CMOS circuits do not draw as much power as TTL circuits while at rest. CMOS requires lower current draw requires less power supply distribution, therefore causing a simpler design. Due to longer rise and fall times, the transmission of digital signals becomes simpler and less expensive with CMOS chips. CMOS components are more susceptible to damage from electrostatic discharge than TTL components.
2.3 Electronic analysis of MOSFET

The voltage applied to the gate controls the flow of electrons from the source to the drain. A positive voltage (for NMOS) or negative voltage (for PMOS) applied to the gate attracts electrons (holes) to the interface between the gate dielectric and the semiconductor. These electrons form a conducting channel called the inversion layer. No gate current is Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 4
required to maintain the inversion layer at the interface since the gate oxide blocks any carrier flow. The net result is that the applied gate voltage controls the current between drain and source.
2.3.1 Pass Characteristics of NMOS-FET

The schematic diagram of NMOS-FET (nFET) pass transistor is as shown in the Fig. 2.1. The input pulse V1 has a voltage 1.8V and the output voltage Vout is measured across the capacitive load Cout. The value of capacitor represents the total capacitance at the output node and has several contributions.
Fig.2.1. Schematic Diagram of NMOS-FET Fig.2.2 summarizes the behavior of the device when NMOS is used to pass the voltage from left to right. Applying VDD to the gate ensures that the nFET is ON and the device acts like a closed switch. If a logic 0V is applied to source of NMOS, this results in an output is applied, Vout is
voltage of Vout= 0V as shown in Fig. 2.2. if input voltage of V 1 =V DD reduced to a value Vout=VDD VTn Vout =1.8V 0.53V Vout =1.273V Dept of Electronics & Communication, SIT Tumkur 2012-13
(2.1)
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Which is less than the input voltage V 1 this is referred to as threshold voltage loss. It arises due to the fact that the minimum value of the gate-source voltage. So maintain an on state Gate to source voltage of VGSn=VTn= 0.53V. (2.2)
Fig.2.2. NMOS pass characteristic From the waveforms in Fig 2.2 it can be concluded that, NMOS-FET can pass strong logic 0 NMOS-FET can pass weak logic 1
2.3.2 Pass Characteristics of PMOS-FET

A pFET has opposite pass characteristics as of nFET. To examine the properties of PMOS, logic 0 is applied to Gate as shown in Fig.2.3. Fig.2.4 summarizes the behavior of the device when PMOS is used to pass the voltage from left to right. Applying logic 0 to the gate ensures that the pFET is ON and the device acts like a closed switch. If an input voltage of V1= 1.8 V is applied to source of PMOS, this results in an output voltage of Vout= 1.8 V as desired, this is shown in Fig.2.4. Decreasing the input voltage results in that value is being transmitted to the output side.
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Fig. 2.3. Schematic diagram of pass PMOS-FET
However if input voltage of V 1 = 0 V is applied, Vout is not equal to 0 V, but Vout=V Tp = 0.619V (2.3)
This is also due to a threshold effect. In order to keep the pFET ON it requires a minimum source-gate voltage of V SGp =V Tp = 0.619V (2.4)
From the waveforms in Fig 2.4 it can be concluded that, PMOS-FET can pass strong logic 1 PMOS-FET can pass weak logic 0
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Fig. 2.4. PMOS Pass characteristic
Thus we can write following rules as a basis for our design: 1. Use pFETs to pass logic 1 voltages of V DD . 2. Use nFETs to pass logic 0 voltages of V SS = 0V. These allow us to build circuits that can pass the ideal logic voltages 0V and V DD to the output terminal.
2.4 Summary
In this chapter, with the availability of many logic families, CMOS logic was opted for the design part and implementation using Cadence.
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Chapter 3 Implementation using Cadence Tools

Cadence on virtuoso platform provides tools for designing full-custom integrated circuits which includes schematic entry, behavioral modeling and circuit simulation. Cadence enables the realization of silicon chips, system-on-chip devices, and complete systems at lower costs with high quality [2].
3.1 Design Steps using Cadence Software

1. Create Library
In command Interpreter Window (CIW) or library manager execute: File New Library Attach design library to an existing technology library and select gpdk as shown in Fig. 3.1
Fig. 3.1 creating a new library from the CIW window
2. Schematic Entry
In CIW, execute: File New cell view. In the blank schematic window add components from the respective library and set their specifications to the requirement. Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 9
Add wires to the schematic, check and save, as shown in Fig 3.2. The CIW window is checked for any errors or warnings in the schematic.
Fig. 3.2 Creation of TSPC schematic
3. Symbol creation
In the schematic window, execute: Create Cell view From Cell view. Fill in the Symbol Generation Options (which include the positions and direction of pins) appropriately, check and save, as shown in Fig 3.3.
Fig. 3.3 Creation of TSPC symbol
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4.

Test schematic
In CIW, execute: File New Cell view A blank schematic window for the test schematic design appears. Add the components using create instance. Complete the connection, check and save, as shown in Fig. 3.4. The CIW window is observed for any errors.
Fig. 3.4 Creation of TSPC test schematic
5.
State)
Simulation with spectre

In the test schematic window, execute: Launch ADEL, as shown in Fig 3.5 Choose Analysis as per requirement and set the specifications. In the simulation window, execute: Outputs To be plotted select on schematic In the simulation window, execute: simulation Net List Observe the transient plots In the simulation window, execute: Session Save State ( to save the current working
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Fig. 3.5 Simulation with spectre in ADEL environment
6.

Delay calculation
From the graph obtained after simulation, execute: Tools Calculator, which opens up the window as shown in Fig. 3.6. Select the delay function from the list of functions provided. Clear buffer and stack. Provide the two necessary signal inputs for delay calculation from the graph or the schematic window. In the same window, execute: Apply Evaluate the buffer
Fig. 3.6 Delay calculation using the in-built calculator Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 12
3.2 Design methodology

CADENCE: Electronic design automation (EDA or ECAD) is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. One of the EDA softwares is CADENCE DESIGN SYSTEM.
3.2.1 Design specifications

The bottomup design flow for a transistor-level circuit layout always starts with a set of design specifications. The specifications typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. Usually, the design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design. The basic components used, along with their specifications have been provided in Table. 3.1 Table.3.1 Design specifications of basic components used in simulation
Component
Specifications Width w = 3 um
Library
pMOS
Length l = 180nm Width w = 1.7um
gpdk 180
nMOS
Length l = 180nm Voltage V1 = 0 V
gpdk 180
Vpulse Vdc
Voltage V2 = 1.8 V Voltage Vdc = 1.8 V
analogLib analogLib
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3.2.2 Selecting P/N ratio

The circuit is designed using standard PMOS and CMOS feature size 180nm with the PMOS to NMOS ratio being 2. Static CMOS gates are a ratio less circuit family, the gates will work correctly for any ratio of PMOS sizes to NMOS sizes. However, the ratio do influence switching threshold and delay, so it is important to optimize the P/N ratio for high speed designs. Using a higher or lower P/N ratio favors rising or falling outputs, respectively. For example, with a P/N ratio of 4/1, the input does not have to fall as far as V dd/2 before the output could switch. Such a circuit is called a high skewed gate and use it on paths where the critical transition is a rising output. Similarly, a 1/1 P/N ratio could be used in a low skewed gate for critical falling outputs.
3.2.3 Creating schematic

The method for describing the transistor level or gate level design is via the schematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up the design. The resulting schematic drawings must accurately describe the main electrical properties of all components and their interconnections. Power supply and ground connections, as well as all pins for the input and output signals of the circuit. This information is crucial for generating the corresponding netlist, which is used in later stages of the design. The generation of a complete circuit schematic is therefore the first important step of the transistor-level design flow. Usually, some properties of the components (e.g. transistor dimensions) and/or the interconnections between the devices are subsequently modified as a result of iterative optimization steps. These later modifications and improvements on the circuit structure must also be accurately reflected in the most current version of the corresponding schematic. An example of a TSPC schematic has been shown in Fig. 3.7.
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Fig. 3.7 Schematic of TSPC circuit
3.2.4 Symbol creation

If a certain circuit design consists of smaller hierarchical components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. This step largely simplifies the schematic representation of the overall system. The symbol view of a circuit module is an icon that stands for the collection of all components within the module. A symbol view of the circuit is also required for some of the subsequent simulation steps, thus, the schematic capture of the circuit topology is usually followed by the creation of a symbol to represent the entire circuit. The shape of the icon to be used for the symbol may suggest the function of the module (e.g. logic gates AND, OR, NAND, NOR), but the default symbol icon is a simple rectangular box with input and output pins. Note that this icon can now be used as the building block of another module, and so on, allowing the circuit designer to create a system-level design consisting of multiple hierarchy levels.
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3.2.5 Simulation of schematic

After the transistor level description of a circuit is completed using the schematic editor, the electrical performance and the functionality of the circuit must be verified using a simulation tool. The detailed transistor level simulation of the design will be the first in depth validation of its operation; hence, it is extremely important to complete this step before proceeding with the subsequent design optimization steps. Based on simulation results, some of the device properties such as transistor width-to-length ratio are modified in order to optimize the performance. As the first step, the symbol of the component created is inserted and the inputs are provided with variable pulses to cover all combinations possible. Vdd supply is provided using Vdc = 1.8 V. the outputs are connected to output pins. Analog Design Environment (ADEL) is launched and transient analysis is chosen. This analysis is performed for a desired period with moderate accuracy. The outputs to be plotted are selected from schematic and the simulation is run for these specifications. The delay is then calculated from the response obtained.
3.2.6 Mask layout

Physical layout design is very tightly linked to overall circuit performance (area, speed and power dissipation) since the physical structure determines the transconductances of the transistors, the parasitic capacitances and resistances, and the silicon area which is used to realize a certain function. The physical (mask layout) design of CMOS logic gates is an iterative process which starts with the circuit topology and the initial sizing of the transistors.
3.2.7 Design Rule Check (DRC)

The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design.
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3.2.8 Extraction
The circuit extractor is capable of identifying the individual transistors and their interconnections on various layers, as well as the parasitic resistances and capacitances that are inevitably present between these layers. Thus, the extracted net-list can provide a very accurate estimation of the actual device dimensions and device parasitic that ultimately determine the circuit performance.
3.2.9 Layout versus Schematic check (LVS)

The design called Layout-versus-Schematic (LVS) Check will compare the original network with the one extracted from the mask layout, and prove that the two networks are indeed equivalent. The LVS step provides an additional level of confidence for the integrity of the design, and ensures that the mask layout is a correct realization of the intended circuit topology.
3.2.10 Post Layout Simulation

The electrical performance of a full-custom design can be best analyzed by performing a post-layout simulation on the extracted circuit net-list. At this point, the designer should have a complete mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no violations. The detailed (transistor-level) simulation performed using the extracted net-list will provide a clear assessment of the circuit speed, the influence of circuit parasitics
3.3
Discussion
In this chapter, the implementation details of the various designs of Prescaler using
Cadence has been discussed, clearly outlining the specifications needed for every circuit design. Care was taken to choose the P/N ratio as per the requirements, along with the other necessities. A comparison was also provided regarding the number of gates and transistors used.
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Chapter 4 Analysis of Ultra Low Power Prescaler

The prescaler is one of the most critical blocks in the synthesizer since it operates at the highest frequency and consumes a large amount of power. Thus the power reduction in the first stage of the prescaler is important in realizing a low power frequency synthesizer. A dualmodulus prescaler such as divide-by-32/33, divide-by-64/65 and divide-by-128/129
usually consists of a synchronous divide-by-2/3 or divide-by-4/5 circuit combined with several asynchronous divide-by-2 circuits.
4.1
Prescaler
The high speed dual modulus prescaler is a critical functional block in frequency
synthesizers which uses wide-band pulse swallow frequency dividers operates the prescaler at the highest frequencies and consumes more power than other circuit blocks of the frequency synthesizer. In a pulse swallow frequency divider, the prescaler has two selectable division ratios and . It is combined with programmable counters P and S as in Fig. 4.1 to .
perform a programmable division ratio of
The prescaler is a synchronous circuit which is formed by D flip-flops and additional logic gates, due to the incorporation of additional logic gates between the flip-flops to achieve the two different division ratios, the speed of the prescaler is affected and the switching power increases. Various flip-flops have been proposed to improve the operating speed of dualmodulus prescalers. The optimization of the D flip-flop in the synchronous stage is essential to increase the operating frequency and reduce the power consumption. The high speed operation of MOS transistors is limited by their low transconductance. Therefore, dynamic and sequential circuit techniques or clocked logic gates such as, true single phase clocks must be used in designing synchronous circuits to reduce circuit complexity, increase operating speed and reduce power dissipation. The state of the art CMOS prescalers have achieved
maximum operating frequencies up to 2.4 GHz using current mode logic (CML) architectures at the expense of power consumption. The fastest frequency dividers were designed at fixed division ratios.
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The power consumption and frequency of operation of TSPC and E-TSPC 2/3 prescalers are analyzed and an ultra low power TSPC 2/3 prescaler is designed. Based on this design a 32/33 prescaler and 47/48 prescaler is then implemented, which is highly suitable for high resolution fully programmable frequency synthesizers.
Fig. 4.1 Topology of the Pulse Swallow frequency divider
4.1.1 Theory of operation

Prescaler divides the input frequency by control. Program counter divides the prescaler output by Swallow counter divides the prescaler output by Start from reset, prescaler divides by After (fixed). (fixed). or based on the modulus
until swallow counter is full. .
pulses at the input, the modulus control changes to
Continues to count until program counter is full. Total pulses at the input =
4.2
Synchronous 2/3 prescaler

An DMP (dual modulus prescaler) consists of a synchronous prescaler
followed by a series of asynchronous divide-by-2 circuits and additional logic gates to control the switching between the two different division ratios. Fig. 4.2 shows the evolution of a simple 2/3 synchronous prescaler from divide-by-2 and divide-by-3 circuits.
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When control logic signal MC goes high, the output of OR gate is always equal to logic 1 and the output of AND gate is always equal to the inverted output of DFF2 (Q2) such that the prescaler operates in the divide-by-2 mode as shown in Fig. 4.2 (a)
Fig. 4.2 a) Divide-by-2 circuit b) Divide-by-3 circuit c) Divide-by- 2 or 3 circuit When control logic signal MC goes low, the output of OR gate is always equal to Q1, such that prescaler operates in the divide-by-3 mode as shown in Fig. 3.1 (b). The output of the synchronous 2/3 prescaler is given by
(4.1)
Frequency dividers designed based on digital counters cannot be implemented by standard digital circuits. These digital counters cannot be synthesized directly using register transfer level (RTL) description which relies on standard cells as high frequency of operation requires accurate design and optimization. The main building block of the frequency dividers is D type edge-triggered flip-flop which are constructed using level triggered latches. The most commonly used logic circuits for high frequency dividers is either source-coupled logic (SCL) or current-mode logic (CML) circuits. Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 20
4.2.1 Current-mode logic (CML) dividers

The CML circuit is based on the use of differential stages with current steering topology. A divide-by-2 circuit implemented using the CML logic type is shown in Fig. 4.3 along with its equivalent transistor level schematic. A CML latch consists of NMOS differential pair transistors (Mn4, Mn5) and a regenerative pair (Mn1, Mn2). The loads are PMOS transistors (Mp1, Mp2) which are always operated in the triode region. When CLK is high, Mn6 turns-on and the differential pair transistors compare the input amplitudes at gate terminals and pass the result to the output nodes. When CLK is low, Mn3 turns-on and the regenerative pair transistors hold the output. The maximum operating frequency is decided by the differential pair transistors since they decide how fast the input amplitudes are sensed and transferred to the output nodes. The CML dividers have higher speed of operation and higher power consumption compared to that of the dynamic logic dividers.
Fig. 4.3 CML divide-by-2 and gate level schematic of CML latch One of the main advantages of CML logic circuits over dynamic logic circuits is the use of the differential topology, which makes the current drained by the supply less variable. Moreover, differential circuits reject disturbances coming from the substrate and power supply due to other blocks. The current steering topology as shown in Fig. 4.3 helps in lowering the voltage head Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 21
room. However, the current of the clock transistors are not controllable which results in larger power consumption. The CML logic circuit is very sensitive to the input amplitude and also requires buffers or level shifters at the output to drive the low frequency dynamic logic counters. Since the main interest lies in the design of low power synthesizer operating below 5 GHz, dynamic logic dividers are preferred over CML logic dividers.
4.2.2 Dynamic logic dividers

The CMOS latches eliminate the static current consumption and use fewer transistors than the CML latches do. They are slow due to the positive feedback (memory element) which introduces additional delay to the switching time. The switching speed of the static circuits depends on two factors namely, the current conduction level through a MOS transistor and parasitic capacitances. Since the parasitic capacitances cannot be controlled, the switching speed is only improved by the use of new and improved process. Alternatively, the memory element formed by a positive feedback can be replaced by a charge storing capacitance, which is called as dynamic memory. The dynamic logic circuit, instead of fighting the time constant limits induced by the RC parasitics, accepts the presence of capacitances and uses them as integral parts of the circuit.
Fig. 4.4 Clocked-CMOS (C2MOS) logic latch When CLK=1, both M3 and M2 are active IN=0 (1), the node S1 charges to 1 (0). When CLK=0, the first stage goes into high-impedance state and the second stage accepts the data at node S1 and passes it to the output node. Hence the output data is same as the input data. However, the output voltage can only be maintained so long as the voltage across node S1 Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 22
Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler remains within an appropriate range. Fig. 4.4 shows a clocked-CMOS (C2MOS) logic latch. The main drawback of this topology is the requirement of complementary clock inputs for a single phase output. In an asynchronous chain, when a divide-by-2 is implemented, an additional inverter is need at the output to provide differential signals thus causing clock skew.
Fig. 4.5 Evolution of TSPC flip-flop from doubled p-C2MOS latch For this reason, domino logic circuits also a part of the dynamic logic circuit family. The original domino logic circuit requires a dual-phase clock, but a single-phase clock is developed using doubled p-C2MOS latch as shown in Fig. 4.5 which avoids the need of the dual-phase clock and clock skew problems. This architecture has higher speed and higher input sensitivity. The TSPC flip-flop has two modes of operation namely; hold mode and evaluation mode as shown in Fig. 4.6. In the hold mode (pre-charge phase), CLK=0and node S1 is precharged to a value depending on the input signal IN and node S2 is pre-charged to VDD. As transistors M7 and M8 is turned-off, output node OUT becomes floating. In the evaluation mode, CLK=1 and if the node S1 is pre-charged to VDD in the hold mode, node S2 is discharged and output node is pulled up by the transistor M7. If the node S1 is pre-charged to Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 23
0 during the hold mode, node S2 is not discharged, and output node is pulled down by the transistors M8 and M9 respectively.
Fig. 4.6 Operation of TSPC flip-flop a) hold mode b) evaluation mode A further modification of the TSPC circuit, which increases the achievable speed by a reduction of the stacked transistors, is the extended TSPC (E-TSPC) logic circuit. The E-TSPC circuit has static current, noise immunity problem which requires additional care in the design. The TSPC and E-TSPC are most suitable in the design of low power dividers for frequencies below 6 GHz applications. However, the choice between TSPC and E-TSPC circuits is very critical since the TSPC circuit has lower power consumption but operates at a lower frequency compared to that of the E-TSPC logic circuit.
4.2.3 Propagation speed analysis of TSPC and E-TSPC flip-flops

In this section, the maximum operating frequency of the TSPC and E-TSPC flip-flops are analyzed. In each stage, an E-TSPC flip-flop uses only two transistors while a TSPC flipflop uses three transistors. Of various dynamic logic CMOS circuits, TSPC and E-TSPC circuits operate with the single-phase clock to avoid clock skew problems. To compare the speed performance of TSPC and E-TSPC circuits, the first stage of both TSPC and E-TSPC circuits with their equivalent RC models are analyzed as shown in Fig. 4.7.
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(a) TSPC
(b) E-TSPC
Fig. 4.7 First stage and equivalent RC model of (a) TSPC (b) E-TSPC flip-flops
The charging and discharging time constants of the first stage of the TSPC flip-flop are manually calculated using the RC ladder method, as follows
(4.2) 2 2
1 3 : 2
(4.3) (4.4) (4.5)
: is
the total depletion capacitance between the series PMOS transistors and
is the fan-out
capacitance. The propagation delay of the first stage TSPC flip-flopis
0.69 1 : 1 2
(4.6)
The charging and discharging time constants of the first stage E-TSPC flip-flop are given by
2 2
3 1
(4.7) (4.8)
The propagation delay of the first stage TSPC flip-flop is given by
0.69 2 : 2 2
(4.9)
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The output load capacitance of E-TSPC stage is lower than that of TSPC due to the reduced fan-out. The charging time constant of E-TSPC is smaller than TSPC from (4.4) and (4.8), the propagation delay of TSPC stage is higher than that of the E-TSPC stage and thus it proves TSPC flip-flop has a lower operating frequency compared to that of the E-TSPC flip flop. If speed is the critical parameter in the design, E-TSPC logic circuits are chosen over other dynamic logic circuits. However, it suffers from static power dissipation which is discussed in the next section.
4.2.4 Power consumption analysis of TSPC and E-TSPC flip-flops

In digital circuits, the power consumption is divided in to three parts namely; switching power, short-circuit power and leakage power. The total power consumption of a digital circuit is given by

01
(4.10)
The first term represents the switching power consumption, where CL is the load capacitance; fclk is the clock frequency and 10 is the node transition activity factor, the average number of transitions in one clock period. The second term is due to conduction of current directly from the supply to ground when PMOS and NMOS are active simultaneously. The third term is due to the leakage current, which arises from the substrate injection and subthreshold effects. Circuit diagram, waveform, schematic and layout of TSPC and E-TSPC flipflop are as shown in Fig. 4.8 and Fig. 4.9 respectively. The load capacitance at each output node of TSPC flip-flop in divide-by-2 mode is given by
1 2 3
3 4 7
2 2 2
3 4 7
2 5 8
2 2 2
2 5 8
5 7 1 9 3
(4.11) (4.12) (4.13)
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(a) TSPC
(b) E-TSPC
Fig. 4.8 (a) Divide-by-2 circuit (a) TSPC (b) E-TSPC
Fig. 4.8 (b) Waveform of TSPC flip-flop Table.4.1 Delay and power consumption of TSPC flip-flop Parameters Operating voltage (V) Max. operating freq.(MHz) Output frequency (MHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (uW) With parasitics 1.8 2.5 1.25 37 88 62.5 64.71 Without parasitic 1.8 2.5 1.25 27 73 50 45.93
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Fig. 4.8 (c) Schematic diagram of TSPC flip-flop
Fig. 4.8 (d) Layout of TSPC flip-flop
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Table.4.2 Circuit inventory of TSPC flip-flop LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor Nmos Pmos VIEW symbol symbol ivpcell ivpcell TOTAL 142 47 5 4
Fig. 4.9 (a) Schematic of E-TSPC flip-flop
Fig. 4.9 (b) Waveform of E-TSPC flip-flop Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 29
Table.4.3 Delay and power consumption of E-TSPC flip-flop Parameters Operating voltage (V) Max. operating freq.(MHz) Output frequency (MHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 2.5 1.25 50 20 35 1.175 Without parasitics 1.8 2.5 1.25 40 15 27.5 1.173
Fig. 4.9 (c) Layout of E-TSPC flip-flop
Page 30
Table.4.4 Circuit inventory of E-TSPC flip-flop LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor Nmos Pmos VIEW symbol symbol ivpcell ivpcell TOTAL 121 37 3 3
The load capacitance at each output node of E-TSPC flip-flop in divide-by-2mode is given by
1 2 3 1 4 5
2 2 2
1 4 5
2 3 6
2 2 2
2 3 6
3 6 1
(4.14) (4.15) (4.16)
From the above equations it is clear that the capacitance at the each output node of the TSPC circuit is higher than that of the E-TSPC circuit. Since the switching power is linearly related to the load capacitance, TSPC circuits cause more switching power than E TSPC circuits. However, the switching power can be reduced by optimization techniques such as reducing the number of switching stages and the width of the transistors. In TSPC circuits, one of the transistors in each stage is always off, hence there is no short-circuit power consumption. The TSPC short-circuit power is smaller than the E-TSPC short circuit power. The timing diagram of Fig. 4.10 illustrates the operation of a divide-by-2 ETSPC circuit. The shaded part shows the duration where the short-circuit current exists in the ETSPC divide by-2 circuit. To analyze E-TSPC short-circuit, a single stage of an E-TSPC circuit is simulated with PMOS and NMOS transistors active and the PMOS transistor width is increased for a constant NMOS transistor width in 0.18um technology.
Page 31
Fig. 4.10 Divide-by-2 operation of an E-TSPC circuit The short circuit power consumption for different ratios of PMOS to NMOS transistor widths is plotted in Fig. 4.11 for the values which are tabulated in Table.5. As the PMOS to NMOS width ratio increases, both the short-circuit power and the output voltage increases. As a result power consumption also increases since it is directly proportional to input voltage.
Page 32
Table.4.5 Short circuit power in a single stage E-TSPC NMOS width (um) 1 PMOS width (um) 1 2 3 4 5 2 2 4 6 8 10 3 3 6 9 12 15 1.8 1.8 Amplitude (V) 1.8 Current (mA) 0.234 0.448 0.587 0.605 0.610 0.459 0.854 1.132 1.160 1.170 0.684 1.321 1.678 1.724 1.753 Power consumption (mW) 0.421 0.807 1.057 1.089 1.090 0.827 1.538 2.037 2.088 2.106 1.232 2.370 3.020 3.103 3.155
Even though the propagation delay of E-TSPC logic is lower than that of TSPC logic, its large short-circuit power and considerable amount of switching power makes the E-TSPC logic less suitable of low power applications compared to TSPC below 5GHz operation. Power consumption of TSPC and E-TSPC flip flop is shown in Fig. 4.12. Based on this analysis, TSPC logic is chosen for the design of low power divider.
Page 33
Short circuit power in a single stage of E-TSPC circuit

power consumption (mW) 3.5 3 2.5 2 1.5 1 0.5 0 1 2 3 4 5 Ratio of PMOS to NMOS width
width of NMOS= 1um width of NMOS= 2um
width of NMOS= 3um
Fig. 4.11 Short circuit power in a single stage of E-TSPC circuit
Power consumption of TSPC and E-TSPC flip-flop (mW)

1.4 1.175 1.2
1
0.8 0.6 0.4 0.2 0 TSPC E-TSPC 0.0647
Fig. 4.12 Power consumption of TSPC and E-TSPC flip-flop
4.2.5 E-TSPC based 2/3 prescaler

The control logic signal MC changes the operation between divide-by-2 and divide-by-3 modes. If MC =1, the 2/3 prescaler operates in the divide-by-3 mode where the two DFFs actively participate in the operation. If MC =0, the 2/3 prescaler operates in the divide-by-2 mode, where PMOS transistor M2 is always turned-on suppressing the switching activities in DFF1 such that the nodes S1, S2 and S3 remain at logic 1, 0 and 1 respectively. Thus the switching power is saved in DFF1 during the divide-by-2 operation. However, there always
Page 34
exists very high short-circuit power in the first stage of the DFF1 and improper device sizing can still result in switching activities in the DFF1 during the divide-by-2 operation.
Circuit diagram, waveform, schematic and layout of E-TSPC divide-by-2 and divide-by-3 are as shown in Fig. 4.13 and Fig. 4.14 respectively.
Fig. 4.13 (a) E-TSPC 2/3 prescaler
Fig. 4.13 (b) Schematic diagram of E-TSPC divide-by-2 prescaler
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Fig. 4.13 (c) Waveform of E-TSPC divide-by-2 prescaler Table.4.6 Delay and power consumption of E-TSPC divide-by-2 prescaler Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 2.5 1.25 31 72 51.5 2.722 Without parasitic 1.8 2.5 1.25 27 60 43.5 2.655
Fig. 4.13 (d) Layout of E-TSPC divide-by-2 prescaler Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 36
Table.4.7 Circuit inventory of E-TSPC 2/3 prescaler in divide-by-2 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 344 110 7 9
Fig. 4.14 (a) Schematic diagram of E-TSPC divide-by-3 prescaler
Fig. 4.14 (b) Waveforms of E-TSPC divide-by-3 prescaler
Page 37
Table.4.8 Delay and power consumption of E-TSPC divide-by-3 prescaler Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (uW) With parasitics 1.8 2.5 0.833 32 78 55 2.569 Without parasitics 1.8 2.5 0.833 28 66 47 2.541
Fig. 4.14 (c) Layout of E-TSPC divide-by-3 prescaler
Table.4.9 Circuit inventory of E-TSPC 2/3 prescaler in divide-by-3 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 346 110 7 9
Page 38
4.3 Conventional synchronous TSPC 2/3 prescaler

The conventional TSPC 2/3 prescaler consists of two D flip-flops, an OR gate and an AND gate. Due to the large load on DFF2 and difficulty to embed the OR and AND gates into the DFF which introduces additional delay limits the speed of conventional 2/3 prescaler and also causes substantial power dissipation. Circuit diagram, schematic, waveform and layout of Conventional TSPC divide-by-2 and divide-by-3 prescaler are as shown in Fig. 4.15 and Fig. 4.16 respectively. The total load capacitance at the output node Qb of the conventional 2/3 prescaler is given by
30 19 31 20
2(
30
31 )
(4.17)
Fig. 4.15 (a) Conventional TSPC 2/3 prescaler and its equivalent gate level schematic Addition of an OR gate and an AND gate in the critical path introduces the additional delay and limits the maximum operating speed of the circuit. The propagation delay of the TSPC 2/3 prescaler is equal to the sum of propagation delay of DFF1, DFF2and logic gates, where the propagation delay of each DFF is equal to the sum of delay of the each stage.
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The total propagation delay is given by
_1
_2
(4.18)
The propagation delay equations shows that the maximum operating frequency of the conventional 2/3 prescaler is limited due to the logic OR and logic AND gates. The conventional TSPC 2/3 prescaler has 12 stages and each stage has a switching output node. The switching power with 12 switching nodes is given by
12 <1
(4.19)
Where
is the capacitance of the each output node of DFF1, DFF2 and logic gates. The short
circuit power of the conventional 2/3 prescaler is almost negligible and power consumption is mainly due to the switching power due to large capacitance at the output of each stage.
One of the main advantages of domino logic is that the logic gates can be embedded into the flip-flop, which can reduce the additional propagation delay.
4.3.1 Divide-by-2 operation
Fig. 4.15 (b) Schematic of conventional TSPC 2/3 prescaler
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Fig. 4.15 (c) Waveforms of Conventional TSPC 2/3 prescaler in Divide by-2 mode Table.4.10 Delay and power consumption of Conventional TSPC 2/3 in Divide by-2 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 2.5 1.25 41 58 49.5 1.421 Without parasitic 1.8 2.5 1.25 30 34 32 0.978
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Fig. 4.15 (d) Layout of Conventional TSPC 2/3 prescaler in Divide by-2 mode Table.4.11 Circuit inventory of Conventional TSPC 2/3 prescaler in divide-by-2 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 626 216 18 16
Fig. 4.16 (a) Schematic of Conventional TSPC 2/3 prescaler in Divide by-3 mode
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Fig. 4.16 (b) Waveforms of Conventional TSPC 2/3 prescaler in Divide by-3 mode Table.4.12 Delay and power consumption of Conventional TSPC in Divide-by-3 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 2.5 0.833 45 66 55.5 1.433 Without parasitics 1.8 2.5 0.833 30 35 32.5 1.138
Fig. 4.16 (c) Layout of Conventional TSPC 2/3 prescaler in Divide by-3 mode Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 43
Table.4.13 Circuit inventory of Conventional TSPC 2/3 prescaler in divide-by-3 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 615 218 18 16
4.4 TSPC 2/3 Prescaler: Design-I

The conventional TSPC 2/3 prescaler consumes large power and has low operating frequency due to its large load capacitance. An improved speed and low power 2/3 prescaler consists of two D flip-flops and two NOR gates embedded into the flip-flops as shown in Fig. 4.17. Circuit diagram, schematic, waveform and layout of Design-I divide-by-2 and divide-by-3 prescaler are as shown in Fig. 4.18 and Fig. 4.29 respectively.
Fig. 4.17 Design-I TSPC 2/3 prescaler circuit and equivalent gate level schematic
The first NOR gate is embedded into the third stage of DFF1 using a single NMOS transistor M10, whose drain is connected to node S3 of DFF1 and the other NOR gate is embedded into the first stage of DFF2. By doing so, an extra inverter driven by node S3 of Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 44
DFF1 and additional stages introduced by the logic gates between DFF1 and DFF2 of the conventional TSPC 2/3 prescaler is eliminated, reducing the number of switching nodes to 7 in the proposed prescaler. The load capacitance of the proposed 2/3 prescaler is given by
_;
19
20
2(
19
20 )
15
11 (4.20)

When MC=1, transistor M10 turns-on and node S3 switches to logic 0 irrespective of the data at node S2. The second NOR gate output is always equal to the inverted output of DFF2 as shown in Fig. 4.19 (a), which is equivalent to simple DFF with its complimentary output connected to the input as shown in Fig. 4.7 (a). Thus the prescaler act as divide-by-2 when MC=1. Here, even though the output of DFF2 is connected in feedback to the input of DFF1, the switching data at node S1 and S2 is blocked by the transistor M10 to reach to the node S3. Thus the switching power at the node S3 is always zero.
Fig. 4.18 (a) Divide-by-2 operation of 2/3 prescaler unit
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Fig. 4.18 (c) Schematic of Design-I 2/3 prescaler in Divide-by-2 mode
Fig. 4.18 (b) Waveform of Design-I 2/3 prescaler in divide-by-2 mode Table.4.14 Delay and power consumption of Design-I 2/3 prescaler in divide-by-2 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 4.5 2.25 49 69 59 1.412 Without parasitics 1.8 4.5 2.25 48 69 58.5 1.213
Page 46
Fig. 4.18 (d) layout of Design-I 2/3 prescaler in Divide-by-2 mode Table.4.15 Circuit inventory of Design-I 2/3 prescaler in divide-by-2 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 426 142 14 9
However, there exists switching power in the first two stages of the DFF at nodes S1 and S2 due to the feedback action of the DFF2 output which switches continuously. The total power of the prescaler in divide-by-2 mode of operation is equal to the sum of switching power of DFF2 and the switching power of first two stages of DFF1which is less than the conventional 2/3 prescaler.

When MC=0, transistor M10 turns-off and the inverted data at node S2 is passed to the node S3. The second NOR gate output is always equal to the inverted output of DFF2. Fig. 4.20 shows the circuit of the proposed 2/3 prescaler unit in divide-by-3 mode of operation. The combination of inverter and NOR gate is equivalent to logic AND gate with the other input Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 47
inverted as shown in Fig. 4.20. Thus the prescaler act as divide-by-3 when MC=0. There is continuous switching activity at each node and the switching power is given by the sum of switching power of both the DFF1 and DFF2 respectively.
Fig. 4.19 (a) Divide-by-3 operation of the Design-I 2/3 prescaler
Fig. 4.19 (b) Schematic of Design-I 2/3 prescaler in Divide-by-3 mode
Page 48
Fig. 4.19 (c) Waveforms of Design-I 2/3 prescaler in Divide-by-3 mode Table.4.16 Delay and power consumption of Design-I 2/3 prescaler in divide-by-3 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 4.5 1.5 34 45 39.5 1.341 Without parasitics 1.8 4.5 1.5 28 32 30 0.8951
Page 49
Fig. 4.19 (d) Layout of Divide-by-3 operation of Design-I 2/3 prescaler Table.4.17 Circuit inventory of Design-I 2/3 prescaler in divide-by-3 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 441 145 14 9
4.4.3 Propagation delay of TSPC 2/3 prescaler: Design-I

The propagation delay of the proposed 2/3 prescaler is calculated using the RC delay model method which is used to calculate the propagation delay of the conventional2/3 prescaler as discussed in section 4.2. However, in divide-by-2 mode of operation, since the node S3 always remains at logic 0 and blocks the data from DFF1 to propagate to the DFF2. The total propagation delay of the proposed 2/3 prescaler individe-by-2 mode of operation is equal to the propagation delay of DFF2 which is given by
_2
(4.21)
Page 50
The propagation delay of the remaining stages of the DFF2 is similar to the propagation delay of the DFF2 in conventional 2/3 prescaler. In divide-by-3 mode of operation, since both DFF1 and DFF2 are active, the propagation delay is equal to the sum of propagation delay of embedded NOR gate DFF1 and DFF2 respectively, which is given by
;;3
_1
_2
(4.22)
Since the NOR gates are embedded in to the flip-flop, the propagation delay of entire 2/3 prescaler is reduced by delay equal to 7 stages as proved by the RC delay model. Since the number of stages in the proposed Design-I prescaler is reduced to 7, the switching power is given by
;;
7 <1
(4.23)
Where
is the load capacitance at each output node of DFF1 and DFF2. The reduction of the
switching power in the proposed design compared to that of the conventional 2/3 prescaler when both circuits are designed with same transistor sizes is given by
_
12 <1
7 <1
(4.24)
In this analysis, both the conventional 2/3 prescaler and Design-I prescaler are designed using same width of 3 um for PMOS and 1.7 um for NMOS transistors. The node capacitances at each output node for both circuits are assumed to be same, since all the devices has same aspect ratio. The Design-I prescaler reduces the area since it uses only 23 transistors to perform divide-by-2 and divide-by-3 compared to the conventional 2/3 which uses as many as 32 transistors. The output Q drives transistors M11 and M14 of DFF2 and Qb drives transistors M1 and M3 such that loading on Q is reduced compared to conventional prescaler. The simulation results show that the conventional TSPC 2/3 prescaler can operate up to maximum frequency of 2.5 GHz. The Design-I 2/3 prescaler has maximum operating frequency of 4.5 GHz. The simulation results indicate that the Design-I prescaler saves nearly % power in divide-by-3 mode and nearly 19% power in divide-by-2 mode compared to conventional 2/3 prescaler respectively.
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4.4.4 Short-circuit power of the Design-I 2/3 prescaler

The short-circuit power in TSPC is almost negligible since one of the transistors in each stage is always off. However, this is not true when a logic gate is embedded in to the TSPC logic. During the divide-by-2 mode when control logic signal MC =1, the transistor M10 turnson as shown in Fig. 4.17 and Fig. 4.19 (a) allowing a direct path from supply to ground when transistor M7 turns-on. This direct path results in the high short circuit power in the third stage of DFF1. In the Fig. 4.20, it is shown that node S2 goes low for half of the input clock period during which M7 turns-on, creating a direct path from supply to ground since M10 is always turned-on during thedivide-by-2 operation. The shadow lines indicate the period during which short circuit power is exhibited in the 3rd stage of DFF1.
Fig. 4.20 Short circuit power analysis However in divide-by-2 mode, the power consumption of the prescaler is given by the sum of switching power in DFF1 and DFF2, short circuit power in 3rd stage ofDFF1 and short circuit power in DFF2. Since short circuit power is very small in TSPC circuits.
The power consumption in divide-by-2 mode is given by
2 3_;
_1_; _3_1_;
_2_;
(4.25)
Page 52
Where,
_1_;
3 <1 4 <1
(4.26)
_2_;
(4.27)
Based on the short-circuit power analysis of single stage discussed in the section 4.2.4, a simple simulation is done to analyze the power consumption of DFF1 and DFF2. The simulation results indicate that the Design-I prescaler saves nearly 65% power in divide-by-3 mode and nearly 54% power in divide-by-2 mode compared to E-TSPC 2/3 prescaler respectively. In order to overcome the short circuit power problem in 3rd stage of DFF1, an improved 2/3 prescaler is designed which is called as Design-II 2/3 prescaler.
4.5
TSPC 2/3 Prescaler: Design-II

A further improved version of Design-I prescaler is as shown in the Fig. 4.21. In the
Design-II prescaler, an extra PMOS transistor M1a is connected between the power supply and DFF1 whose input is the controlled by the logic signal MC. As discussed in the section 4.2, during the divide-by-2 operation, one of the inputs of second NOR gate is always zero since transistor M10 blocks the data at the input of DFF1 to propagate to the output node. Here, DFF1 is not actively participating in the divide-by-2 operation however; it contributes to the power consumption due to the continuous switching at the nodes S1and S2 respectively. Circuit diagram, schematic, waveform and layout of Design-II divide-by-2 and divide-by-3 prescaler are as shown in Fig. 4.22 and Fig. 4.23 respectively.
Page 53
Fig. 4.21 Design-I TSPC 2/3 prescaler circuit

In this new design, when the control logic signal MC=1 during the divide-by-2 mode, the PMOS transistor M1a is turned-off and DFF1 is disconnected from the power supply. Fig. 4.23 shows the simplified schematic of the Design-II prescaler in the divide-by-2 mode of operation. Even though M10 is always turned-on, the source of M7 is at virtual ground and shortcircuit power is completely avoided. Even if the output Qb switches continuously, the nodes S1, S2 and S3 always remain at logic0 and thus the switching activities are blocked in DFF1 resulting in zero switching power.
Fig. 4.22 (a) Design-II TSPC 2/3 prescaler: divide-by-2 operation The total power consumption of the Design-II prescaler is equal to the switching power of DFF2 which is given by Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 54
2 3_
_2_
(4.28)
_2_
4 <1
(4.29)
Fig. 4.22 (b) Schematic of Design-II 2/3 prescaler in Divide-by-2 mode
Fig. 4.22 (c) Waveforms of Design-II 2/3 prescaler in Divide-by-2 mode
Page 55
Table.4.18 Delay and power consumption of Design-II 2/3 prescaler in divide-by-2 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 4.5 2.25 34 45 39.5 1.039 Without parasitics 1.8 4.5 2.25 26 29 27.5 0.631
Fig. 4.22 (d) Layout of Design-II 2/3 prescaler in Divide-by-2 mode Table.4.19 Circuit inventory of Design-II 2/3 prescaler in divide-by-2 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 418 119 14 9
Page 56
Fig. 4.23 (a) Schematic of Design-II 2/3 prescaler in Divide-by-3 mode
Fig. 4.23 (b) Waveforms of Design-II 2/3 prescaler in Divide-by-3 mode
Page 57
Table.4.20 Delay and power consumption of Design-II 2/3 prescaler in divide-by-3 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 4.5 0.833 34 45 39.5 1.338 Without parasitic 1.8 4.5 0.833 26 29 27.5 0.893
Fig. 4.23 (c) Layout of Design-II 2/3 prescaler in Divide-by-3 mode Table.4.21 Circuit inventory of Design-II 2/3 prescaler in divide-by-3 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 409 119 14 9
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4.5.3 Power saving analysis in Divide-by-2 operation

The percentage of power saved by the Design-II prescaler in the divide-by-2 mode is ratio of the difference in power consumed by Design-I and Design-II prescalers to the power consumed by Design-I prescaler given by
2 3_ ;2 3_ 2 3_
2 3_%
00
(4.30)
Since both circuits use same flip-flop DFF2, which consumes the same power in both the circuits during divide-by-2 and divide-by-3 modes, the power saved by the Design-II prescaler is given by subtracting (4.25) from (4.28).
2 3_;
2 3_; ;3;1_;
;1_;
(4.31)
The flip-flops DFF1, DFF2 of Design-I prescaler are simulated with separate power supply to find out the approximate relation between the power consumption of both D flip-flops during the divide-by-2 operation. From the theoretical analysis it is found that the power consumed by the DFF1 during divide-by-2 operation is almost twice of the power consumed by DFF2. This assumption makes (4.31) simplified and the power consumed in thedivide-by-2 mode is rewritten as
;1_; ;3;1_; ;2_;
;2_;
(4.32)
Thus substituting (4.32) and (4.33) in (4.30), the amount of power saved by the Design-II 2/3 prescaler is 76% in divide-by-2 mode and 65% in divide-by-3 mode compared to E-TSPC 2/3 prescaler. Thus the power consumed in the divide-by-2 mode by the Design-I prescaler is rewritten as
2 3_;
;2_;
;2_;
(4.33)
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4.6 Analysis of TSPC 32/33 (N/N+1) Prescaler

To verify the advantages of the proposed ultra-low power prescaler of Design-II, a divide 32/33 dual modulus unit is implemented with the 2/3 prescaler of Design-II as shown in Fig. 4.24. In this 32/33 prescaler, the proposed 2/3 prescaler unit is followed by four stages of the toggled TSPC divide-by-2 units. Schematic, waveform and layout of TSPC 32/33 prescaler are as shown in Fig. 4.25 and Fig. 4.26 respectively.
Fig. 4.24 TSPC 32/33 prescaler using Design-II 2/3 prescaler

When the control signal MOD is 1, the output of NOR2 always remains at logic 0 and forces the output of NAND2 to logic 1 irrespective of data on Qb1. Since MC is always equal to logic 1, the Design-II prescaler remains in divide-by-2. Thus the 32/33 prescaler acts as divide-by-32 circuit. Since control logic signal MC is logically high, DFF1 in the Design-II 2/3 prescaler is completely turned-off for the entire 32 input clock cycles. The 32/33 prescaler consists of both the synchronous (Design-II prescaler) and asynchronous (toggle divide-by-2) circuits and thus the power and speed is traded-off as discussed in the design of digital counters earlier.
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Fig. 4.25 (a) Schematic of TSPC 32/33 prescaler in divide-by-32 mode
Fig. 4.25 (b) Waveforms of TSPC 32/33 prescaler in Divide-by-32 mode Table.4.22 Delay and power consumption of TSPC 32/33 prescaler in Divide-by-32 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (uW) With parasitics 1.8 2.5 0.078 160 110 135 733.1 Without parasitic 1.8 2.5 0.078 170 120 145 733.1
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Fig. 4.25 (c) Layout of TSPC 32/33 prescaler in Divide-by-32 mode Table.4.23 Circuit inventory of TSPC 32/33 prescaler in divide-by-32 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor Nmos Pmos VIEW symbol symbol ivpcell ivpcell TOTAL 409 119 14 9 and the four asynchronous
If we denote the synchronous 2/3 prescaler as
dividers whose division ratio equal to 16 by AD, the division ratio in this mode (MOD=1) is given by
32
(4.34)
The total power consumed by the 32/33 prescaler using Design-I 2/3 prescaler during divide-by-32 is equal to the sum of switching and short circuit power of the DFF1, DFF2 over 32 clock cycles, power consumed by four asynchronous divide-by-2 circuits, and the power consumed by the logic gates.
32_1 _2 _1 _3_1 __16
(4.35)
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The power consumed by the four asynchronous divide-by-2 circuits is given by

41 2 1
2
__16
4 ;1
(4.36)
Here,
is the frequency of the output signal from the 2/3 prescaler which can be half or one-
third of the input clock signal and is the total short-circuit current of the each asynchronous divide-by-2 circuit. Each of the asynchronous divider toggles at half the operating frequency of the preceding divide-by-2 circuit. Similarly, the power consumed by the 32/33 prescaler during the divide-by-32 operation using the Design-II prescaler is equal to the sum of switching and short circuit power of DFF2 over 32 clock cycles (DFF1 turned-off) and the power consumed by the 4 asynchronous dividers and logic gates. The power saved by the 32/33 prescaler during divide-by-32 mode using Design-II prescaler is equal to the amount of power consumed by DFF1 of the Design-I prescaler. Here, the power consumed by DFF1 always refers to the Design-I prescaler since power consumed by DFF1 of Design-II prescaler is always zero.
32_ _1 _3_1
(4.37)

The dual-modulus 32/33 prescaler operates as divide-by-33 when MOD=0. By using the combination of logic NOR and NAND gates, the asynchronous divide-by-16 counter is made to count an extra input clock. The control signal MC is given by
(4.38)
Fig. 4.26 (a) Schematic of TSPC 32/33 prescaler in Divide-by-33 mode Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 63
Fig. 4.26 (b) Waveforms of TSPC 32/33 prescaler in Divide-by-33 mode Table.4.24 Delay and power consumption of TSPC 32/33 prescaler in Divide-by-33 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 2.5 0.075 150 130 140 1.046 Without parasitics 1.8 2.5 0.075 140 110 125 0.894
Table.4.25 Circuit inventory of TSPC 32/33 prescaler in divide-by-33 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 1536 455 46 37
Page 64
Fig. 4.26 (c) Layout of TSPC 32/33 prescaler in Divide-by-33 mode In the initial state, the Design-II 2/3 prescaler will be in divide-by-2 mode (MC=1) and the asynchronous divide-by-16 starts counting the output pulses of 2/3 prescaler from 0000 to 1111. When the asynchronous counter value reaches 1110, the logic signal MC goes low (MC=0) and the Design-II 2/3 prescaler operates in divide-by-3 mode, where the asynchronous counter counts an extra input clock pulse. During this operation, the 2/3 prescaler operates in divide-by-2 mode for 30 input clock cycles and for the remaining 3 input clock cycles; it operates in divide-by-3 mode. The division of the 32/33 prescaler in this mode is given by
33
(4.39)
where AD=16, MOD=0 and M=2. The total power consumed by the 32/33 prescaler using Design-I prescaler during the divide-by-33 operation is equal to the sum of switching power of the flip-flops DFF1, DFF2, short circuit power in the 3rd stage of DFF1 over 30 clock cycles, power consumed by four asynchronous divide-by-2 circuits and the power consumed by the digital gates.
32_1 __16 30 33 _3_1 _2 _1
(4.40)
Page 65
Similarly, the power consumed by the 32/33 prescaler using Design-II prescaler during the divide-by-33 operation is equal to the sum of the switching, of DFF2; switching power of DFF1 over 3 clock cycles, power consumed by the 4 asynchronous dividers and digital logic gates.
32_1 3 33 _1 _2 __16
(4.41)
Since power consumed by DFF2, 4 asynchronous dividers and the logic gates are same in both cases, the total amount of power saved by the 32/33 prescaler during the divide-by-33 using Design-II prescaler is equal to 1.4 times the power consumed during divide-by-32.
4.7
Proposed TSPC 47/48 prescaler
The proposed 47/48 prescaler circuit as shown in Fig. 4.27 is similar to the 32/33 prescaler except for an additional inverter which is added between the output of the NAND2 gate and the control signal (MC) input of the 2/3 prescaler. The 47/48 prescaler consists of Design-II 2/3 prescaler, four asynchronous divide-by-2 circuits and additional logic gates to control the division ratio between 47 and 48. Schematic, waveform and layout of TSPC 47/48 prescaler are as shown in Fig. 4.28 and Fig. 4.30 respectively.
Fig. 4.27 TSPC 47/48 prescaler using Design-II 2/3 prescaler
Page 66
When MC=0, the 2/3 prescaler of the 32/33 prescaler operates in divide-by-3 mode whereas the 2/3 prescaler in the proposed 47/48 prescaler operates in divide-by-2 mode. Thus the inverter swaps the operation modes of the 2/3 prescaler.

The proposed 47/48 prescaler operates as divide-by-47 when MOD=0. By using the combination of logic NOR and NAND gates, the asynchronous divide-by-16 counter is made to count an extra input clock. In the initial state, the 2/3 prescaler will be in divide-by-3 mode (MC=1) and the asynchronous divide-by-16 starts counting the output pulses of 2/3 prescaler from 0000 to 1111. When the asynchronous counter value reaches 1110, the logic signal MC goes low (MC=0) and 2/3 prescaler operates in divide-by-2 mode, where the asynchronous counter counts an extra input clock pulse. During this operation, the 2/3 prescaler operates in the divide-by-3 mode for 45 input clock cycles and in the divide-2 mode for 2 input clock cycles. The division ratio of the 47/48 prescaler in this mode is given by
48
2 2
(4.42)
Fig. 4.28 (a) Schematic of TSPC 47/48 prescaler in Divide-by-47 mode
Page 67
Fig. 4.28 (b) Waveforms of TSPC 47/48 prescaler in Divide-by-47 mode Table.4.26 Delay and power consumption of TSPC 47/48 prescaler in Divide-by-47 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 2.5 0.053 240 140 190 1.141 Without parasitics 1.8 2.5 0.053 140 110 125 0.887
Table.4.27 Circuit inventory of TSPC 47/48 prescaler in divide-by-47 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor Nmos Pmos VIEW Symbol Symbol Ivpcell Ivpcell TOTAL 1566 469 47 38
Page 68
Fig. 4.28 (c) Layout of TSPC 47/48 prescaler in Divide-by-47 mode

When the control signal MOD is 1, the output of NOR2 in Fig.4.28 always remains at logic 0 and forces the output of NAND2 to logic 1 irrespective of data on Qb1. Since MC is always equal to logic 1 ( =0), the 2/3 prescaler remains in divide-by-3 mode. The equivalent circuit of inverter and the 2/3 prescaler is equal to divide-by-3 counter as shown in Fig. 4.29. Thus the 47/48 prescaler operates in divide-by-48 mode when MOD=1. If we denote the synchronous 2/3 prescaler as (MOD=1) is given by and the four asynchronous dividers whose division ratio equal to 16 by AD, the division ratio of the 47/48 prescaler in this mode
48
0 2 0 2
(4.43)
Page 69
Fig. 4.29 Divide-by-48 mode of operation
Fig. 4.30 (a) Schematic of TSPC 47/48 prescaler in Divide-by-48 mode
Fig. 4.30 (b) Waveforms of TSPC 47/48 prescaler in Divide-by-48 mode
Page 70
Table.4.28 Delay and power consumption of TSPC 47/48 prescaler in Divide-by-48 mode Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 2.5 0.052 230 130 180 1.141 Without parasitics 1.8 2.5 0.052 140 110 125 0.877
Fig. 4.30 (c) Layout of TSPC 47/48 prescaler in Divide-by-48 mode Table.4.29 Circuit inventory of TSPC 47/48 prescaler in divide-by-48 mode LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW symbol symbol ivpcell ivpcell TOTAL 1572 462 47 38
Page 71
Chapter 5 Ultra Low Power Fully Programmable Dividers

5.1 Introduction
Most of integer-N frequency synthesizers are implemented using the pulse-swallow divider topology. The IEEE 802.15.4 and Zigbee standard has 16 channels, spaced 5 MHz apart from 2405 MHz to 2480 MHz. If direct conversion is used in both the TX and RX, then the 16 channel selection frequencies would be from 2405 MHz to 2480 MHz in steps of 5 MHz. If a low IF architecture is used for the RX, then the channel selection frequencies could be different for the both TX and RX. In order to have more flexibility to accommodate channel selections for both kind of architecture, the resolution of the divider and reference frequency chosen is 1 MHz which gives a resolution of 1 MHz to the channel selection frequency. For example, if the IF frequency is chosen to be 2 MHz, the divider is programmed to have the channel frequencies equal to 2403, 2408.2478 MHz or 2407, 2412.2482 MHz
5.2 Fully Programmable Divider: Design-I

For PLL synthesizers operating in the 2.4 GHz ISM band with a resolution of 1MHz and division ratios of 2400-2484 can be achieved with a 32/33 prescaler, a 7 bit P-counter and a 5 bit S-counter. Fig. 5.1 shows the Design-I fully programmable divider with a division ratio from 2400 to 2484 in steps of 1. In this design, only bits P1, P2 and P3 of the P-counter are used programming and the bits P4, P5, P6 and P7 are fixed at 1, 0, 0 and 1 respectively to have P-values between 74-77. Here all the bits of S-counter are used for programming. The P and S counters programmable value for the division ratios between 2400-2484 is shown in Table.5.1. Table.5.1 Programmable values of the programmable counters Frequency division Programmable Swallow Prescaler (N/N+1) Ratio counter counter 2400-2431 N=32 P=75 S=0-31 2432-2463 N=32 P=76 S=0-31 2464-2484 N=32 P=77 S=0-20
Page 72
Fig. 5.1 Fully programmable divider: Design-I
5.2.1 Prescaler (N/N+1)

A 32/33 prescaler is used in this Design-I of the fully programmable divider. To provide a 1 MHz resolution, the maximum programmable value of the swallow S-counter should be less than the value of the prescaler (S<N) and the value of S-counter value should be always less than P-counter value (S<P) to satisfy the conditions of pulse-swallow topology. So, a 64/65, 128/129 prescaler cannot be used for the implementation of 1 MHz resolution divider with division ratio between 2400 and 2484. A 16/17 prescaler can be used, but this will increase the complexity of the programmable P-counter and the input frequency at which the two counters operate. If a 32/33 prescaler, which is briefly discussed in the chapter 4 is used, the maximum programmable value of swallow S-counter is equal to 31 (S=N-1).
5.2.2 Programmable P-counter

The 32/33 prescaler scales the input 2.4 GHz signal by a value of 32 or 33 such that the P and S counters will be working in the frequency range of 72 - 78 MHz in order to obtain the 1 MHz frequency output. The design requirements of the P-counter in the design of 2.4 GHz fully programmable divider are as follows: Operate at frequencies of up to several 100 MHz with low power consumption. Able to program the desired P values from 74 to 77. To generate full-swing output, which is fed to the phase frequency detector block. Page 73
Fig. 5.2 7-bit programmable P-counter The programmable P-counter used in the design of the fully programmable divider is a 7-bit asynchronous down counter as shown in Fig. 5.2. The P-counter is designed with 7 reloadable TSPC D flip-flops (DFF) and an end-of-count (EOC) detector which has reload circuit in it. Since the counter is asynchronous and based on the ring topology, the output of the first DFF is fed as clock to the input of next flip-flop. In the initial state, all the reloadable FFs are loaded by the programmable pins P1-P7. As the counter is triggered by the output of the prescaler, the P-counter starts down counting till the state 0000000 is reached. Once this state is detected by the EOC logic circuit, the load (LD) signal goes high to reset all loadable FFs to the initial state.
Page 74
5.2.2.1
Operation of EOC logic
The EOC logic circuit is used to detect when the P-counter reaches the state Q1Q2Q3Q4Q5Q6Q7=0000000, and preset the reloadable FFs to the initial state so that Pcounter starts down counting again from the loaded value to the final state. The EOC logic circuit is built with a 2-input NOR, two 3-input NAND and an embedded NOR DFF as shown in Fig. 5.3 (a) and the Fig. 5.3(b) shows the equivalent transistor level schematic of the embedded NOR-DFF. Here all the complementary outputs of the reloadable FFs are given to EOC logic circuit to detect the state Qb1Qb2Qb3Qb4Qb5Qb6Qb7=1111111 to simplify the EOC circuit. Fig. 4.4 shows the timing diagram of the EOC logic circuit.
Fig. 5.3 a) EOC logic circuit for P-counter b) NOR embedded TSPC DFF When the P-counter reaches the penultimate state (Q1Q2Q3Q4Q5Q6Q7=0000001), the following events occur during the next rising edge of the clock: The counter enters the final state 0000000 after a CLK-to-Q delay TCLK-Q where the input to the EOC is 1111111. The delay of EOC logic circuit is TEOC1 after which the EOC logic circuit output goes high (LD=1) to reload the FFs with initial programmable values. In this case P=75 or 1001011. There is a reloading delay time of TR for the P-counter to reload the initial state. Page 75
Fig. 5.4 Timing diagram of 7-bit P-counter The output of EOC logic circuit goes low only after a delay of TEOC2 after the Pcounter is loaded with the preset value. There exists a time delay of TEN where the LD goes low and the counter starts counting from the loaded value. From the above timing diagram, it is found that all the delays must be less than a single clock period for the counter to function correctly. The relation between all the delays and clock period is given by > ; 1 2 (5.1)
From the above delay analysis, it is found that the counter speed can be increased by reducing the CLK-to-Q (TCLK-Q) delay. For the counter to function correctly, instead of detecting all zeros state, a previous state is made to detect by the EOC logic circuit to avoid the delays introduced by the reloadable FFs and logic gates of the EOC circuit. The logic gates introduce glitches since all the outputs from the reloadable FFs are not arrived at the same time. To avoid all the glitches passing to the input of reloadable FFs, a TSPC DFF is introduced between the logic gates and the reloadable FFs. The NOR gate is embedded in to the DFF to reduce the delay. By introducing NOR-embedded DFF, the signals A and B are latched to output LD only at the rising edge of the clock signal. In this design we chose to detect the state 0000010. When the state 0000010 is reached, the signals A and B go low after a delay introduced by the Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 76
logic gates which is assumed to be less than half of the input clock cycle. However, the output of the embedded-NOR gate is latched to output only at the next rising edge of clock after the state 0000001 is reached. This output LD signal will initialize the P and S counters and the counting process continues. If the state 0000001 is chosen to detect, then it results in the undercounting due to the delays.
5.2.2.2 Reloadable TSPC DFF for P-Counter
Fig. 5.5(a) Reloadable DFF for P-counter
Fig. 5.5(b) schematic of Reloadable DFF for P-counter Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 77
Fig. 5.5 shows the schematic of reloadable TSPC DFF used in the design of the 7-bit Pcounter. This reloadable FF is similar to the original nine transistors TSPC DFF with reloadable functions added to it. The reloadable FF is programmed through the input PI. The signals LD and LDB are used to reload the programmable state of the FF.
Operation of Reloadable DFF Once the programmable input (PI) of the each reloadable FF is loaded with a value and LD signal goes low, the P-counter begins to count down. Under this condition, the right hand side of the reloadable DFF as highlighted in Fig. 5.5 is deactivated and transistor M5 is turnedoff such that the FF acts as a divide-by-2 circuit where node S3 is complimentary of the divideby-2 output. The FF remains in the divide-by-2 mode until the counter reaches the state 0000010. When LD=1, the first two stages of the reloadable FF is deactivated and node S1 always remains at logic 0 since the transistor M5 is turned-on. Since node S1 is at logic 0, node S2 should be at logic 1. However, node S2 is overridden by the complimentary value of node S4. Under this condition (LD=1), if the programmable input PI=0, nodes S4 and S2 switch to logic 1 and 0 respectively. The value at node S2 is latched to the output node Q on the next rising edge of the clock. Similarly, if PI=1, the output Q switches to 1 on the clock rising edge. However when LD=0, the bit-cell acts as a divide-by-2 circuit irrespective of the PI value. Table 5.2 shows the operation of the reloadable FF. Table 5.2 Operation of the Reloadable DFF of the P-counter Load (LD) Programmable input (PI) Output (Q) 0 0 CLK/2 0 1 CLK/2 1 0 0 1 1 1
5.2.3 Swallow S-counter

The fully programmable divider also consists of a 5-bit swallow S-counter whose design requirements are as follows: To operate at frequencies of up to several 100 MHz with low power consumption. To load the programmable S values from 0 to 31 in steps of one and stop the operation when S counting is finished. Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 78
To generate a full-swing output, this is given as feedback signal to phase frequency detector block.
Fig. 5.6 A 5-bit Swallow S-counter The swallow S-counter used in the design of the fully programmable divider is a 5-bit asynchronous down counter as shown in Fig. 5.6. The S-counter is designed with 5 reloadable TSPC D flip-flops and an end-of-count (EOC) detector with the reload circuit. Since the counter is asynchronous and based on the ring topology, the complementary output of the first DFF is fed as clock to the input of next flip-flop. In the initial state, all the reloadable FFs are loaded by the programmable value set by pins S1-S5. In the S-counter all states from 0-31 are usable and adjustable in steps of 1 to obtain a resolution of 1MHz. Once the counter is triggered by the output of the prescaler, the S-counter starts down counting till the final state is reached, which is detected by the EOC logic circuit and the stop (SP) signal goes high until the P-counter finishes its counting. Since the value of P is always greater than value of S in pulse-swallow divider, the S-counter remains idle for a period of the S-counter is shown in Fig. 5.7. Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 79 clock cycles. The EOC logic circuit for
Fig. 5.7 EOC logic circuit for S-counter

As discussed earlier, the signal SP goes high only when the outputs of all the reloadable DFF in the S-counter go low and remain in the same state until the LD signal from the P-counter goes high. The state where SP remains at logic high indicates the S-counter has finished counting. The Scounter cannot use the EOC logic circuit of the P-counter since SP has to remain high until the Pcounter reaches the state 0000010 when the LD signal goes high for one clock cycle. Moreover in the S-counter, all zero state is detected by EOC circuit unlike in the P-counter. Since the S-counter uses all available states from 0-31 and the EOC circuit detects the state 00000, SP signal goes high only during the next clock cycle which results in the counting of an extra clock cycle. In order to avoid to the counting of extra clock cycle, state Q 5Q4Q3Q2=0000 is detected and the least significant bit (Q1) is neglected. The output of the NAND2 gate switches to logic 0 as soon as the S-counter reaches the state 0000. Since the other input of the embedded NOR gate is always 0, SP goes high during the next rising edge of the clock cycle and the S-counter remains idle until it is triggered by LD signal from the P-counter.
5.2.3.1
Reloadable TSPC DFF for S-Counter
Fig. 5.8 shows the schematic of an improved reloadable TSPC DFF used in the design of 5-bit Scounter. This reload DFF is similar to the reloadable DFF used in the design of P-counter. However, the reloadable DFF for the S-counter needs an extra logic function SP to be incorporated.
Page 80
Fig. 5.8 (a) Reloadable DFF for S-counter
Fig. 5.8 (b) schematic of Reloadable DFF for S-counter Operation of reloadable DFF for S-counter When SP goes high, the S-counter remains idle for a period of clock cycles
and the reloadable DFF of the S-counter consumes some switching power. In the improved design, transistors M6 and M7 are added to reduce the switching activities in the reloadable DFF. When the state 0000 is reached, SP goes high, M6 is turned-on and M7 is turned-off such that Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 81
node S1 and S2 remain at logic 0 for the remaining
clock cycles until LD
becomes high. During this period, since LD=0, the right hand side portion of the circuit is deactivated similar to the reloadable DFF of the P-counter. Thus there is no switching activity at any node during the idle state of the S-counter and switching power is saved for a period of clock cycles. In other conditions, the operation of the improved reloadable DFF for S-counter is similar to the operation of the reloadable DFF in P-counter described earlier. Table 5.3 shows the operation of reloadable DFF used in the S-counter. Table 5.3 Operation of the Reloadable DFF of the S-counter Stop (sp) Load (LD) Programmable input (PI) Output (Q) 1 X X 1 0 0 0 CLK/2 0 0 1 CLK/2 0 1 0 0 0 1 1 1
5.3 Simulation and Measured results of the programmable divider: Design-I

The simulations of the fully programmable divider with 1MHz resolution are performed using Cadence SPECTRE RF for a 0.18um CMOS process. Here the programmability of the divider is set to 2400 and the results indicate that the output of the fully programmable divider is 1MHz with duty cycle less than 25%. The low duty cycle is due to the large difference between programmability P value, prescaler N value and the S-counter S value (P>>N and P>>S). Fig. 5.9 shows the output waveform of the proposed fully programmable divider respectively.
Page 82
Fig. 5.9 Output waveform of proposed fully programmable divider: Design I
5.4 Fully programmable divider: Design-II

For the IEEE 802.15.4 standard, to obtain a 1 MHz resolution for division ratios between 2400-2484 with a 47/48 prescaler, a 6-bit P-counter and a 6-bit S-counter is required as shown in Fig. 5.10. In this design-II, the P-counter is programmable from 51 to 52 (P1 and P2 are only programmable) and the S-counter is programmable from 0 to 47 (S1 to S6) in steps of 1 to accommodate division ratios from 2400 to 2484. The frequency division (FD) performed by the programmable divider is given ( ) ( ) (5.2)
Page 83
Fig. 5.10 Fully programmable divider: Design-II The frequency division (FD) in (5.2) is different to the conventional division ratio performed by pulse-swallow divider discussed in the previous sections due to the dual-modulus 47/48 prescaler. When P1=1, P2=1 and P3=0, the P-counter is loaded to a value of 51 and S-counter is programmed from 0 to 47 to accommodate division ratio from 2400 to 2448 in steps of 1. When P1=0, P2=0 and P3=1, the P-counter is loaded to a value of 52 and S-counter is programmed from 14 to 47 to accommodate division ratio from 2448 to 2483 in steps of 1. The P and S counters programmable value for the division ratios between 2400-2484 is shown in Table 5.4.
Table 5.4 Programmable values of the programmable counters Frequency Division Programmable Swallow Prescaler (N/N+1) Ratio counter (P) counter (S)
2400-2448 2449-2484 N=47 N=47
51 52
0-47 41-47
Page 84
5.4.1 Programmable P-counter and S-counters: 6-bit version
Fig. 5.11 (a) 6-bit Swallow S-counter with EOC logic circuit The 6 bit swallow S-counter used in the fully programmable divider is shown in Fig. 5.11 which is similar to the S-counter shown in Fig. 5.7 except an additional reloadable DFF. Here the state Q6Q5Q4Q3Q2=000000 is detected by the EOC logic circuit. The S-counter in this programmable divider can be programmed from 0-47 in steps of 1 for a fixed value of the Pcounter.
Page 85
Fig. 5.11 (b) Schematic of 6-bit Swallow S-counter with EOC logic circuit
Page 86
Fig. 5.12 (a) 6-bit Programmable P-counter with EOC logic circuit
Fig. 5.12 (b) schematic of 6-bit Programmable P-counter with EOC logic circuit Dept of Electronics & Communication, SIT Tumkur 2012-13 Page 87
The 6-bit programmable P-counter used in the design-II programmable divider is shown in Fig. 5.12 which is similar to the P-counter shown in Fig. 5.2 with a reduced number of reloadable DFFs. The EOC logic circuit is modified according to the design of the P-counter to detect the state Q6Q5Q4Q3Q2Q1=000010. Here, bit P6 and P5 are always at logic '1' and bit P4 at logic '0' to have a programmable values of 51 and 52. By choosing a fixed value of 51 and 52, the swallow S-counter is programmed in steps of one-bit to provide a division ratio from 2400 to 2484 with 1 MHz resolution.
5.5 Simulation and Measured results of the programmable divider: Design-II

The Design-II fully programmable divider at 2.4 GHz consumes a power of 0.6 mW. The results indicate that the output of the fully programmable divider is 1MHz with duty cycle of 45%. The divider consumes a power of 0.62 mW at 1.8V power supply and Fig. 5.13 shows the measured 1 MHz output of the Design-II fully programmable divider.
Fig. 5.13 Output waveform of fully programmable divider: Design-II
Page 88
5.6 Summary
In this chapter, detailed designs of the fully programmable divider with 1 MHz resolution are presented along with the detailed design of the programmable P-counter and swallow S-counter. A 47/48 TSPC dual modulus prescaler is proposed which improves the output signal duty cycle of the fully programmable divider. An improved reloadable TSPC DFF for the S-counter is introduced which reduces the switching power of the counter during the idle state when the Pcounter is still active. The implemented fully programmable divider consumes a power of 0.62mW at 1.8 V power supply.
Page 89
Chapter 6
6.1 Simulation Results and Future Scope
A complete analysis and comparison of the performance of the proposed TSPC 2/3prescalers, the conventional TSPC 2/3 and E-TSPC based prescalers is carried out. The prescalers are simulated at 1.8 V to have driving capability for fair comparison. The simulations are performed using Cadence SPECTRE RF for a 180nm CMOS process.
Table.5.5 (a) Simulation results

Design parameters Process (nm) 180 180 TSPC E-TSPC CONVENTIONAL TSPC 180 CONVENTIONAL E-TSPC 180 180 180 DESIGN-I DESIGN-II
Max. Freq (Hz) Power (mW) Divide-by-2 mode (av_etracted) Power (mW) Divide-by-2 mode (Schematic) Power (mW) Divide-by-3 mode (av_etracted) Power (mW) Divide-by-3 mode (Schematic)
2.5M
2.5M
2.5G
2.5G
4.5G
4.5G
0.064
1.175
1.421
2.722
1.412
1.039
0.045
1.173
0.978
2.655
1.213
0.631
1.433
2.569
1.341
1.338
1.138
2.541
0.895
0.893
Page 90
Table.5.5 (b) Simulation results

Design parameters TSPC Fully programmable divider DESIGN-I Process (nm) 180 180 Fully programmable divider DESIGN-II 180
Max. Freq (Hz)
2.5M
2.5G
2.5G
Power (mW) Divide-by-32 mode Power (mW) Divide-by-33 mode Power (mW) Divide-by-47 mode Power (mW) Divide-by-48mode
0.733
0.894
0.887
0.877
It can be seen that the analysis done using Cadence tools has achieved the desired aim of reducing the power consumption and reducing the delay satisfying the provided specifications. This project is concentrated on the design of fully programmable divider with reduced power consumption. The future scope lies in designing the frequency synthesizer.
Page 91
Chapter 8 Conclusion
This project focuses on the design techniques of low power frequency dividers and frequency divider. A detailed study of different kind of divider topologies is given and the propagation speed and power consumption of dynamic logic dividers such as TSPC and E-TSPC circuits are investigated. Based on this study, a new low power and improved speed TSPC 2/3 prescaler is proposed. Compared with the existing TSPC architectures, the proposed 2/3 prescaler is capable of operating up to 4.5 GHz and the amount of power saved by the Design-II 2/3 prescaler is 76% in divide-by-2 mode and 65% in divide-by-3 mode compared to E-TSPC 2/3 prescaler.
A fully programmable divider with 1 MHz resolution is presented using 32/33 prescaler, a 7-bit P-counter and a 5-bit S-counter. This divider suffers from low output duty cycle of 25% mainly due to the large difference between P and S values. To overcome the low duty cycle problem, a low power TSPC 47/48 is proposed whose maximum operating speed is 4.8 GHz with power consumption of 0.48 mW at a supply voltage of 1.8V. An improved reloadable DFF is implemented in the design of S-counter which reduces the switching power of S-counter during its idle state. A new fully programmable divider using the proposed 47/48 prescaler, a 6bit P-counter and a 6-bit S-counter are implemented using 180nm technology in Cadence. The divider consumes a power of 0.62 mW at 1.8V power supply and the duty cycle of the output 1 MHz signal is close to 47%.
Page 92
BIBLIOGRAPHY
References [1] M. V. Krishna, J. Xie, W. M. Lim, M. A. Do, K. S. Yeo, and C. C. Boon, A low power fully programmable 1 MHz resolution 2.4 GHz CMOS PLL frequency synthesizer, in Proc. IEEE Biomed. Circuitsand Syst. Conf., Nov. 2007, p. 187. [2] J. M. Rabaey, A. Chandrakasan, and B. Nikolic,Digital Integrated Circuits, A Design Perspective, ser. Electron and VLSI, 2nd ed. UpperSaddle River, NJ: Prentice-Hall, 2003
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Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

Dept of Electronics & Communication, SIT Tumkur 2012-13

Organization of the report

Chapter 2 Literature Survey

2.2 Comparison between TTL and CMOS logic families

2.2.1 Characteristics of CMOS logic family

Dept of Electronics & Communication, SIT Tumkur 2012-13

2.2.2 Characteristics of TTL logic family

2.2.3 Advantages of CMOS over TTL

2.3 Electronic analysis of MOSFET

2.3.1 Pass Characteristics of NMOS-FET

2.3.2 Pass Characteristics of PMOS-FET

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Fig. 2.3. Schematic diagram of pass PMOS-FET

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Fig. 2.4. PMOS Pass characteristic

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Chapter 3 Implementation using Cadence Tools

3.1 Design Steps using Cadence Software

Fig. 3.1 creating a new library from the CIW window

Fig. 3.2 Creation of TSPC schematic

Fig. 3.3 Creation of TSPC symbol

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Fig. 3.4 Creation of TSPC test schematic

Simulation with spectre

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Fig. 3.5 Simulation with spectre in ADEL environment

3.2 Design methodology

3.2.1 Design specifications

Length l = 180nm Width w = 1.7um

Length l = 180nm Voltage V1 = 0 V

Voltage V2 = 1.8 V Voltage Vdc = 1.8 V

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3.2.2 Selecting P/N ratio

3.2.3 Creating schematic

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Fig. 3.7 Schematic of TSPC circuit

3.2.4 Symbol creation

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3.2.5 Simulation of schematic

3.2.6 Mask layout

3.2.7 Design Rule Check (DRC)

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3.2.9 Layout versus Schematic check (LVS)

3.2.10 Post Layout Simulation

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Chapter 4 Analysis of Ultra Low Power Prescaler

perform a programmable division ratio of

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Fig. 4.1 Topology of the Pulse Swallow frequency divider

4.1.1 Theory of operation

until swallow counter is full. .

pulses at the input, the modulus control changes to

Synchronous 2/3 prescaler

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4.2.1 Current-mode logic (CML) dividers

4.2.2 Dynamic logic dividers

4.2.3 Propagation speed analysis of TSPC and E-TSPC flip-flops

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(4.3) (4.4) (4.5)

capacitance. The propagation delay of the first stage TSPC flip-flopis

The propagation delay of the first stage TSPC flip-flop is given by

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