Reg. No.

Question Paper Code :

77905

Second Semester Applied Electronics

VL 9221 CAD FOR VLSI CIRCUITS (Common to M.E. VLSI Design) (Regulation 2009) Time : Three hours

PART A (10 2 = 20 marks)

2. 3. 4. 5. 6. 7. 8.

What are the entities to be optimized while designing VLSI circuits? What is the common type of minimum distance rules? How do you enhance the partitioning efficiency? What is a shape function? List out any four local routing problems. What are the different delay models? What is the principle behind the reduced ordered binary decision

9.

10.

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diagram?

What are the goals of high level synthesis? Draw the data flow graph (DFG) for iterative dataflow with example.

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1.

Compare and contrast tractable and intractable problems.

Answer ALL questions

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Maximum : 100 marks

M.E. DEGREE EXAMINATION, APRIL/MAY 2011

PART B (5 16 = 80 marks) 11. (a) With an aid of Y chart explain the different design domains and compare the different design methodologies. Or (b) 12. (a) Explain, how can the principle of backtracking be used in travelling salesman problem with example? (16) Write the pseudo code of Kernighan-Lin partitioning algorithm and explain it with suitable example. (16) Or (b) (16)

List out the factors to be considered for partitioning and explain how can simulate annealing be applied to placement problems. (16) (i) (ii) Describe the shape functions, floor plan sizing and optimization problems in floor planning. (10) What is the goal of channel routing and describe the classical model? (6) Or

13.

(a)

(b) 15. (a)

Explain the specific simulation tools for different abstraction levels.(16) Explain various scheduling algorithms in high level synthesis and compare them. (16) Or

(b)

Write explanatory notes on : (i)

High level transformation. models, internal representation in high

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Or 2

14.

(a)

Write about the issues related to event driven simulation and their merits and demerits. (16)

(b)

What are the different approaches to solve global routing problem? Write an efficient algorithm to find a path between a pair of points in a rectangular grid. (16)

(ii) Hardware synthesis.

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(8) level (8)

77905