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Ecad Lab Manual1
Ecad Lab Manual1
x x x x t
= 1.6k
ii. A
o
=1+
1
R
RF
=5
R
f
=4R
1
Choose a value of 10k for R
1
Then R
f
=40 k
GRAPH:
Sl.No Input frequency Output voltage Gain 20 log Vo/Vi
1. 100
2 200
3 500
4. 1kHz
5. 1.5KHz
6. 2.0kHz
7. 5kHz
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 77
BY VIDYA SAGAR.P
RESULT:
i. The cut-off frequency of the low pass filter = kHz
ii.The pass band gain of low pass filter =
INFERENCE:
i. The working of active low pass filter is observed and the output is plotted.
ii. The frequency response of the low pass filter is plotted on a semi-log graph
paper.
iii. It is observed that the gain rolls of at the rate of 20dB per decade at the cut
of frequency.
REVIEW QUESTIONS:
i.Define an electric filter.
ii.Classify filters
iii.Discuss the disadvantages of passive filters
iv.Why are active filters preferred?
v.List the commonly used filters.
vi.Define pass band and stop band of a filter.
vii.What is roll-off rate of a first order filter?
viii.Why do we use higher order filters?
ix.On what does the damping coefficient of a filter depend?
x.What is sallen key filter?
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 78
BY VIDYA SAGAR.P
EXPERIMENT NO 2 : HIGH PASS FILTER
AIM:
To Design a Low pass, first order Butterworth Filter with a cut-off frequency
of fL=1.0 kHz and pass band gain of 5.
EQUIPMENTS AND COMPONENTS:
APPARATUS
1. CRO (Dual channel) - 1 No
2. Signal Generator - 1 No
3. Bread Board - 1 No.
4. Dual channel power supply 1 No
THEORY:
A frequency selective electric circuit that passes electric signals of specified
band of frequencies and attenuates the signals of frequencies outside the brand
is called an electric filter. The first order high pass filter consists of a single RC
network connected to the non-inverting input terminal of the operational
amplifier. Resisters R1 and R
F
determine the gain of the filter in the pass band.
The high pass filter has maximum gain at f = f
l
Hz. The frequency range from
0 to F
l
is called the stop band the frequency range f > fl is called the pass band.
An Op-Amp High pass filter is shown in fig 2. The circuit allows the high
frequency signals freely through it and attenuates the signals below a cut off
frequency called Lower cut off frequency (f
L
). The inverting terminal is
grounded through a resistor R
i
. A resistor R
f
is connected in feedback path.
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 79
BY VIDYA SAGAR.P
A Capacitor C is connected between the input signal source and the inverting
terminal of the Op-Amp and a Resistor R is connected between the inverting
terminal and ground.
Let V
i
= Input voltage
V
g
= Voltage at the Non-inverting input
V
o
= output voltage.
A = Gain of the Op-Amp
Where f
L
is the Lower cut off frequency of the High pass filter = 1/2 RC.
R
V
g
= V
i
R + X
c
R
V
o
= A
R + 1/jC
1
V
o
= A
1 + 1/jRC
1
V
o
= A
1 + 1/j2 f RC
A
V
o
=
1 j f
L /
f
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 80
BY VIDYA SAGAR.P
Transfer function of High pass filter is given as H (s) = V
o
/ V
i
CIRCUIT DIAGRAM:
Vo
1
2
3 6
3
741 OP-AMP
Vi
C=0.01 Micro F
Rf
Ri
R
A
H (s) =
1 j f
L /
f
A
H (s) =
1 j f
L /
f
Magnitude is given by
H (s) =20 log A
1 +{f
L /
f}
2
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 81
BY VIDYA SAGAR.P
PROCEDURE:
1. Insert the Op-Amp IC 741 into the breadboard correctly.
2. Connect the power supply to the pin 7 with a positive voltage of 15 V
and ground the other.
3. Connect the 2nd power supply negative voltage of 15 V to the pin 4 and
ground the positive terminal.
4. The inverting terminal pin 2 is grounded through a resistor R
i
.
5. A resistor R
f
is connected in feedback path between the pin 2 and 6.
6. A Capacitor C is connected between the input signal source ( Function
generator) and the inverting terminal pin 2 of the Op-Amp
7. A Resistor R is connected between pin 2 and other end is grounded.
8. Take output at pin6.
9. Apply a sine wave of any frequency between 5 to 10 K Hz from
function generator.
10. Observe the output waveform of High pass filter on CRO.
11. Decrease the frequency from 10 KHz to 1 K Hz in steps of 1 KHz as
shown in table and note down the output waveform amplitude and
tabulate these values.
12. From the above tabulated values, draw graph between frequency and
output voltage.
13. From the graph it is observed that lower cut off frequency f
L
is between
1 KHz
to 2 K Hz.
14. Compare the observed lower cutoff frequency from graph with the
theoretical lower cut off frequency.
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 82
BY VIDYA SAGAR.P
OBSERVATIONS:
CALCULATIONS:
i. Choose a standard value of Capacitor C say 0.1 F.
Then R=
fC t 2
1
=
6 3
10 1 . 0 10 1 2
1
x x x x t
= 1.6k
ii.A
o
=1+
1
R
RF
=5
R
f
=4R
1
Choose a value of 10k for R
1
Then R
f
= 40 k
GRAPH:
Sl.No Input frequency Output voltage Gain 20 log Vo/Vi
1. 100
2 200
3 500
4. 1kHz
5. 1.5KHz
6. 2.0kHz
7. 5kHz
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 83
BY VIDYA SAGAR.P
RESULT:
The lower cutoff frequency of the high-pass filter = ------- KHz.
The pass band gain = -------
INFERENCE:
i. The working of active high pass filter is observed and the output is plotted.
ii. The frequency response of the high pass filter is plotted on a semi-log graph
paper.
iii. It is observed that the gain increases at the rate of 20dB per decade at the
cut of frequency.
REVIEW QUESTIONS
i.Define Bessel , Butterworth and Chebyshev filters, and compare their
response.
ii.What are the important parameters of a band pass filter?
iii.Define Notch filter.
iv.How do we get a notch filter from a band pass filter?
v.Define state variable filter.
vi.What is switched capacitor ?
vii.Discuss the importance of switched capacitors.
viii.Give the circuit of a switched capacitor low pass filter
ix.Discuss the advantages of active filters
x.What is the roll-off rate of second order filter?
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 84
BY VIDYA SAGAR.P
3. FUNCTION GENERATOR USING OP AMPS.
AIM: Study the Function generator circuit and generating square and triangular
waveforms using IC-741 Op- Amp.
APPARATUS REQUIRED:
Components: 1. IC 741 Op-Amp --- 2 nos.
2. Capacitors ----- 0.01 F, 0.1 F
3. Resistors ------ 68 K & 100 K---3 nos.
Equipment: 1. CRO
2. Bread board.
3. Power supply.
THEORY:
A Function generator is a circuit that provides Square wave and a
Triangular wave output signal.
Square wave generator:
A constant amplitude squarewave generator using IC 741 Op-Amp is shown in
Fig. The inverting terminal is grounded through a capacitor. A resistor is
connected in feed back path. A potentiometer is connected between output and
ground. The inverting terminal is connected between the potentiometer circuit as
shown.
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 85
BY VIDYA SAGAR.P
1
2
3
OP-AMP 741
C
100nF
R1
100kohm
A B
T
G
XSC1
R2 100kohm
R3 68kohm
When ever power is applied to this circuit Op-Amp is forced to operate in
saturation region. The output of Op-Amp is forced to swing respectively between
positive saturation and negative saturation (-V
EE
). The output of Op-Amp is a
square wave. It is also known as Astable multivibrator.
Triangular waveform Generator:
The Triangular waveform generator can be constructed using two Op-Amps as
shown in fig, here the first Op-Amp acts as an Astable multivibrator that produces
a square wave output. The second Op-Amp is an integrator, which converts the
square wave into a triangular waveform. The output of Op-Amp is connected to
the inverting terminal of the 2
nd
Op-amp through a resistor (100 K). The
noninverting terminal is grounded. A capacitor C=0.1F is connected in feed back
path as shown. The square wave input charges and discharges the capacitor.
6
3
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 86
BY VIDYA SAGAR.P
1
2
3
OP-AMP 741
C
100nF
R1
100kohm
R2 100kohm
R3 68kohm
1
2
3
OP-AMP 741
R
100kohm
C2
100nF
A B
T
G
XSC2
When the negative half cycle or squire is applied to non-inverting
terminal, the output of op-amp-2 starts rising linearly at the rate of I/C V/sec. Here
I is current determined by input resistor (100 K). As a consequence the bias
voltage at positive input of op-amp 1 also rises and when it crosses the zero volt
level the output of OP-Amp-1 rises to fully positive value (i.e. During positive half
cycle). Now the capacitor starts discharging at the same rate linearly till the
positive voltage crosses zero level. The cycle repeats continuously. The amplitude
of triangular waveform depends on the ratio of 68 K and 100 K.
MODEL WAVEFORMS:
V
o1
t
t
V
o2
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 87
BY VIDYA SAGAR.P
PROCEDURE:
1. Connect the circuit as shown in the fig to generate a square wave.
2. Connect the CRO probe between output terminal and ground of OP-AMP
1.
3. Observe the waveform on CRO, which is a square wave.
4. Now connect the circuit at the output of OP-AMP1 to generate the
Triangular waveform.
5. Connect the CRO probe between output terminal of OP-AMP 2 and
ground.
6. Observe the waveform on CRO, which is a Triangular wave.
7. Plot the waveforms on graph sheets and calculate the time period and
frequency of the waveforms theoretically and practically.
RESULT:
The Square and Triangular waveforms are generated and calculated their
frequencies and amplitudes.
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 88
BY VIDYA SAGAR.P
4. MULTI-VIBRATORS
EXPERIMENT NO 1: 555 TIMER-ASTABLE MULTI-VIBRATOR
AIM:
To design and test astable multi-vibrator with fixed and adjustable duty cycle.
EQUIPMENTS AND COMPONENTS:
APPARATUS
1. DC power supply - 1 No.
2. CRO - 1 No.
3. Bread Board - 1 No.
COMPONENTS:
1. 3.62 k Resistor 1 No.
2. 7k Resistor 1 No.
3. 0.1 F Capacitor 1 No
3. IC555 - 1 No.
4. Diode 1 No.
THEORY:
IC 555 Timer
IC-555 Timer is a versatile Monolithic timing circuit that can produce accurate
and highly stable time delays or oscillations. It can be used as an Astable and
Monostable multivibrators. It is available as an 8- pin mini DIP-package.
IC Timer 555 as a Monostable Multivibrator
Monostable Multivibrator has only one stable state. We can change the stable
state by applying a trigger pulse. The capacitor charges through R. The larger
the time constant RC, the longer it takes the capacitor voltage to reach 1/3 V
CC
.
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 89
BY VIDYA SAGAR.P
The time constant controls the pulse width. After the time period given by R
and C elements the circuit goes back to its stable state. Even the trigger pulse is
removed in between still the circuit will not comeback to its stable state until
its time period is reached..
CIRCUIT DIAGRAM:
Ra = 560 Ohm
0.1 Micro F
Rb = 100 K Ohm
0.1 Micro F
555
A B
T
G
+ Vcc = 15 V
CRO
2
6
7
8
4
3
5
1
Trigger
Input
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 90
BY VIDYA SAGAR.P
PROCEDURE:
1. 1. The pulse width design equation is T=1.1RC sec. If T = 0.1msec, choose
R=10k and C=0.01F.
2. Keep the connections as shown in figure-1.
3. A trigger circuit consisting of a differentiator and a diode connected as
shown.
4. A square wave input is applied to this circuit from astable multivibrator
whose output is spikes and the diode will remove the positive spikes.
5. The output of the trigger circuit is applied at the trigger input of the
monostable multivibrator at pin 2.
6. The input and output waveforms are observed on the CRO.
7. The control pin-5 input is grounded through a capacitor 0.01 F, this
provides noise filtering for control voltage.
8. The time period of input square waveform have to be verified from the
input waveform.
9. Observe the output waveform on the CRO and measure the pulse width T
on the CRO and compare with the theoretical value.
10. Observe the output waveform across the capacitor for both Astable and
Monostable operations and note down the corresponding amplitudes.
OBSERVATIONS:
1.t
ON
= 69 (R
A
+ R
B
) C
2.t
OFF
= 0.69 R
B
C
3. 100 % x
t t
t
Dutycycle
OFF ON
ON
+
=
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 91
BY VIDYA SAGAR.P
CALCULATIONS:
i. Design of astable multi-vibrator of 1 kHz with a 75% duty cycle
t
ON
= 69 (R
A
+ R
B
) C
t
OFF
= 0.69 R
B
C
100 100 % x
T
t
x
t t
t
Dutycycle
ON
OFF ON
ON
=
+
=
Where T = 1/f, the time period of the output waveform
T= 1msec, t
ON
= 0.75 m/sec, t
OFF
0.25msec
Lec C = 0.1 F
R
B
= 3.62 k O
Choose R
B
= 1.8 k O + 1.8 kO
c R R T
f
B A
) 2 (
45 . 1 1
+
= = Eq. (1)
ii. Design of astable multivibrator to produce 1 KHz output waveform with
adjustable duty cycle of 10% to 90% The circuit is as shown in Fig. 2 During
the charging period, the diode D is forward biased, R
B
is bypassed Hence t
on
= 0.69 R
A
C. During the discharge period, the discharging transistor is shorted
(ON) and the diode D is reverse biased. Hence t
OFF
= 0.69R
B
C Output
frequency f= 1 KHz is assumed
c R R T
f
B A
) (
45 . 1 1
+
= = Eq. (2)
Let C = 0.1 F
R
A
+ R
B
= 14.5 KO Where t
ON
= 0.1 m/sec (for 10% duty cycle)
R
A
= 1.44 K O When t
ON
= 0.9 m/sec (for 90% duty cycle)
R
A
= 12.96 K O R
A
is to be varied form 1.414 KO to 12.96KO for 10% to
90% duty cycle. Therefore choose R
A
as 1.0 KO fixed resistor + 15.0kO pot,
similarly R
B
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 92
BY VIDYA SAGAR.P
V
i
t
t
V
d
t
V
o
t
V
c
GRAPH:
V
i
Input square wave
V
d
Differentiator output
V
C
Discharge capacitor output
V
O
Output pulse
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 93
BY VIDYA SAGAR.P
RESULT:
t
ON
= 69 (R
A
+ R
B
) C =
t
OFF
= 0.69 R
B
C =
100 100 % x
T
t
x
t t
t
Dutycycle
ON
OFF ON
ON
=
+
= =
INFERENCE:
i. The working of 555 timer astable multivibrator is observed and the output is
plotted.
ii. The duty cycle is calculated
iii. Frequency of the output wave form is calculated
REVIEW QUESTIONS
i.Explain the functional block diagram of a 555 timer
ii.Explain the function of reset
iii.What are the modes of operation of timer?
iv.What is the expression of time delay of a astable multivibrator?
v.Discuss some applications of timer in astable mode.
vi.Define duty cycle
vii.Give methods of obtaining symmetrical waveform.
viii.How is an astable multivibrator connected into a pulse position modulator
ix.How Schmitt trigger circuit is constructed using 555 timer
x.Draw the pin diagram of 555 timer.
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 94
BY VIDYA SAGAR.P
EXPMENT NO 2: 555 TIMER-MONOSTABLE MULTI-VIBRATOR
AIM:
To design and test monostable multi-vibrator using IC555 Timer.
EQUIPMENTS AND COMPONENTS:
APPARATUS
1. DC power supply - 1 No.
2. CRO - 1 No.
3. Bread Board - 1 No.
4. Function Generator - 1 No.
COMPONENTS:
1. 11.8 k Resistor 1 No.
2. 1k Resistor 1 No.
3. 1 F Capacitor 1 No
4. 1 F Capacitor 1 No
5. IC555 - 1 No.
6. 1N4148 Diode 1 No.
THEORY:
The 555 timer can be used with supply voltage in the range of +5 v to +18 v
and can drive upto 200 mAmps. It is compatible with both TTL and CMOS
logic circuits because of the wide range of supply voltage the 555 timer is
versatile and easy to use in monostable multivibrator we will provide external
triggering in order to make the timer to switch over to high state (unstable).
This is also called as one-short multivibrator.
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 95
BY VIDYA SAGAR.P
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect the circuit using the component values as per the design
2. Set the square wave 2.5V peak and 1KHz trigger input on function
generator
3. Apply the trigger input at pin-2 through capacitor C1. Observe both trigger
input and the output of the multivibrator on CRO simultaneously and
sketch the waveforms
4. Repeat the step 3 for trigger input of 2KHz frequency
OBSERVATIONS:
1 T
P
= 1.1 R.C. = 1.3 m/sec
2. T = 1/ f = 1m/sec
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 96
BY VIDYA SAGAR.P
CALCULATIONS:
i. To produce a pulse of 1.3 m/sec duration:
T
P
= 1.3mSec
T
P
= 1.1 R.C.
Let C = 0.1 F
R = 11.8KO
To provide negative edge triggering a circuit of fig.2 is to be connected
between pin 2 and 8.
Design of Differentiator:
Let the trigger input frequency is 1KHz
i.e., T = 1/f = 1mSec
Assume t
1
= R
1
C
1
= 0.01mSec
Let C = 0.01 F
Therefore R
1
= 1.0 KO
GRAPH:
RESULT:
T
p
= 1.1R.C. =
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 97
BY VIDYA SAGAR.P
INFERENCE:
i. The working of 555 timer monostable multivibrator is observed and the
output is plotted.
ii. The time period of the output waveform is calculated
iii. Frequency of the output wave form is calculated
REVIEW QUESTIONS
i. Explain the functional block diagram of a 555 timer
ii. Explain the function of reset
iii. What are the modes of operation of timer?
iv. What is the expression of time delay of a monostable multivibrator?
v. Discuss some applications of timer in monostable mode.
vi. Define duty cycle
vii. Give methods of obtaining symmetrical waveform.
viii.How is an monostable multivibrator connected into a pulse position
modulator
ix. How Schmitt trigger circuit is constructed using 555 timer
x. Draw the pin diagram of 555 timer.
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IC&E-CAD LAB
VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 98
BY VIDYA SAGAR.P
5. IC566 VCO
AIM:
To study the operation of NE566 VCO
APPARATUS
1. DC power supply - 1 No.
2. CRO - 1 No.
3. Bread Board - 1 No.
4. Function Generator - 1 No.
COMPONENTS:
1. 6.8 k Resistor 1 No.
2. 15 k Resistor 1 No.
3. 100 k Resistor 1 No.
4. 75 pF Capacitor 1 No
5. IC566 - 1 No.
.
THEORY:
A common type of VCO available in IC form in Stigmatic NE/SE566.
Referring to the circuit diagram a timing capacitor C
T
is linearly charged or
discharged by a constant current source/sink. The amount of current can be
controlled by changing the voltage v
c
applied at the modulating input (pin5) or
by changing the timing resistor R
T
external to IC chip. The voltage at pin 6 is
held at the same voltage as pin 5. Thus, if the modulating voltage at pin5 is
increased, the voltage pin 6 also increases, resulting in less voltage across R
T
and thereby decreasing the charging current.
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VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 99
BY VIDYA SAGAR.P
The voltage across the capacitor CT is applied to the inverting input terminal
of Schmitt Trigger the output voltage swing of the Schmitt Trigger is designed
to Vcc and 0.5 Vcc. The output frequency of the VCO can be calculated as
follows:
The total voltage on the capacitor changes from 0.25 Vcc to 0.5 Vcc. Thus Av
= 0.25 Vcc. The capacitor charges with a constant current source.
So,
T
C
i
t
v
=
A
A
T
C
i
t
Vcc
=
A
25 . 0
At =
i
VccC
T
25 . 0
The time period T of the triangular wave form equal to 2At. The frequency of
oscillator fo is,
fo =
t T A
=
2
1 1
=
T C VccC
i
5 . 0
But i =
T
CC
R
Vc V
Where Vc is the voltage at pin 5. Therefore,
fo =
CC T T
CC
V R C
Vc V ) ( 2
The output frequency of the VCO can be changed either by (i) R
T
, (ii) C
T
are
(iii) The voltage V
C
at the modulating input terminal pin 5. The voltage V
C
can
be varied by connecting a R
1
R
2
circuit.
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VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 100
BY VIDYA SAGAR.P
IV. CIRCUIT DIAGRAM:
V. PROCEDURE:
1) Make connections of the VCO as show in the Circuit diagram.
2) Measure the free running frequency of VCO at Pin 4, with the input signal
V in set = 0. Compare it with the theoretical calculated value.
3) Draw the output wave form obtained at Pin No 3.
4) Draw the output wave form obtained at Pin No 4
5) Compare the theoretical and practical values of free running frequency.
VI. OBSERVATIONS:
fo =
CC T T
CC
V R C
Vc V ) ( 2
= ___________
Output amplitude at Pin 4 = _____________
Output amplitude at Pin 3 = _____________
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VII. CALCULATIONS:
T
C
i
t
v
=
A
A
T
C
i
t
Vcc
=
A
25 . 0
At =
i
VccC
T
25 . 0
The time period T of the triangular wave form equal to 2At. The frequency of
oscillator fo is,
fo =
t T A
=
2
1 1
=
T C VccC
i
5 . 0
But i =
T
CC
R
Vc V
Where Vc is the voltage at pin 5. Therefore,
fo =
CC T T
CC
V R C
Vc V ) ( 2
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VIII. GRAPH:
IX: RESULT:
fo = _________
X: INFERENCE:
i. The working of 566PLL is observed and the output is plotted.
ii. The time period of the output waveform is calculated
iii. Frequency of the output wave form is calculated
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XV REVIEW QUESTIONS
i. List the basic building blocks of a VCO.
ii. Define free running frequency.
Iii .Define lock range
Iv .Explain the block diagram of IC 566 VCO.
v. What is the range of modulating input voltage applied to a VCO?
vi. What is the frequency transfer coefficient of VCO.
vii. List the applications of VCO,
viii. Explain about Schmitt trigger circuit.
Ix .Explain how VCO is used in PLL.
X .Explain the operation of constraint current source.
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6. VOLTAGE REGULATOR USING IC 723.
I AIM:
To study the operation of IC723 voltage regulator
II EQUIPMENTS AND COMPONENTS:
(i).APPARATUS
1. DC power supply - 1 No.
2. Digital Multimeter - 1 No.
3. Ammeter - 1 No.
4. Bread Board - 1 No.
COMPONENTS:
1. 1k Resistor 1 No.
2. 33 Resistor 1 No.
3. 10k Resistor 1 No
4. 680 O Resistor 1 No.
16. 2.2 kO Resistor 1 No.
17. 100 pF Capacitor 1 No
18. IC723
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III. THEORY:
The three-terminal regulators have the following limitations
1. No short-circuit protection
2. Output voltage (+ve or ve) is fixed
These limitations have been overcome in 723 general purpose regulator. This
IC is inherently low current device but can be boosted to provide 5 amps or
more current by connecting external components. The limitation of 723 is that
it has no in-built thermal protection. It also has no short-circuit current limits.
The IC723 has two sections. The first section consists of Zener Diode constant
current source and a reference amplifier. The other section of the IC consists of
an error amplifier series pass transistor and a current limit transistor. This is a
14-pin DIP package. The main
Features of 723 include an input voltage of 40v max, output voltage is
adjustable from 2V to 37V, 150 mA output current without external pass
resistor, can be used as either a linear or a switching regulator.
IV. CIRCUIT DIAGRAM:
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V. PROCEDURE:
1. Connect the 723 regulator as shown in the circuit diagramSet Dc power
supply voltage V
in
to +10V measure and record V
ref
with respect to ground.
With load R
L
(10kO pot) removed from the circuit (output open). Measure
the minimum and maximum output voltage by rotating the 1kO pot through
its full range.
2. Now adjust the 1kO pot so that V
o
is +5V dc. Measure the voltage between
the wiper arm of the 1 kO pot and ground.
3. Adjust the load R
L
(10 kO) pot until the load current I
L
= 1 mA. Record V
L
.
Repeat for different values of load currents 5mA, 10mA, 15mA, 18mA.
Calculate the load regulation and compare with manufacturers
specifications
4. Gradually increase the load current above 18mA, you will see that the load
voltage suddenly decreases when the load current is about 18 to 20 mA.
Now the voltage across R
SC
is enough to begin current limiting. Measure
and record a few values of load current and load voltage below and above
the current limiting point. Plot a graph of V
L
vs I
L
from the data obtained in
steps 4 and 5
VI. OBSERVATIONS:
1. The load regulation = _____ %
2. The line regulation = ______%
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VII. CALCULATIONS:
1. The load regulation can be calculated by using the below formulae
%load regulation = ( (V
fl
V
nl
) / (V
fl
)) * 100
2. The line regulation can be calculated by using the below formulae
%line regulation = ( AV
o
/ AV
i
)
VIII. GRAPH:
IX: RESULT:
i.The % load regulation =
ii. The % line regulation =
X: INFERENCE:
i. The working of 723 regulator is observed and the output is plotted.
ii. The load regulation is calculated
iii. The line regulation is calculated
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XV REVIEW QUESTIONS
i.What is the maximum input voltage that we can give to 723 regulator?
ii.What output voltage range we can obtain from 723 regulator?
iii.What is the output current in case of 723 regulator?
iv.What are the applications of 723 regulator?
v.Define line regulation
vi.Define load regulation
vii.Define ripple rejection
viii.Define long term stability
ix.What is the current limit protection
x.What are the ideal values of load and line regulations
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7. 4 bit DAC using OP AMP.
I AIM:
To construct a 4-bit R 2 R ladde type D/A converter. Plot the transfer
characteristics, that is, binary input vs output voltage. Calculate the resolution
and linearity of the converter from the graph.
II EQUIPMENTS AND COMPONENTS:
(i).APPARATUS
1. DC power supply - 1 No.
2. CRO - 1 No.
3. Bread Board - 1 No.
4. Function Generator - 1 No.
COMPONENTS:
1.10 k Resistor 1 No.
2.20 kO Resistor 1 No.
3.IC741 - 1 No.
.Bandwidth adjustment range = < 1 to 60%
III. THEORY:
Most of the real world physical quantities such as voltage current temperature
pressure are available in analog form. It is very difficult to process the signal in
analog form, hence ADC and DAC are used.
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The DAC is to convert digital signal into analog and hence the functioning of
DAC is exactly opposite to that of ADC. The DAC is usually operated at the
same frequency as the ADC. The output of the DAC is commonly staircase.
This staircase like digital output is passed through a smoothing filter to reduce
the effect of quantization noise. There are three types of DAC techniques (i)
Weighted resistor DAC (ii) R-2R ladder. (iii) Inverted R-2R ladder. Wide
range of resistors is required in binary weighted resistor type DAC. This can be
avoided by using R-2R ladder type DAC where only two values of resistors are
required it is well suited for integrated circuit realization.
IV. CIRCUIT DIAGRAM:
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V. PROCEDURE:
i. Set up the circuit shown in Fig.
ii. With all inputs (d
0
to d
3
) shorted to ground, adjust the 20 kO pot until the
output is 0V. This will nullify any offset voltage at the input of the op-amp.
Iii ..Measure the output voltage for all binary input states (0000 to 1111) and plot
a graph of binary inputs vs output voltage.
iv. .Measure the size of each step and hence calculate resolution
v. .Calculate linearity
VI. OBSERVATIONS:
Output Voltage = ____________
Size of each step = ____________
Resolution = ____________
Linearity = ____________
VII. CALCULATIONS:
V
O
= V
R
/ 2 = V
FS
/ 2
Resolution (in volts) = V
FS
/ (2
n
1) = 1 LSB increment.
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VIII. GRAPH:
.
IX: RESULT:
Output Voltage = ____________
Size of each step = ____________
Resolution = ____________
Linearity = ____________
X: INFERENCE:
i. The working of D / A converter is observed and the output is plotted.
ii. The staircase wave form is plotted.
iii. Resolution is calculated.
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XV REVIEW QUESTIONS
i. Classify DAC on the basis of their output.
ii. Name the essential parts of a DAC.
iii. Describe the various types of electronic switches used in DAC.
vi. How many resistors are required in 12 bit weighted resistor DAC?
v. Why is an inverted R-2R ladder network DAC is better than R-2R ladder
DAC.
vi. Define resolution.
vii. Define linearity.
Viii .Define monotonicity.
Ix .Define step size.
x. Define settling time.
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