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Apuntes de Clase PIC
Apuntes de Clase PIC
Apuntes de Clase PIC
I. CARACTERISTICAS
4. Peripheral Features
Timer0: 8-bit timer/counter with 8-bit 12 I/O pins with individual direction control programmable prescaler High current sink/source for direct LED Enhanced Timer1: drive - 16-bit timer/counter with prescaler Analog comparator module with: - External Gate Input mode - One analog comparator - Option to use OSC1 and OSC2 in LP mode - Programmable on-chip comparator as Timer1 oscillator, if INTOSC mode voltage reference (CVREF) module selected - Programmable input multiplexing In-Circuit Serial Programming (ICSP) via from device inputs two pins - Comparator output is externally accessible Analog-to-Digital Converter module (PIC16F676): - 10-bit resolution - Programmable 8-channel input - Voltage reference input
PIC16F630/676
II.Diagrama de Patillas
14-pin PDIP, SOIC, TSSOP
Arquitectura Interna
Descripcin de Patillas
Descripcin de Patillas
Descripcin de Patillas
III.ORGANIZACIN DE MEMORIA
Memoria Programa
The PIC16F630/676 tiene un Contador de programa PC de 13-bit con capacidad de direccionar 8K x 14 . Solo los primeros 1K x 14 (0000h - 03FFh) son implementados
Memoria data
IV Listado de Instrucciones
Numero hexadecimal Numero binario : 0xhh : 00010000b
Se agrupan en 3 categorias:
Byte-oriented operations Bit-oriented operations Literal and control operations
Listado de Instrucciones
Port A,C
TIMER 0
The Timer0 module timer/counter has the following features: 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock
Timer0-External Clock
TMR0 Interrupt
The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut-off during SLEEP
INTERRUPCIONES
MICROCHIP Familia Mid-Range
Logica de interrupcin
LATENCIA DE INTERRUPCION
HABILITACION DE INTERRUPCIONES
TIMER 1
Timer1 has the following features: 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt on overflow from FFFFh to 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input (T1G) Optional LP oscillator
MODULO COMPARADOR
The PIC16F630/676 devices have one analog comparator.The inputs to the comparator are multiplexed with the RA0 and RA1 pins. There is an on-chip Comparator Voltage Reference that can also be applied to an input of the comparator. In addition, RA2 can be configured as the comparator output.
Operacin de Comparacion
Configuracion de Modos
CM<2:0> CIS - ref + ref Output Description 000 001 010 011 100 101 101 110 110 111 0 1 0 1 CINCINCINCINCINCINCIN+ CINCIN+ (none) CIN+ CIN+ CIN+ CVREF CVREF CVREF CVREF CVREF CVREF (none) off external internal external internal external external internal internal off Off with inputs connected (default) Both inputs, external output Both inputs, internal only Negative input vs. reference, external output Negative input vs. reference, internal only Negative input vs. reference, external output Positive input vs. reference, external output Negative input vs. reference, internal only Positive input vs. reference, internal only Off with inputs disconnected (lowest power)
Note: 1)Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur. 2) Comparator mode is changed, the comparator output level may not be valid for a specified period of time. Refer to the specifications in Section 12.0.
Entrada analgica
Consideracion: La entrada analgica, debe estar entre VSS y VDD , considerar circuitos de proteccin externa
Comparator Reference
El comparador permite seleccionar una referencia interna El registro VRCON controla este modulo La tensin de referencia puede dar salida a 32 distintos niveles de tension,16 en un rango de alta y 16 en un rango bajo.
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.000 0.042 0.083 0.125 0.167 0.208 0.250 0.292 0.333 0.375 0.417 0.458 0.500 0.542 0.583 0.625 0.00V 0.21V 0.42V 0.62V 0.83V 1.04V 1.25V 1.46V 1.67V 1.87V 2.08V 2.29V 2.50V 2.71V 2.92V 3.12V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0.250 0.281 0.313 0.344 0.375 0.406 0.438 0.469 0.500 0.531 0.563 0.594 0.625 0.656 0.688 0.719
1.25V 1.41V 1.56V 1.72V 1.88V 2.03V 2.19V 2.34V 2.50V 2.66V 2.81V 2.97V 3.13V 3.28V 3.44V 3.59V
Effects of a RESET
Un RESET obliga a CMCON y VRCON a resetear sus estados. Esto obliga al modulo comparador a ir al modo RESET, CM2: CM0 = 000 y al voltage reference a su estado de apagado. Por lo tanto, con todas las posibles entradas analgicas y voltage reference desabilitadas da como resultado el menor consumo de corriente.
Comparator Interrupts
El Flag de interrupcion del comparador se activa cada vez que hay un cambio en el valor de salida del comparador. PIR1 <3>, es la bandera de interrupcin del comparador. Este bit deber limpiarse a cero. Puesto que tambin es posible escribir un '1 'en este registro, una interrupcion simulada puede ser iniciada. Ademas deben habilitarse GIE,PEIE,PIE(CMIE) Para limpiar la Interrupcion hay 2 maneras a) Cualquier lectura o escritura de CMCON. Esto pondr fin a la condicin Mismatch. b) limpiar flag bit CMIF
NOTE: If a change in the CMCON register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR1<3>) interrupt flag may not get set.
ADC
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC16F676 has eight analog inputs, multiplexed into one sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. Figure 7-1shows the block diagram of the A/D on the PIC16F676. TAD es el tiempo de conversion para un bit, una completa conversion de 10 bits requiere 11 TAD ya se usa un TAD al inicio de la conversion.
Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be performed during SLEEP. ADCS<2:0> conversion clock TAD 000 FOSC / 2 TCY / 2 001 FOSC / 8 TCY 2 010 FOSC / 32 TCY 8 1.6 s 9 s 011 FRC 100 FOSC / 4 TCY 101 FOSC / 16 TCY 4 110 FOSC / 64 TCY 16 111 FRC 1.6 s 9 s
For accurate conversions, the conversion clock must be selected such that TAD is at least 1.6 s.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Secuencia de Conversin
To calculate the minimum acquisition time, Equation 7-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution.
Effects of RESET
A device RESET forces all registers to their RESETstate. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged.
Operacin
La memoria EEPROM permite lectura y escritura de bytes . Una escritura de byte borra automticamente la ubicacin y escribe los nuevos datos (borrando antes de escribir). La memoria EEPROM est diseado para borrar de alta erase/write cycles. El tiempo de escritura est controlada por un temporizador en el chip. El tiempo de escritura puede variar con el voltaje y la temperatura, as como de chip en chip. Por favor, consulte las especificaciones de CA para lmites exactos. When the data memory is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer accessthis memory.
EEDAT REGISTER
EEADR REGISTER
EECON2 is not a physical register. Reading EECON2will read all '0's. The EECON2 register is used exclusively in the Data EEPROM write sequence.
LECTURA DE EEPROM
Para leer una posicin de memoria , el usuario debe escribir la direccin en el registro EEADR y a continuacin, setear el bit de control RD (EECON1 <0>), como se muestra en el ejemplo 8-1. Los datos estan disponibles, en el ciclo siguiente, en el registro EEDATA. Por lo tanto, se puede leer en el siguiente instruccin. EEDATA mantiene este valor hasta que otra lectura, o hasta que este es escrito por el usuario (durante una operacin de escritura).
Escritura de EEPROM
Para escribir una posicin de memoria , el usuario debe escribir la direccin en el registro EEADR y el dato en EEDATA. Entonces el usuario debe seguir una secuencia especifica para iniciar la escritura para cada Byte,como muestra el ejemplo 8-2. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit (PIR<7>) register must be cleared by software.
Interrupts Watchdog Timer (WDT) SLEEP Code protection ID Locations In-Circuit Serial Programming
Configuration Bits
EEPROM FLASH
NO SE HABILITA AUTOMATICAMENTE
A.-TIPOS DE OSCILADORES
LP Low Power Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor (2 modes) INTOSC Internal Oscillator (2 modes) EC External Clock In
When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin
2. RC OSCILLATOR
Para aplicaciones donde no es necesario que el tiempo sea preciso. Two options are available for this Oscillator mode which allow RA4 to be used as a general purpose I/O or to output FOSC/4. La frecuencia del oscilador depende de: - Supply voltage - Resistor (REXT) and capacitor (CEXT) values - Operating temperature - Vary from unit to unit( especialmente para valores pequeos de CEXT Tolerance of the external R and C components
B. RESET
Tipos de reset a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during SLEEP d) MCLR Reset during normal operation e) MCLR Reset during SLEEP f) Brown-out Detect (BOD)
1.RESET EXTERNO
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or Wake-up from SLEEP.
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked after POR has expired. Then, OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no timeout at all. Figure 9-7, Figure 9-8 and Figure 9-9 depict timeout sequences.
WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. External RESET input on MCLR pin 2. Watchdog Timer Wake-up (if WDT was enabled) 3. Interrupt from RA2/INT pin, PORTA change, or a peripheral interrupt.
SLEEP
When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h) In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction.