BASIC VHDL PROGRAMMING USING XILINX FPGA

Ex. no: Date: Aim:

To simulate the basic programs in VHDL using Xilinx ISE Spartan 3A software and verify it using fpga trainer kit.

Procedure:
1. Open file->new project->give the project name and location to store it 2. Click next 3. Details of the software are opened selected the preferred language as VHDL/verilog and click next->finish 4. Right click the project->new source->VHDLmodule->give the project name which is created in step1.click next. 5. Then declare the inputs and output. 6. Click next->finish. 7. Program is created now the main line routine is typed and save the program 8. On the left side a tab is open double click synthesize 9. After synthesize is completed successfully we have to create a test bench for simulation. 10. Select simulation in the top left corner and right click the project->new source>VHDL/verilog test bench->give name for test bench->click next->finish 11. Test bench is created. 12. Select the test bench go to ISIM simulator->double click the simulate behavioral model 13. By changing the inputs in the test bench the required output is simulated. 14. Load the program in Xilinx Spartan ISE trainer with suitable output ports and verify the result.

VHDL programs: 1. AND gate:

Entity and _1is Port(a:in std_logic; B:in std_logic; C:out std_logic;); End and_1; Architecture behavioral of and-1is Begin C<=a and b; End behavioral;

2. OR gate:
Entity or_1is Port(a:in std_logic; B:in std_logic ; C:out std_logic;); End or_1; Architecture behavioral of or_1is Begin C<=a or b; End behavioral;

3. XOR gate:
Entity xor_1is Port(a:in std_logic; B:in std_logic ; C:out std_logic;); End xor_1; Architecture behavioral of xor_1is Begin C<=a xor b; End behavioral;

4. HALF ADDER gate:

Entity half_adder 1is Port(a:in std_logic; B:in std_logic; Sum:out std_logic; Carry:out std_logic;); End half_adder1; Architecture behavioral of half_adder1is Begin Sum<=a xor b; Carry<=a and b; End behavioral;

5. FULL ADDER gate:

Entity full_adder1is port(a:in std_logic; B:in std_logic; C:in std_logic; Sum:out std_logic; Carry: out std_logic;); End full_adder1; Architecture behavioral of full_adder1is Begin Sum<=(a and (((not b) and (not c) or (b and c)) ore ((not a) and (((not b) and c) or (b and(not c))));

Carry<=(b and c) or (a and b) or (a and (not b)and c); End behavioral;

6. MUX gate:
Entity mux_1 is; Port (a:in std_logic; B: in std_logic; C: in std_logic; D: in std_logic; X: in std_logic; Y: in std_logic; Op: outstd_logic;); End mux_1;

Architecture behavioral of mux_1 is Begin Op<=(((not x) and (not y) and a) or ((not x)and y and b ) or (x and (not y)and c) or (a and y and d)); End behavioral;

7. DEMUX gate:
Entity demux_1 is; Port (x: in std_logic; y: in std_logic; e: in std_logic; i: in std_logic; a: out std_logic; b: out std_logic; c: out std_logic; d: out std_logic;); End demux_1; Architecture behavioral of demux_1 is Begin A<=(a and I and((not x) and (not y))); B<=(a and I and ((not x) and y)); C<=(e and I and (a and(not y))); D<=(e and I (x and y)); End behavioral;

Result:
Thus the basic programs in VHDL was simulated by using Xilinx Spartan ISE 3A software and verified in fpga trainer kit.