Case: 13-1339

Document: 18-1

Page: 1

Filed: 06/18/2013

2013-1339 (Reexamination Nos. 95/000,178 and 95/001,152)

IN THE

UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT ___________ RAMBUS, INC., v. MICRON TECHNOLOGY, INC., ___________

Appellant,

Appellee.

Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board. ___________ BRIEF FOR APPELLANT RAMBUS INC. ___________ J. Michael Jakes James R. Barney Molly R. Silfen Aidan C. Skoyles FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 June 18, 2013

Attorneys for Appellant Rambus Inc.

Case: 13-1339

Document: 18-1

Page: 2

Filed: 06/18/2013

CERTIFICATE OF INTEREST Pursuant to Federal Circuit Rules 27(a)(7) and 47.4(a), counsel for Appellant Rambus Inc. certify the following: 1. The full name of every party or amicus represented by us is: Rambus Inc. 2. The name of the real party in interest (if the party named in the caption is not the real party in interest) represented by us is: Rambus Inc. 3. All parent corporations and any publicly held companies that own 10 percent or more of the stock of any party represented by us are: None 4. The names of all law firms and the partners or associates that appeared for the parties now represented by us in the trial court or are expected to appear in this Court are: J. Michael Jakes, Kathleen Daley, James R. Barney, Naveen Modi, Molly R. Silfen, Aidan C. Skoyles FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP

Case: 13-1339

Document: 18-1

Page: 3

Filed: 06/18/2013

TABLE OF CONTENTS Table of Authorities ...................................................................................................v Statement of Related Cases ..................................................................................... vii Statement of Jurisdiction............................................................................................1 I. II. III. Statement of the Issues ....................................................................................2 Statement of the Case ......................................................................................2 Statement of Facts............................................................................................3 A. B. Claim 33 of the 120 Patent...................................................................4 Background of the Technology-at-Issue ...............................................5 1. 2. 3. 4. C. D. Dynamic Random Access Memory ............................................5 Asynchronous Versus Synchronous DRAM Chips ...........................................................................................7 Prior Cases Involving Synchronous Memory Devices ......................................................................................9 Precharging of Sense Amplifiers ..............................................11

The Unrebutted, Objective Evidence of Nonobviousness ..................18 The Prior Art-at-Issue..........................................................................19 1. Primary References ...................................................................20 a. b. c. 2. Bennett ............................................................................20 iAPX ...............................................................................21 iRAM ..............................................................................22

Secondary References ...............................................................22 a. b. Olson ...............................................................................23 Wicklund.........................................................................23 ii

Case: 13-1339

Document: 18-1

Page: 4

Filed: 06/18/2013

c. E.

Bowater ...........................................................................24

The Proceedings Below .......................................................................25 1. The Examiners Determination of Nonobviousness .................25 a. The Examiner Found in This Proceeding and in a Related Proceeding that the Cited Prior Art Does Not Disclose or Render Obvious an Operation Code Containing Both a Read Instruction and Precharge Information ....................................................25 The Examiner Found that the Cited Prior Art Does Not Disclose or Render Obvious a Synchronous DRAM ............................................................................31

b.

2.

The Boards Reversal of the Examiners Decision Confirming Claim 33 ................................................................36 a. The Board Construed Precharge Information as Nonfunctional Descriptive Material and Rejected the Examiners Findings Regarding Precharging .....................................................................36 The Board Reversed the Examiners Findings Regarding the Nonobviousness of Synchronous DRAMs in 1990..............................................................38

b.

IV. V.

Summary of Argument ..................................................................................44 Argument .......................................................................................................45 A. Standards of Review............................................................................45 1. 2. Claim Construction Is Reviewed de Novo ...............................45 Factual Findings of the Board Are Reviewed for Substantial Evidence Based on the Entire Record, Including Any Findings of Fact Made by the Examiner ...................................................................................46 The Board Cannot Simply Rely on Its Own Expertise; It Must Point to Concrete Evidence in the iii

3.

Case: 13-1339

Document: 18-1

Page: 5

Filed: 06/18/2013

Record to Support Its Findings ...............................................47 4. B. The Boards Ultimate Conclusion of Obviousness Is Reviewed de Novo ....................................................................48

The Board Erred in Construing Precharge Information in Claim 33 as Nonfunctional Descriptive Material that Need Not Be Shown in the Prior Art ..................................................48 The Boards Alternative Determination that an Operation Code Containing Both a Read Instruction and Precharge Information Would Have Been Obvious in 1990 Lacks Substantial Evidence ...........................................................................51 The Board Erred in Finding, Without Any Prior-Art Examples of Synchronous DRAMs, that Synchronous DRAMs Would Have Been Obvious Based on Bennett or iAPX in View of iRAM ......................................................................60

C.

D.

VI.

Conclusion .....................................................................................................67

iv

Case: 13-1339

Document: 18-1

Page: 6

Filed: 06/18/2013

TABLE OF AUTHORITIES Cases Page(s)

AstraZeneca LP v. Apotex, Inc, 633 F.3d 1042 (Fed. Cir. 2010) ..........................................................................50 Bicon, Inc. v. Straumann Co., 441 F.3d 945 (Fed. Cir. 2006) ............................................................................50 Brand v. Miller, 487 F.3d 862 (Fed. Cir. 2007) .................................................................... passim Comark Communications, Inc. v. Harris Corp., 156 F.3d 1182 (Fed. Cir. 1998) ..........................................................................51 Gechter v. Davidson, 116 F.3d 1454 (Fed. Cir. 1997) ..........................................................................46 Graham v. John Deere Co., 383 U.S. 1 (1966) ................................................................................................64 In re Baker Hughes Inc., 215 F.3d 1297 (Fed. Cir. 2000) ..........................................................................45 In re Gartside, 203 F.3d 1305 (Fed. Cir. 2000) ..........................................................................46 In re Glatt Air Techniques, Inc., 630 F.3d 1026 (Fed. Cir. 2011) ..........................................................................60 In re Gulack, 703 F.2d 1381 (Fed. Cir. 1983) ..........................................................................48 In re Gurley, 27 F.3d 551 (Fed. Cir. 1994) ..............................................................................54 In re ICON Health & Fitness, Inc., 496 F.3d 1374 (Fed. Cir. 2007) ..........................................................................48 In re Lowry, 32 F.3d 1579 (Fed. Cir. 1994) ............................................................................50

Case: 13-1339

Document: 18-1

Page: 7

Filed: 06/18/2013

In re Ngai, 367 F.3d 1336 (Fed. Cir. 2004) ................................................................... 48, 50 In re NTP, Inc., 654 F.3d 1279 (Fed. Cir. 2011) ....................................................... 48, 64, 66, 67 In re Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012) ..........................................................................9, 10 In re Zurko, 258 F.3d 1379 (Fed. Cir. 2001) ..........................................................................47 Panduit Corp. v. Dennison Manufacturing Co., 810 F.2d 1561 (Fed. Cir. 1987) ..........................................................................50 Pozen Inc. v. Par Pharmaceutical, Inc., 696 F.3d 1151 (Fed. Cir. 2012) ..........................................................................54 St. Clair Intellectual Property Consultants, Inc. v. Canon Inc., 412 F. Appx 270 (Fed. Cir. 2011) .....................................................................47 Tandon Corp. v. U.S. International Trade Commission, 831 F.2d 1017 (Fed. Cir. 1987) ..........................................................................51 Universal Camera Corp. v. National Labor Relations Board, 340 U.S. 474 (1951) ............................................................................................47 Warner-Jenkinson Co. v. Hilton Davis Chemical Co., 520 U.S. 17 (1997) ..............................................................................................50 Statutes 35 U.S.C. 141 ..........................................................................................................1

vi

Case: 13-1339

Document: 18-1

Page: 8

Filed: 06/18/2013

STATEMENT OF RELATED CASES Rambus is unaware of any other appeals or petitions taken in this reexamination proceeding. There are, however, a number of different matters pending in this Court and other courts that involve the patent-at-issue in this appeal, U.S. Patent No. 6,324,120 (the 120 patent). 1. The following pending case involves the 120 patent. a. Rambus Inc. v. Hynix Semiconductor Inc., No. 5:05-cv-00334-

RMW (N.D. Cal.) (Whyte, J.). 2. The following pending cases do not involve the 120 patent but

involve patents that, like the 120 patent, descend from Application No. 07/510,898 (the 898 application). a. Hynix Semiconductor Inc. v. Rambus Inc., No. 5:00-cv-20905-

RMW (N.D. Cal.) (Whyte, J.). This case is on remand from Appeal Nos. 20091299, -1347, 645 F.3d 1336 (Fed. Cir. 2011). b. Micron Technology, Inc. v. Rambus Inc., No. 1:00-cv-00792-

SLR (D. Del.) (Robinson, J.). This case is on remand from Appeal No. 2009-1263, 645 F.3d 1311 (Fed. Cir. 2011). c. (Seeborg, J.). Rambus Inc. v. LSI Corp., No. 3:10-cv-05446-RS (N.D. Cal.)

vii

Case: 13-1339

Document: 18-1

Page: 9

Filed: 06/18/2013

d.

Rambus Inc. v. Micron Technology, Inc., No. 5:06-cv-00244-

RMW (N.D. Cal.) (Whyte, J.). e. Rambus Inc. v. STMicroElectronics, N.V., No. 3:10-cv-05449-

RS (N.D. Cal.) (Seeborg, J.). 3. Several ex parte and inter partes reexaminations involving patents

descended from the 898 application are pending at the U.S. Patent and Trademark Office (PTO). Of those, the following have been appealed to this Court. a. 2012). b. Rambus, Inc. v. Rea, No. 2012-1634 (Fed. Cir.) (oral argument In re Rambus Inc., No. 2011-1247, 694 F.3d 42 (Fed. Cir.

set for July 11, 2013). c. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1087

(Fed. Cir.) (briefing not yet complete). d. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1192

(Fed. Cir.) (briefing not yet complete). e. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1224

(Fed. Cir.) (docketed). f. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1228

(Fed. Cir.) (docketed).

viii

Case: 13-1339

Document: 18-1

Page: 10

Filed: 06/18/2013

g.

Rambus, Inc. v. Micron Technology, Inc., No. 2013-1426

(Fed. Cir.) (docketed).

ix

Case: 13-1339

Document: 18-1

Page: 11

Filed: 06/18/2013

STATEMENT OF JURISDICTION This appeal arises from two inter partes reexamination proceedings before the U.S. Patent and Trademark Office (PTO). Micron Technology, Inc.

(Micron), one of the requesters, appealed the examiners confirmation of the sole claim-at-issue to the Patent Trial and Appeal Board (Board). The Board

reversed the examiners confirmation of the claim on January 19, 2012. The parties requested rehearing, and the Board issued a final and appealable decision on January 8, 2013. 35 U.S.C. 141. Rambus appealed. This Court has jurisdiction under

Case: 13-1339

Document: 18-1

Page: 12

Filed: 06/18/2013

I.

STATEMENT OF THE ISSUES 1. Did the Board err in reversing the examiners decision confirming

claim 33, where the claim requires use of an operation code that includes both a read instruction and precharge information, where the Board ignored and dismissed the precharge limitation as nonfunctional descriptive material, and where the examiner correctly found in this proceeding and in a related proceeding that the cited prior art does not disclose the operation-code-including-precharge limitation or render it obvious? 2. Alternatively, did the Board err in reversing the examiners decision confirming claim 33, where the examiner correctly found that neither Bennett nor the combination of iAPX and iRAM would have rendered obvious a synchronous dynamic random access memory device (synchronous DRAM), where the cited prior art discloses, at most, only conventional asynchronous DRAMs, and where the Board cited no record evidencelet alone substantial evidenceto justify its sharp departure from the examiners findings? II. STATEMENT OF THE CASE Rambus appeals the Boards reversal of the examiners decision confirming claim 33 of U.S. Patent No. 6,324,120 (the 120 patent). After a thorough review of all the evidence, the examiner properly confirmed claim 33 over the cited prior art and rejected Microns obviousness arguments based on Bennett in

Case: 13-1339

Document: 18-1

Page: 13

Filed: 06/18/2013

view of Wicklund, Bowater, or Olson, and iAPX in view of both iRAM and Olson. On appeal, the Board misconstrued the claim by essentially ignoring the precharge limitation altogether, dismissing it as nonfunctional descriptive material. Moreover, the Board erroneously concludeddirectly contrary to the examiners findingthat a person of ordinary skill in the art in 1990 would have considered it obvious to combine the systems of Bennett or iAPX with an operation code that specifies both a read instruction and precharge information (not disclosed in any of the cited references) and a synchronous DRAM (also not disclosed in any of the cited references). In reaching this conclusion, the Board ignored the evidence developed by the examiner and, instead, substituted its own presumed expertise for that of the examiner, contrary to this Courts precedent. Accordingly, the Boards decision should be reversed. III. STATEMENT OF FACTS By 1990, when Drs. Farmwald and Horowitz filed their landmark patent application from which the 120 patent claims priority, the DRAM device was twenty years old, asynchronous, and, as stated by the Board, ubiquitous in the industry. (A57.) Every DRAM device, then and today, requires for its operation a memory controller that accepts requests to read from or write to memory, translates each request into a series of DRAM-specific operations, and commands such operations to the DRAM device. It is uncontested that, in the twenty years before 3

Case: 13-1339

Document: 18-1

Page: 14

Filed: 06/18/2013

1990, no one had conceived of a synchronous DRAM that uses an operation code containing both a read instruction and an instruction to optionally precharge after reading. Today, virtually all DRAMs are synchronous and, consistent with the teachings of the 120 patent, include read/write commands with a precharge option. A. Claim 33 of the 120 Patent

The 120 patent claims priority to Application No. 07/510,898, filed on April 18, 1990. (A79.) Claim 33the sole claim-at-issuedepends from claims 26 and 29. Collectively, these claims recite: 26. A synchronous dynamic random access memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; input receiver circuitry, including a first plurality of input receivers to sample block size information synchronously with respect to the external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a first operation code; and a plurality of output drivers to output the amount of data in response to the first operation code. 29. The memory device of claim 26 wherein the input receiver circuitry samples the first operation code synchronously with respect to the external clock signal. 33. The memory device of claim 29 wherein the first operation code includes precharge information. (A110[26:30-65] (emphases added).) 4

Case: 13-1339

Document: 18-1

Page: 15

Filed: 06/18/2013

B.

Background of the Technology-at-Issue 1. Dynamic Random Access Memory

The 120 patent is generally directed to the structure, operation, and control of Dynamic Random Access Memory devices or DRAMs. DRAMs store

information in memory cells, which are typically arranged in a two-dimensional rectangular array. (A98[1:60-64]; A2413[15].) The array of cells includes

columns and rows, such that each cell can be accessed using a row/column address. (A98[1:60-64]; A2413[15].) Each memory cell contains a capacitor for storing a charge representing one bit of information; for example, a charged capacitor may represent a 1, while a capacitor with no charge would represent a 0. (A98[1:60-64]; A2412-13[13].) A computer typically has many DRAMs

controlled by a single memory controller. (See, e.g., A103[11:11-19] (discussing a computer with 100 DRAMs).) A central processing unit (CPU) can transfer information to or from a memory address using a memory controller. (A2413[17].) The memory

controller accesses a designated row/column address in a given DRAM and performs either a read or write operation. (Id.) Information and control signals flowing between the CPU and the memory controller or between the memory controller and the numerous DRAMs can travel on one or more buses, each consisting of a series of wires or lines that connect

Case: 13-1339

Document: 18-1

Page: 16

Filed: 06/18/2013

the devices. (A99[3:51-4:34].) Prior-art computers typically had a primary bus that connected the CPU to the memory controller and a secondary bus that connected the memory controller to an array of numerous DRAMs, as shown in the figure below from the Wicklund reference (each set of two-way arrows represents a bus).

(A1732.) A similar setup is shown in the iAPX reference. (A1783 (showing a Memory Module consisting of an MCU, or memory control unit attached to a primary MACD Bus, and an Array attached by a secondary bus to the MCU); see also A2413-14[17-18]; A2427[56]; A2476[56].) Generally, instructions traveling along the primary bus are system-wide instructions such as instructions to access memory, whereas in the prior art, signal transitions on the secondary busbetween the memory controller and the individual DRAMsmanaged the detailed operations of the individual DRAMs in the memory array. (A2480-81[73].) 6

Case: 13-1339

Document: 18-1

Page: 17

Filed: 06/18/2013

A focus of the 120 patent is to make the memory system more efficient so that data can be transferred faster than was possible in the prior art. (A100[5:3134].) This is accomplished, in part, by (1) employing a synchronous memory interface between the memory controller and the DRAMs, i.e., one that utilizes an external clock signal to govern memory transactions with the individual DRAMs; and (2) using multi-bit operation codes that provide for new combination instructions that allow a controller to specify, e.g., both a read operation and whether or not the DRAM should automatically precharge as a part of the read operation. 2. Asynchronous Versus Synchronous DRAM Chips

Prior to 1990 (the effective filing date of the 120 patent), conventional DRAMs operated asynchronously, i.e., without being synchronized with an external clock signal. (A2413[18]; A98[2:44-47].) Read and write operations were conducted by the controller driving control signal transitions on specific bus lines, where the transitions had to occur in a specific order based on the desired operation. (A2413-14[18].) This was considered the most efficient way to access information because each DRAM transferred data as soon as possible after being instructed to do so. (See A3249.) In contrast, the DRAMs disclosed in the 120 patent are synchronous (A79[Abstract]), which means they operate markedly differently from prior-art 7

Case: 13-1339

Document: 18-1

Page: 18

Filed: 06/18/2013

asynchronous DRAMs. The hallmark of a synchronous DRAM is that an external clock signal governs the timing of the read and write operations for all DRAMs on the bus, based on when a potentially complex instruction is sent onto the bus. (A2414[19]; A99[3:8-11].) In a synchronous system, at least one signal line carries an external clock signal, such as the one shown below, which is used to synchronize all read and write operations for all the DRAMs on the bus. (A101[8:30-31]; A2414[19]; see A101[8:44-59]; A95[Fig. 14].)

In such a system, the memory controller can issue an operation code specifying a read to a particular DRAM at a given clock cycle and further specifying that the requested data must be returned a precise number of clock cycles later. (A2414-17[19-26].) Then, after that precise number of clock cycles has elapsed, that DRAM responds and the controller can check the data on the bus lines and know that it is the data associated with the earlier read request. (Id.) Meanwhile, in the intervening clock cycles, the memory controller can issue another operation code to another DRAM and start another access while the first DRAM is working to process the first read. (Id.) In this way, transactions can be interleaved and pre-scheduled to occur at certain times, i.e., after a certain number of clock cycles. (Id.) In contrast, prior-art asynchronous systems could 8

Case: 13-1339

Document: 18-1

Page: 19

Filed: 06/18/2013

only control one operation at a time because each operation required specific control signal transitions at specific intervals throughout the operation (and thus tied up the bus for the duration of the operation). While it was known prior to 1990 to include a clock on a primary bus (i.e., between the CPU and a memory controller), the bus between the memory controller and the asynchronous DRAM chips did not include a clock, and the DRAM chips were therefore not operated synchronously in the prior art. (A241314[18]; A2427-28[55-57]; A2475-76[55-56].) Instead, prior-art DRAMs

typically came in arrays of many DRAMs, each of which was asynchronously operated based on bus signal transitions from the memory controller, which in turn was connected to a CPU via the primary bus. A2427[56]; A2475-76[55].) 3. Prior Cases Involving Synchronous Memory Devices (See A2413-14[17-18];

In past cases involving other patents in the 120 family, the asynchronous/synchronous issue has been extensively litigated. For instance, in U.S. Patent No. 6,034,918 (the 918 patent), the claims-at-issue recited a synchronous memory device, and this Court held that this term was not limited to a single chip memory device. In re Rambus Inc., 694 F.3d 42, 46-48

(Fed. Cir. 2012). As a result, this Court concluded that multiple DRAMs and their associated memory controller could collectively (in certain circumstances) be 9

Case: 13-1339

Document: 18-1

Page: 20

Filed: 06/18/2013

considered a memory device.

Id.

Under this interpretation, even if the

individual DRAM chips themselves were controlled asynchronously by a memory controller, if the entire collection of DRAMs and their memory controller was connected by the memory controller to a synchronous primary bus, then the whole collection could be considered a synchronous memory device. Id. That issue is not present here, however. In this case, claim 33 requires a synchronous dynamic random access memory device, as opposed to a generic synchronous memory device, as was at issue in the 918 patent. (A110[26:3031]; see A110[26:39] (referring back to the memory device).) The examiner construed this limitation to require a single synchronous DRAM chip (A1092; A1131-32), and the Board treated the limitation the same way (A55-56 & n.17 (assuming that single-chip DRAM interpretation applied and explaining that Micron concedes that if the preamble is limiting, claim 26 requires a single chip DRAM)). Thus, to determine whether a DRAM chip is synchronous or

asynchronous for purposes of claim 33, one must look to the specific bus to which that chip is attached, not some higher-level bus to which its associated controller may be attached. If the DRAM chip itself does not receive a clock signal, then it is an asynchronous DRAM, regardless of whether there may be synchronous components upstream of its controller.

10

Case: 13-1339

Document: 18-1

Page: 21

Filed: 06/18/2013

4.

Precharging of Sense Amplifiers

DRAMs sense (for reading) or store (for writing) a charge in a given cell using a sense amplifier, which is an electrical component that detects and amplifies the small amount of charge in a cell corresponding to a 0 or a 1, such that the cell can be accessed for a read or write. The 120 patent explains this basic configuration as follows, using the conventional terminology of word line and bit line for row and column, respectively. All modern DRAM, SRAM and ROM designs have internal architectures with row (word) and column (bit) lines to efficiently tile a 2-D area. Referring to FIG. 1, one bit of data is stored at the intersection of each word line 5 and bit line 6. When a particular word line is enabled, all of the corresponding data bits are transferred onto the bit lines. This data, about 4000 bits at a time in a 4 Mbit DRAM, is then loaded into column sense amplifiers 3 and held for use by the I/O circuits. (A100[5:66-6:7].)

11

Case: 13-1339

Document: 18-1

Page: 22

Filed: 06/18/2013

(A83.) When a row address is sent from the memory controller, the information from each cell in that row is sent to the sense amplifiers. This is known as open[ing] a row. (A2415-16[23].) In the demonstrative illustration below, the sense amplifiers are shown near the bottom of the figure. The third row has been opened, so the information from the third row has been copied to the sense amplifiers.

12

Case: 13-1339

Document: 18-1

Page: 23

Filed: 06/18/2013

0 1

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 0 1 0 1 0 1 0 0

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

Row Decoder

1 1 0 1 0 1 0 1

Column Decoder

Sense Amplifiers

When a particular column address is sent from the memory controller, the column decoder selects the corresponding sense amplifier (assuming only one bit read per address) and, depending on whether a read or write is being performed, the bit of information in that sense amplifier is read out or a new bit of information is written into that sense amplifier. In the illustration below, the memory controller has specified that the fourth column in the opened row should be read. Thus, the 0 stored in the fourth sense amplifier is output to the memory controller.

13

Case: 13-1339

Document: 18-1

Page: 24

Filed: 06/18/2013

Before a new row can be loaded into the sense amplifiers, the current row must be closed and the sense amplifiers must be precharged, i.e., their charges must be preset to a known voltage level, e.g., between the voltages used to represent a 0 and a 1. (Id.) Much like a balanced seesaw will respond to slight pressure on one side to swing the seesaw, precharging enables the sense amplifiers to subsequently detect a logical 1 or 0 based on just a tiny quantity of charge in a cell. (Id.) In the art, DRAMs were known to operate in at least two modes: normal mode and page mode. (A102[10:15-39].) In normal mode, a new row is 14

Case: 13-1339

Document: 18-1

Page: 25

Filed: 06/18/2013

opened and then a column address is supplied to access data, as shown in the first demonstrative illustration above. (Id.) Opening a new row takes time, however, which is generally undesirable in very high-speed memory systems. (Id.) An alternative to a normal mode access is a page mode access, in which data from a previously opened row remain in the sense amplifiers from a previous read or write, and another column in that same row is accessed without the need to load a new row into the sense amplifiers. Page mode accesses are only advantageous, however, if the next cell to be accessed is in the same row as the previous cell that was accessed. (Id.) In prior-art asynchronous DRAMs, one signal line (Row Address Strobe or RAS) was used to open and close rows, and another signal line (Column Address Strobe or CAS) was used to control column access operations (i.e., read and write) to open a row. Annotated Figure 2 from Bowater (one of the references relied on by the Board) illustrates this process:

15

Case: 13-1339

Document: 18-1

Page: 26

Filed: 06/18/2013

Open Row

Read COL 0

Read COL 1

Close Row, Precharge

(A1740 (annotated).) Figure 2 shows row and column control for two banks of DRAM devices A and Bboth banks of devices operate similarly, and thus the A operation is representative of prior-art asynchronous operation. At transition 41, the controller transitions RAS A low, causing a row at address ROW to be opened. After allowing enough time for the sense amplifiers to sense the row data, the controller transitions CAS A low, causing a read at address COL 0 of ROW and data 0 to be output onto the DATA lines. The controller then transitions CAS A high, causing data 0 to no longer be driven onto the DATA lines. The controller later transitions CAS A low again, causing a second read at address COL 1 of ROW and data 2 to be output. The controller then transitions CAS A high, causing data 2 to no longer be driven onto the DATA lines. Finally, the controller transitions RAS A high, closing ROW and precharging the sense amplifiers. 16

Case: 13-1339

Document: 18-1

Page: 27

Filed: 06/18/2013

Notably, the controller in Bowater must hold RAS low throughout the entire time that column operations are performed, or else the sense amplifiers will be precharged prematurely and the column operations will not be performed correctly. Thus, because a read or write operation requires that RAS be held low while CAS transitions low, it would be impossible to also simultaneously signal a precharge operation by driving RAS high. In other words, asynchronous devices require, as shown above, that the controller hold RAS low and that no precharge signaling be initiated until the column operations have completed. The memory device recited in claim 33 of the 120 patent operates differently from the prior art. Instead of using the prior-art method of dedicating a RAS line that must be held low from the time a row is open until the time that row is closed, the 120 patent teaches that a combination instruction or operation code can be used. This combination instruction can include, among other things, an indication to read or write as well as precharge information, such that the DRAM already knows whether or not to perform a precharge operation in conjunction with the read/write operation, without the need for a separate instruction as was required in the prior art. (A102-03[10:40-11:45].) Such

precharge information in a synchronous DRAM allows the bus to be used only briefly and only once per read/write request, whereas prior-art devices had to hold RAS low until column operations were completed, effectively tying up the bus 17

Case: 13-1339

Document: 18-1

Page: 28

Filed: 06/18/2013

until a precharge was possible. Thus, in contrast to the prior art, the claimed devicein which read instructions are combined with precharge information in an operation codeallows the bus to be freed up to preschedule other operations. (See A2416[23] (Mr. Murphy explaining that auto-precharge helps free up control bandwidth, whereas a dedicated precharge command consumes additional bandwidth).) C. The Unrebutted, Objective Evidence of Nonobviousness

The invention recited in claim 33 of the 120 patent, including the novel use of synchronously controlled DRAM chips to improve speed and efficiency, achieved tremendous commercial success and widespread acceptance in the industry. (A2459[11].) Indeed, Rambuss synchronous DRAM technology was widely considered revolutionary in the industry. (A2785[91]; see also A3224 (stating in March 1992 that Rambus had a revolutionary memory chip technology . . . offer[ing] a tenfold speed boost to memory chips); A3241; A3248; A3252; A3229 (describing Rambuss approach a fundamental change in the design of computer memory systems).) Moreover, based on his pioneering efforts in

developing synchronous memory device technology, Dr. Horowitz, one of the inventors, received an IEEE award and was elected to the National Academy of Engineering. (A3211; A3214; A3216.) His research has changed the way an entire industry thinks about memory interfaces and fostered a revolution in that 18

Case: 13-1339

Document: 18-1

Page: 29

Filed: 06/18/2013

industry. Memory access bandwidths have increased by more than an order of magnitude in just a few years as a result of the ideas he pioneered. (A3212; see also A3216.) As Mr. Murphy also explained, Drs. Farmwald and Horowitzs solutions to the bottleneck problem were received with skepticism by many experts in the field at the time they conceived the invention, but this skepticism was eventually proven wrong, as a majority of the memory devices available today (e.g., DDR, DDR2, DDR3, SDRAMs) employ features that are claimed in the 120 patent. (A2459[12]; see also A2787[105] (The response to the early presentations in 1989-90 was just disbelief that Drs. Farmwald and Horowitz would be able to achieve a 500 megabit per second DRAM data rate.); A3234 (potential licensees expressed concern whether a computers drivers and receivers could work at these frequencies); A3247 (system companies were skeptical that [Rambus could] operate reliably at these speeds).) Notably, Micron did not submit any expert declarations or other evidence rebutting these facts. D. The Prior Art-at-Issue

The Board found claim 33 obvious in view of (a) Bennett in combination with Olson, Bowater or Wicklund; or (b) iAPX and iRAM in combination with Olson. Each of these references will be discussed briefly below. 19

Case: 13-1339

Document: 18-1

Page: 30

Filed: 06/18/2013

1.

Primary References a. Bennett

Bennett discloses a mainframe computer system, circa 1982. (A1335.) The reference focuses on the interface between a primary bus, called the Versatile Bus, and various different types of Users connected to it. (A1335[Abstract]; A2475-76[55].) Bennetts Figure 38, reproduced below, shows four such Users connected to a V Bus or Versatile Bus.

(A1360.) At 396 pages long, Bennett discusses many different types of Users that can be connected to the primary bus and many different attributes of the primary interface. (A2475-76[54-58]; see A1335-730.) It does not disclose DRAMs, however, nor does it disclose precharging or anything related to precharging. (A2478[63-64]; A2480-81[70-74]; see A55-58.)

20

Case: 13-1339

Document: 18-1

Page: 31

Filed: 06/18/2013

b.

iAPX

iAPX discloses a system that includes a primary bus connected to memory cards, wherein each memory card consists of a memory controller connected to multiple asynchronous DRAMs, as was conventional in the prior art. As shown in iAPXs Figure 1-2, the primary MACD Bus is connected to a Memory Module, or memory card. (A1783.) The Memory Module consists of an MCU (memory control unit) attached by a secondary bus to an Array of asynchronous DRAMs.

(Id.) Thus, iAPX does not disclose any DRAMs synchronously connected to the primary bus, or even connected to the primary bus at all. (See A2426-29[54-59];

21

Case: 13-1339

Document: 18-1

Page: 32

Filed: 06/18/2013

A2460-63[15-18].)

Nor does it disclose precharging or anything related to

precharging. (See A2442[105].) c. iRAM

iRAM similarly does not disclose synchronous DRAMs or anything related to precharging. iRAM discloses an integrated RAM, or iRAM. (A2135.) It teaches integrating a dynamic RAM and its control and refresh circuitry on one substrate, creating a chip that has dynamic RAM density characteristics, but looks like a static RAM to users. (Id.) iRAM thus discloses combining one DRAM chip with its refresh circuitry. It does not suggest that this chip should be

synchronous with any clock; and, indeed, the chip has no circuitry to receive a clock input. (See infra III.E.2.b; cf. A61.) 2. Secondary References

The Board relied on Olson, Wicklund, and Bowater as secondary references to show the claimed precharge limitation. conventional, asynchronous DRAMs. Those references all disclose

(A2441-42[104]; A2483[82-83];

A1763[2:49-68]; A1733[2:62-66]; A2482[79]; A1738[Abstract].) Thus, none of them discloses synchronous operation codes provided to a DRAM for any purpose, much less a single operation code that combines both a read instruction and precharge information, as recited in claim 33.

22

Case: 13-1339

Document: 18-1

Page: 33

Filed: 06/18/2013

a.

Olson

Olson is designed to solve a specific problem, in which prior-art systems always precharged after a host idle cycle, preventing a page-mode access. (A1763[1:24-36].) Thus, Olson discloses a memory system using conventional, asynchronous DRAMs, in which a memory controller does not precharge the sense amplifiers if the system is idle, to allow the next access to be to the same row. (A1763[1:8-14].) Thus, the precharge signaling in Olson, like that of any

conventional asynchronous DRAM, is sent separate from the read/write signaling, not in any operation code combining the two instructions. (See A3466.) b. Wicklund

Wicklund discloses a memory system using conventional, asynchronous DRAMs, in which a memory controller guesses whether to precharge the sense amplifiers of the asynchronous DRAMs based on prediction algorithms. (A1734[3:6-9, 4:4-25].) Wicklund includes asynchronous read/write signaling to the DRAMS, and whether to precharge is determined separately by the memory controller using an algorithm and is triggered by separate and distinct asynchronous precharge signaling (issued by the memory controller to the asynchronous DRAMs) that is not combined with any read/write signaling. (A2481-82[76-77].) Thus, any precharge signaling in Wicklund is necessarily

23

Case: 13-1339

Document: 18-1

Page: 34

Filed: 06/18/2013

sent by the memory controller separate from the read/write signaling. (A3538; A3553.) c. Bowater

Bowater also discloses a memory system using conventional asynchronous DRAMs and a timing-based algorithm in a memory controller for determining special circumstances when precharging is required. In contrast to Wicklund, the memory controller in Bowater opens a row and keeps it open until a certain amount of time passes. (See A3540.) In other words, Bowater assumes that, regardless of what the previous access was, the next access will be in the same row. (A1752[7:54-56].) If the next access is not in the same row, just like in other prior-art asynchronous DRAMs, Bowater closes the row (thereby incurring a time penalty, see A102[10:33-36]), and the sense amplifiers are then precharged. If multiple accesses are in the same row, Bowater waits for a specified amount of time and then closes the row, on the premise that the row should only be left open for a limited period of time to preserve the integrity of data in an open row, even if the next access is to the same row. (A1752[7:54-8:8].) Bowater cannot send precharge information with read/write signaling, as discussed in the preceding section, because RAS must be held low during read/write signaling and high to initiate precharge. Thus, Bowater does not disclose the concept of combining

24

Case: 13-1339

Document: 18-1

Page: 35

Filed: 06/18/2013

read/write signaling and precharge information and does not disclose providing a combination operation code to DRAMs. E. The Proceedings Below 1. The Examiners Determination of Nonobviousness

After thoroughly considering all of the asserted prior art, including Bennett, iAPX, iRAM, Olson, Wicklund, and Bowater, and after duly considering all of Microns arguments, the examiner concluded that none of the cited art renders claim 33 obvious. In particular, the examiner found that none of the art discloses or renders obvious a synchronous DRAM, as required by claim 33. Furthermore, in this proceeding and in an earlier reexamination involving a related patent with the same specification, the examiner concluded that none of the prior art discloses or renders obvious an operation code that contains both a read instruction and precharge information, as required by claim 33. a. The Examiner Found in This Proceeding and in a Related Proceeding that the Cited Prior Art Does Not Disclose or Render Obvious an Operation Code Containing Both a Read Instruction and Precharge Information

In affirming claim 33 in this reexamination, the examiner primarily focused on the fact that the prior art fails to disclose or render obvious the synchronous DRAM limitation. (See A1187-90 (not maintaining proposed rejections to claim 33 [f]or the reasons set forth above, i.e., failure to disclose synchronous DRAM).) However, based on the full context of the proceedings below and related 25

Case: 13-1339

Document: 18-1

Page: 36

Filed: 06/18/2013

proceedings, it is clear that the examiner also found no disclosure in the cited prior art of an operation code containing both a read instruction and precharge information, as required by claim 33. For instance, in discussing the precharge issue with respect to claim 7 of the 120 patent, the examiner stated that the same operation code that includes precharge information is the same operation code th[at] contains [an] instruction to perform a first operation. The claim specifically requires the same operation code to indicate this information. (A1133.) The examiner had explained that, for both claims 7 and 33 (see A3380), although Olson disclosed precharge information, neither iAPX nor Olson showed whether this precharge information [is] sent along with the first operation code. As noted in the claims the first operation code must cause the memory device to perform a read operation (A3465-66). Thus, the examiner found that neither iAPX nor Olson discloses the operation code containing precharge as required by claim 33. (See also A1173-74 (stating that Issue 11, which addresses iAPX and Olson as applied to claim 33, A1088, is not maintained [f]or the reasons noted above . . . and in the [Action Closing Prosecution], cited supra).) Similarly, in the reexamination of a related patent, U.S. Patent No. 6,584,037 (the 037 patent), which has the same specification as the 120 patent, the same examiner extensively discussed the prior arts failure to disclose an 26

Case: 13-1339

Document: 18-1

Page: 37

Filed: 06/18/2013

operation code containing both a read/write instruction and precharge information. Specifically, in the 037 patent reexamination, as here, it was an accepted fact that neither Bennett nor iAPX nor iRAM discloses the recited operation code that contains both a read/write instruction and precharge information. (A3621[ll.7-10]; A3528-30; A3466; A58; A62-63.) Indeed, as Micron conceded in its request for the present reexamination, none of these references discusses precharging at all. (A2274 (explaining that Olson is combined with the iAPX Manual and iRAM to supply the teaching that the operation code disclosed in the iAPX Manual includes precharge information); A2286-90 (Microns reexamination request not alleging any disclosure of precharging in Bennett).) In the related 037 reexamination, the examiner found that Olson, Wicklund, and Bowater do not disclose the claimed operation code containing both a read/write instruction and precharge information. (A3581; A3530-31.) Thus,

although the examiner found that Bennett generically discloses an operation code (A3552), he found that no reference discloses or suggests the claimed operation code containing both a read/write instruction and precharge information, and he further found that such an operation code would not have been obvious to a person of ordinary skill in the art in 1990 (A3553; A3556-57). 1

The Board reversed that finding, and that issue is currently the subject of Appeal No. 2013-1087, now pending before this Court. 27

Case: 13-1339

Document: 18-1

Page: 38

Filed: 06/18/2013

With respect to Olson, the examiner found that it did not disclose whether this precharge information is included in the same operation code as the request for sampling data to be written. (A3530.) With respect to Wicklund, the examiner explained in the 037 reexamination that [t]here is no indication [in Wicklund] that precharge is automatically performed after data is written. (A3536-37; see also A3538 ([Wicklund] does not disclose . . . [a] precharging instruction [that] came within the same operation code as the specifying of the sampling of the data to be written . . . .); see also A3550; A3553.) Thus, as the examiner found, in Wicklund, page mode is

automatically turned on or off based on a prediction of whether or not the next access will be at the same DRAM row address as the last one. (A3538.) This is different from the claimed invention, which receives and responds to a first operation code that includes a read (data output) instruction and precharge information. (Id.) Regarding Bowater, the examiner found in the 037 reexamination that Bowater does not disclose the claimed operation code that includes both a read/write instruction and precharge information. (A3540-01 (Bowater does not disclose that such precharge information is included in an operation code that also indicates a write operation as recited in claim 34 since Bowater is respon[ding] to a counter and not an instruction that is included with a same operation code that 28

Case: 13-1339

Document: 18-1

Page: 39

Filed: 06/18/2013

includes a specify[ing] of sampling data to be written.); see also A3556.) Instead, Bowater has a timer, and, after a certain amount of time, the row is closed and the sense amplifiers are precharged in response to independent signaling to precharge that is given to the DRAM separate from any read or write signaling. (A3540-01; A3556; A2482[78-80].) The examiner further explained in the 037 reexamination that one would not have been motivated to include the precharge information of Bowater in an operation code. Specifically, he found that the precharge indication of Bowater is based on a counter and there is no support for including this information along with [a] write request since that would defeat the purpose of the essential counter. (A3541.) As he further explained, [i]f Bowater provides precharge information that will automatically precharge after writing data, Bowater would not be able to change the time since the instruction would have already been sent. (A3542.) In the present reexamination, the only expert testimony proffered on the precharge issue was that of Mr. Murphy, Rambuss expert. He explained that it would not have been obvious at the time of the invention to combine a read/write instruction with precharge information into a single operation code, as required by claim 33. For example, he explained that, in Bennetts mainframe computer

system, high-level instructions (such as a read or write instruction) and low-level operations (such as a precharge operation) would be generated by different parts of 29

Case: 13-1339

Document: 18-1

Page: 40

Filed: 06/18/2013

the system. (See A2480[70] (Bennett is not focused on memory devices, let alone DRAMs, and therefore it does not provide any disclosure about specific DRAM functions such as precharging.); A2480[73] ([T]he localized operation of precharging DRAMs after the completion of a row access is not something that would be handled by the processors in Bennett that generate requests to memory as those processors would not be aware of the page boundaries [i.e., which row particular data are stored in] for the particular memory devices within the memory modules of Bennett.).) Mr. Murphy explained that the same is true of the iAPX and iRAM systems. (A2427-29[56-59]; A2467[31]; A2470[38].) Consistent with Mr. Murphys testimony, in Olson, Wicklund, and Bowater, precharge signaling is generated by the memory controller, whereas read and write requests are generated by the CPUa higher-level processor. Thus, as

Mr. Murphy explained, if DRAMs were implemented in Bennett at all (despite not being taught), instructions to write and signaling to precharge would have been two different functions, originated by two different parts of the system. 81[70, 73]; see also A2427[56].) (A2480-

Micron submitted no expert evidence

rebutting this testimony of Mr. Murphy. Indeed, Micron submitted no expert testimony at all during this reexamination proceeding.

30

Case: 13-1339

Document: 18-1

Page: 41

Filed: 06/18/2013

b.

The Examiner Found that the Cited Prior Art Does Not Disclose or Render Obvious a Synchronous DRAM

The examiner also found claim 33 of the 120 patent nonobvious based on the prior arts failure to disclose a synchronous DRAM. The examiner construed synchronous dynamic random access memory device to be limited to a single chip, such that it is an integrated synchronous interface for a DRAM. (A1145; A1092; A1131-32.) In arriving at this construction, the examiner relied on the 120 patents specification, which makes clear that a synchronous DRAM device is a single chip. (A1131-32 (quoting A99[4:21-34]).) The Board did not dispute this construction.2 (A56 n.17.) Based on this essentially undisputed construction, the examiner determined that a person of ordinary skill in the art in 1990, reading Bennett (which does not disclose DRAMs) or iAPX in view of iRAM (which both disclose only conventional asynchronous DRAMs) would not have been motivated to operate a single DRAM chip synchronously, as required by claim 33. (A1134-36; A1140; A1177-81.) Micron argued that the term synchronous dynamic random access memory device was not limiting because it is recited only in the claims preamble. (A56 n.17.) But, as the Board pointed out, the body of the claim refers back to the preamble by reciting the memory device. (Id.) The Board found Micron had conceded that, to the extent synchronous DRAM is a claim limitation, it requires a synchronous DRAM chip. (Id. (citing A3318).) Indeed, Micron never raised that argument in its opening brief to the Board. (A2326-70.) 31
2

Case: 13-1339

Document: 18-1

Page: 42

Filed: 06/18/2013

With respect to Bennett, although it discloses many possible Users that can be connected to the synchronous Versatile Bus, it is undisputed that it does not disclose DRAM devices as Users, even though DRAMs existed at the time of Bennetts filing. (A2478[63]; A2413[15].) Micron argued, however, that one of the disclosed Users in Bennettthe so-called large memory Usercould hypothetically be made up of DRAMs, such that DRAMs are either inherent or obvious. (A2284; see A2333-37.) The examiner addressed this argument and correctly concluded that any such DRAMs used in Bennett would be asynchronous, rather than synchronous as required by claim 33. (A1140.) The only DRAMs in use at the time of the claimed invention were asynchronous DRAMs. (A2413[18].) For instance, besides Bennett, which does not disclose DRAMs at all, all five of the other prior-art references relied on by the Board disclose only asynchronous DRAM-based systems. The most common way of using DRAMs at that time was by connecting many DRAM chips (i.e., an array) to a secondary bus having a dedicated memory controller. (See, e.g., A2475-78[54-64]; A1732; A2426-28[53-58]; A2460-63[15-17];

A2482[80]; A2483[83]; A2413-14[18].)

That whole group, i.e., the

asynchronous DRAMs along with the secondary bus and a memory controller (collectively called a memory card or module), was then connected by the controller to a primary bus. (A2475-76[55].) As the examiner correctly found, 32

Case: 13-1339

Document: 18-1

Page: 43

Filed: 06/18/2013

such a configuration would not meet the synchronous DRAM limitation because this limitation requires a single DRAM chip that operates synchronously (as opposed to multiple asynchronous chips that are connected to a memory controller that, in turn, is connected synchronously to a primary bus). (A1145; A1092; A1131-32.) Indeed, an expert retained by Micron conceded in litigation that Bennetts large memory, to the extent it could be made up of DRAMs, would have been composed of multiple chips. (A3683 (emphasis added).) And Samsung, the other party that initially requested reexamination, made the same point in its request for reexamination of the 037 patent, i.e., that Bennetts large memory necessarily would have been made of multiple chips. (A3764; see also A2475-76[55].) Consistent with these admissions, Bennett discloses that the large memory includes up to 232 addresses of 32-bit words (A2475-76[55] (citing A1637[95:5859])), a number that even now cannot be contained on a single DRAM chip (see A2413[15]). Moreover, as Mr. Murphy explained in an unrebutted declaration, Bennetts architecture would not permit individual DRAM chips to be connected directly to Bennetts primary bus. Specifically, Mr. Murphy testified that Bennett describes the VBI (or primary bus) as being designed to accept complex connections, containing many different pins. (A2476-77[58-62].) If a single DRAM chip 33

Case: 13-1339

Document: 18-1

Page: 44

Filed: 06/18/2013

were to be connected to the primary bus, it would have to contain all of those pins and the complex circuitry that goes with them. (Id.) Mr. Murphy explained that DRAMs were desirable specifically because they were small and cheap, and adding so many pins and so much circuitry would have made each DRAM chip large and expensive, and therefore undesirable. (Id.; see also A1593[8:10-12].) Given all this evidence, the examiner concluded that Bennett did not disclose or render obvious a synchronous DRAM chip. With respect to the size of Bennetts large memory, the examiner stated that he was not ab[le] to find any disclosure in Bennett that would show that a single integrated memory chip (i.e. the claimed synchronous dynamic random access memory device) would support the noted address [i.e., size] requirements. Thus, even if one would have considered that it would have been obvious to have a DRAM based memory device, the disclosure of Bennett does not disclose that the relied up[on] memory device that is the memory device that is on the same substrate as the Versatile Bus Interface, would be a DRAM. (A1140.) Instead, according to the examiner, Bennetts 232 addresses of 32 bit words (A1637[95:58-60]) support only multi-DRAM memory cards and the like (A1140). The examiner therefore found Bennett does not anticipate or render obvious the claimed synchronous DRAM chip. (Id.) As for the proposed iAPX/iRAM combination, the examiner found it would not have been obvious to combine iAPX Manual with iRAM . . . . (A1187.) The examiner relied in part on testimony from Intels architects of the iAPX system, 34

Case: 13-1339

Document: 18-1

Page: 45

Filed: 06/18/2013

who stated that the DRAMs of iAPX were designed to be interchangeable with other types of memory devices. According to Intels designers, replacing the whole memory card of iAPX with a single iRAM chip would defeat that goal of iAPX since the MCU [memory control unit] would have to be physically removed and placed into each individual iRAM. (A1178; see also A1177.) The examiner concluded that nothing within the references indicate[s] that an integrated MCU and DRAM in iAPX would be predictable to one of ordinary skill in the art given the fact that iAPX designers sought to separate the MCU from the storage array so that different types of DRAMs can be used. The Examiner finds that based on the submitted testimonies and declaration the combination would not have been predictable and would teach away from having a system which would be flexible in using different types of DRAMs. (A1179-80.) The examiner also concluded that replacing the memory card of iAPX with individual iRAM chips connected to the primary bus would defeat several other goals of iAPX and render the system inoperable. (A1180-81.) For instance, the examiner agreed with Rambus that integrating a memory control unit onto each of the memory devices would prevent any one of the memory control units in the system from having the perspective on the data and [error checking and correction] information stored in the array that would allow for the error detection and correction to occur. The proposed 35

Case: 13-1339

Document: 18-1

Page: 46

Filed: 06/18/2013

integration would, therefore, render the iAPX 432 system inoperable. (A1180 (emphasis added).) The examiner further agreed with Rambus that the combination would prevent the use of iAPXs spare DRAM chip, which can be used to replace a defective DRAM in the array if the memory control unit detects such a faulty device. (Id.) Without a global perspective on the array, a

perspective which would no longer exist if the memory control unit were integrated onto each of the DRAMs, the ability to utilize the spare DRAM device would be eliminated. (A1181.) 2. The Boards Reversal of the Examiners Decision Confirming Claim 33 a. The Board Construed Precharge Information as Nonfunctional Descriptive Material and Rejected the Examiners Findings Regarding Precharging

In its decision on appeal, the Board spent less than two pages discussing the precharge limitation in combination with Bennett (A58-59), with even less analysis with respect to adding precharge information to the combination of iAPX and iRAM (A62-63). On rehearing, the Board simply rehashed its conclusions

regarding both sets of combinations. (A25-29.) As part of its analysis, the Board determined that claim 33s recitation of precharge information constitutes nonfunctional descriptive material, which

36

Case: 13-1339

Document: 18-1

Page: 47

Filed: 06/18/2013

cannot be used to distinguish the prior art. (A59; A62; A26.) For example, in discussing the iAPX/iRAM combination, the Board held: [T]he type of information added to the first operation code in claim 33, in this case, precharge information, constitutes nonfunctional descriptive material, because claim 33 does not require the device to precharge, decide to precharge, or to have the ability to do either (i.e., to operate differently based on the precharge information versus some other type of information). Such nonfunctional descriptive material concerning information which the claimed device need not even process to render a distinct decision fails to render claim 33 patentably distinct over [the prior art]. (A62; see also A59; A26.) In the alternative, the Board found (contrary to the examiners findings) that combining precharge information with a read instruction in either Bennett or the iAPX/iRAM combination would have been obvious to a person of ordinary skill in the art in 1990. For Bennett, the Board found (contrary to the examiner) that Wicklund shows . . . that precharge normally (i.e., when the DRAM is not in page mode) occurs at the end of a read or write function, showing the obviousness of banding the two related functions into Bennetts write code. (A58; see also A26.) Notably, however, the Board failed to point to anything in the record (other than attorney argument contained in Microns briefs) to justify this sharp departure from the examiners findings, nor did the Board address the stark conflict between its

37

Case: 13-1339

Document: 18-1

Page: 48

Filed: 06/18/2013

personal view and the fact that a read and a precharge are necessarily separate operations in prior-art DRAMs. Similarly, for the iAPX/iRAM combination, the Board stated in conclusory fashion that sending one operation code with information as required to perform certain read operations would have been obvious for the purpose of keeping related read control information together in an existing (or modified) iAPX operation code. (A62-63.) On rehearing, the Board merely added that skilled artisans would have recognized that an iAPX modified controller would have had sufficient perspective to send a precharge signal to an integrated DRAM in the same code as the read signal since the precharge signal normally would have followed the controllers read signal in prior art systems. (A29.) Again, the Board failed to point to any evidence in the record to justify this sharp departure from the examiners finding of nonobviousness. b. The Board Reversed the Examiners Findings Regarding the Nonobviousness of Synchronous DRAMs in 1990

The Board also reversed the examiners finding that neither Bennett nor iAPX/iRAM renders the synchronous DRAM limitation obvious. Regarding

Bennett, the Boards only analysis entailed explaining that DRAMs were ubiquitous, so one of ordinary skill in the art allegedly would have known to use individual synchronous DRAMs as the large memory. (A56.) First, the Board 38

Case: 13-1339

Document: 18-1

Page: 49

Filed: 06/18/2013

accepted, at least for purposes of argument, the examiners construction of the synchronous DRAM term, requiring synchronous DRAM to be a single DRAM chip that receives a clock signal and is connected synchronously to a bus. (A56 n.17.) The Board then found that, because (in the Boards view) Bennett generally discusses attaching memory chips other than DRAMs to the bus, it would have been obvious to connect a single DRAM chip directly to Bennetts primary bus and operate it synchronously. (A57-58.) Thus, notwithstanding Bennetts failure to disclose DRAMs at all, and notwithstanding that the only DRAMs in use at the time were asynchronous DRAMs, the Board concluded that synchronous DRAMs would have been obvious. The Board relied on an implicit motivation to

improve the technology, since (in hindsight) the 120 patents synchronous DRAM technology has proven to be faster than the prior-art asynchronous DRAM technology. (A57 n.18.) On rehearing, the Board repeated its assertions that Bennetts generic synchronous single-chip memory disclosure and Rambuss concession that DRAMs were a well-known, if not dominant, type of memory chip render obvious the claimed combination. (A21 (citation omitted).) The Board then specifically addressed Rambuss argument that Bennetts large memory was intended to hold up to 232 addresses, which is much more than can be held on a single DRAM chip, even today. The Board first relied on the non sequitur that the claims of the 39

Case: 13-1339

Document: 18-1

Page: 50

Filed: 06/18/2013

120 patent do not require 232 addresses, even though Rambuss argument was based on Bennetts implicit suggestion that the large memory would necessarily consist of more than just a single DRAM chip. (Id.) Alternatively, the Board reasoned that Bennett specifically contemplates less address space in chips having a small number of pins, relying on the disclosure of up to 232 addresses, and it further reasoned that Bennett contemplates large address space in future memory chips. (A21-22.) The following annotated figures from Wicklund (top (A1732)) and Bennett (bottom (A1360)) summarize the Boards holding regarding synchronous DRAM:

40

Case: 13-1339

Document: 18-1

Page: 51

Filed: 06/18/2013

As illustrated above, Rambus presented evidence (including admissions by Micron and Samsung, and the unrebutted testimony of Mr. Murphy) that, to the extent DRAMs would be used at all in Bennett, they would have been incorporated as shown above in red (see arrow pointing to Device D), i.e., an entire array of asynchronous DRAMs and their controller would be attached to Bennetts primary bus. As the examiner correctly found, such a configuration would not meet the synchronous DRAM limitation because the individual DRAM chips would still be asynchronous (i.e., asynchronously connected to their controller), just as they were in the prior art. The Board found, however, that it would have been obvious in 1990 to follow the blue path above (see arrow pointing to Device C) by attaching an individual DRAM chip directly to the synchronous Versatile Bus of Bennetts mainframe computer system (even though the Versatile Bus must then support new functions never supported on a synchronous bus, such as precharge and refresh). With respect to the combination of iAPX and iRAM, the Board again foundcontrary to the examiners findingthat the iAPX/iRAM combination rendered synchronous DRAMs obvious. It is undisputed, however, that iAPX discloses only asynchronous DRAM chips attached to a memory controller, and that the memory controller provides the interface with the primary bus. (A47.) With respect to iRAM, despite no one (neither Micron nor the examiner) arguing 41

Case: 13-1339

Document: 18-1

Page: 52

Filed: 06/18/2013

that iRAM discloses synchronous DRAM chips, and contrary to the abundant evidence that the iRAM chip was not designed to even receive a clock input, the Board determined that iRAMs reference to a synchronous 2187 iRAM meant that [t]he iRAM may be synchronous in the sense of the 120 patent. (A54; see A61 (The iRAM solution also includes synchronous iRAMs, similar to the synchronous MCU operation (under the rejection of claim 1). (citing A54)).) As Rambus explained, however, and as the examiner correctly found, iRAMs reference to synchronous means something entirely different from the claimed synchronous DRAM. Indeed, even Micron never argued that iRAM

discloses a synchronous device within the meaning of claim 33. (A2266-67; A2275; A2346-50 & n.10.) And with good reasonthe iRAM reference shows that there is no clock signal that reaches the allegedly synchronous chip. Instead, as shown in iRAMs Figure 26, the 2187 iRAM chip (highlighted in pink) receives only conventional transition-based signalssuch as chip enable (CE) and write enable (WE)and does not receive any clock signal (CLK), such as the one received by the separate 8051 chip (highlighted in green).

42

Case: 13-1339

Document: 18-1

Page: 53

Filed: 06/18/2013

(A2170 (highlighting added).) Indeed, the European Patent Office (EPO) looked at the iRAM reference and concluded that, although iRAM contain[s] a device labelled as Synchronous 2167, that use of the term synchronous has nothing to do with a synchronous bus protocol controlled by a clock signal as claimed. (A3310[11].) Rather, as the EPO explained, the synchronous versus asynchronous descriptions in iRAM refer to whether refreshing is done autonomously or through a separate input. (A3311[11].) It thus concluded that [n]one of the disclosed iRAM

devices has a synchronous bus interface in the sense of the present invention, with an external clock signal provided to the device. (Mr. Murphy explaining same thing).) On rehearing, after Rambus explained these facts, the Board nevertheless maintained its incorrect finding, stating that [t]he cited iRAM page describes (Id.; see also A2464[21]

43

Case: 13-1339

Document: 18-1

Page: 54

Filed: 06/18/2013

synchronous 2187 iRAM . . . running at 10MHz by utilizing a method known as clock stretching. (A28 (quoting A2169).) But the Board cited no evidence (nor is there any evidence in the record) suggesting that iRAM contemplated a synchronous DRAM, as recited in claim 33. As for the examiners finding that it would not have been obvious to combine iAPX Manual with iRAM (A1187) and his specific finding that such a combination would render iRAM inoperable (A1180), the Board dismissed these findings as not persuasive yet failed to cite any record evidenceother than attorney argument contained in Microns briefsto support this sharp departure from the examiners findings and conclusions (A61). IV. SUMMARY OF ARGUMENT The Board erred in reversing the examiners finding that claim 33 is nonobvious in view of the cited prior art. First, the Board erred as a matter of law in construing the precharge information limitation of claim 33 as nonfunctional descriptive material, essentially eliminating the limitation altogether, contrary to this Courts precedent. Second, the Board erred in substituting its own presumed expertise for that of the examiner in determining (as an alternative to its nonfunctional claim-construction ruling) that it would have been obvious in 1990 to include a read instruction and precharge information in the same operation code, notwithstanding that asynchronous devices cannot signal read operations and 44

Case: 13-1339

Document: 18-1

Page: 55

Filed: 06/18/2013

precharge operations at the same time, that none of the cited prior art discloses synchronous DRAM operation codes, and that the examiner found the concept was not obvious in 1990. Third, the Board erred in reversing the examiners finding that neither Bennett nor the combination of iAPX and iRAM would have rendered a singlechip synchronous DRAM obvious to a person of ordinary skill in the art in 1990.3 The Boards reliance on its own presumed expertise and on Microns attorney argument does not constitute substantial evidence, nor does it justify disregarding the examiners detailed and explicit factual findings on this issue. V. ARGUMENT A. Standards of Review 1. Claim Construction Is Reviewed de Novo

[C]laim construction by the PTO is a question of law that [this Court] review[s] de novo. In re Baker Hughes Inc., 215 F.3d 1297, 1301 (Fed. Cir. 2000).

The Court need not reach this issue if it reverses the Board on the precharge limitation. 45

Case: 13-1339

Document: 18-1

Page: 56

Filed: 06/18/2013

2.

Factual Findings of the Board Are Reviewed for Substantial Evidence Based on the Entire Record, Including Any Findings of Fact Made by the Examiner

This Court reviews factual findings of the Board for substantial evidence, based on a review that is confined to the factual record compiled by the Board. In re Gartside, 203 F.3d 1305, 1315 (Fed. Cir. 2000). Under the substantial evidence standard of review, [the Court] search[es] for evidence, clearly set forth in the record below, to justify the conclusions that the Board has drawn. Brand v. Miller, 487 F.3d 862, 868 (Fed. Cir. 2007). This Court has also expressly held that the Boards opinion must explicate its factual conclusions, enabling [the Court] to verify readily whether those conclusions are indeed supported by substantial evidence contained within the record. Gartside, 203 F.3d at 1314 (citing Gechter v. Davidson, 116 F.3d 1454, 1460 (Fed. Cir. 1997)). The record in an inter partes reexamination proceeding includes any findings of fact made by the examiner. Thus, regardless of whether the Board adopts or incorporates the examiners findings into its opinion, all of the examiners findings must be considered part of the record on appeal and must be given appropriate weight in determining whether the Boards decision is supported by substantial evidence. See id. at 1312 ([S]ubstantial evidence review involves examination of the record as a whole, taking into account evidence that both justifies and detracts from an agencys decision. (emphases added) (citing Universal Camera 46

Case: 13-1339

Document: 18-1

Page: 57

Filed: 06/18/2013

Corp. v. NLRB, 340 U.S. 474, 487-88 (1951))); see also St. Clair Intellectual Prop. Consultants, Inc. v. Canon Inc., 412 F. Appx 270, 276 (Fed. Cir. 2011) (unpublished) (stating that an examiner in reexamination can be considered one of ordinary skill in the art). 3. The Board Cannot Simply Rely on Its Own Expertise; It Must Point to Concrete Evidence in the Record to Support Its Findings

In Zurko, this Court made clear that, in determining patentability, the Board cannot simply rely on common sense or its own expertise without pointing to specific factual support in the record: With respect to core factual findings in a determination of patentability, however, the Board cannot simply reach conclusions based on its own understanding or experienceor on its assessment of what would be basic knowledge or common sense. Rather, the Board must point to some concrete evidence in the record in support of these findings. To hold otherwise would render the process of appellate review for substantial evidence on the record a meaningless exercise. In re Zurko, 258 F.3d 1379, 1386 (Fed. Cir. 2001) (footnote omitted); accord Brand, 487 F.3d at 869 ([I]n the context of a contested case, it is impermissible for the Board to base its factual findings on its expertise, rather than on evidence in the record, although the Boards expertise appropriately plays a role in interpreting record evidence.).

47

Case: 13-1339

Document: 18-1

Page: 58

Filed: 06/18/2013

4.

The Boards Ultimate Conclusion of Obviousness Is Reviewed de Novo

Obviousness is a question of law that [this Court] review[s] de novo with underlying factual findings. In re NTP, Inc., 654 F.3d 1279, 1297 (Fed. Cir. 2011); see also In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1378 (Fed. Cir. 2007) (Although based on determinations of underlying facts, which we review for substantial evidence, the ultimate conclusion of obviousness is a legal question, which we review de novo.). B. The Board Erred in Construing Precharge Information in Claim 33 as Nonfunctional Descriptive Material that Need Not Be Shown in the Prior Art

As part of its obviousness analysis, the Board construed precharge information in claim 33 as nonfunctional descriptive material, which the Board concluded need not be present in the prior art to establish invalidity. (A59; A62.) Under this erroneous construction, the Board essentially eliminated the precharge information limitation altogether, making it unnecessary to show in the prior art. As legal authority for doing so, the Board cited In re Ngai, 367 F.3d 1336, 1338 (Fed. Cir. 2004), which in turn relies on In re Gulack, 703 F.2d 1381, 1385 (Fed. Cir. 1983). (A59.) The Boards construction, however, is legally faulty and unsupported by any controlling authority. As explained above, the operation code recited in claim 33 tells the DRAM that the next operation is a read and tells the sense amplifiers whether or not to 48

Case: 13-1339

Document: 18-1

Page: 59

Filed: 06/18/2013

precharge after that read. (Supra III.B.4.) Even though, as the Board noted, the claim does not recite the act of precharging the sense amplifiers (A59), for a DRAM to operate as described in claim 33, it must receive an operation code that includes both a read instruction and precharge information. Indeed, claim 29 specifically requires the DRAM to sample this operation code. Receiving both pieces of information in the same operation code changes the timing of bus access compared to the prior art and significantly improves the efficiency of the system. (Supra III.B.4.) Thus, claim 33s requirement that precharge information be included in the same operation code as the read instruction cannot be dismissed as mere nonfunctional material since it provides necessary information to the DRAM and affects bus timing in a critical way that distinguishes the prior art. Indeed, it bears repeating that in all of the secondary references relied on by the Board (Olson, Wicklund, and Bowater), the read/write operation and precharge operation are sent in necessarily separate signals, with the bus tied up between those signals, whereas the invention recited in claim 33 requires only a single, brief bus access because the read instruction and precharge information are contained in the same operation code. This is not a trivial or nonfunctional distinction, as the Board erroneously held. It is a basic tenet of patent law that the claims define the scope of the patent right, and every limitation of the claim must be considered to determine validity or 49

Case: 13-1339

Document: 18-1

Page: 60

Filed: 06/18/2013

infringement. See Warner-Jenkinson Co. v. Hilton Davis Chem. Co., 520 U.S. 17, 29 (1997) (Each element contained in a patent claim is deemed material to defining the scope of the patented invention . . . .); Panduit Corp. v. Dennison Mfg. Co., 810 F.2d 1561, 1576 (Fed. Cir. 1987) (A disregard of claim limitations, as here, would render claim examination in the PTO meaningless.); Bicon, Inc. v. Straumann Co., 441 F.3d 945, 950-52 (Fed. Cir. 2006) ([C]laims are interpreted with an eye toward giving effect to all terms in the claim.). The Boards reliance on Ngai is inapposite. That case refers to the rule that alleged inventions that consist of nothing more than printed matter to be observed by a human generally do not fall within the class of patentable statutory subject matter. Ngai, 367 F.3d at 1339; see also AstraZeneca LP v. Apotex, Inc., 633 F.3d 1042, 1063-65 (Fed. Cir. 2010) (citing Ngai for proposition that adding new instructions to a known product is simply an addition of unpatentable subject matter). The printed matter cases limit patentable subject matter in order to prevent inventors from patenting material useful and intelligible only to the human mind. In re Lowry, 32 F.3d 1579, 1583 (Fed. Cir. 1994). Here, by contrast, the bits that provide precharge information are not even read by humans; they are sent to DRAMs. The printed matter cases have no factual relevance where the invention as defined by the claims requires that the information be processed not by the mind but by a machine, the computer. 50 Id. (citation

Case: 13-1339

Document: 18-1

Page: 61

Filed: 06/18/2013

omitted). Thus, the printed matter exception is not even applicable in the context of computerized bits. The Boards construction also runs afoul of this Courts claim-differentiation doctrine. As this Court has held, claim differentiation create[s] a presumption that each claim in a patent has a different scope. Comark Commcns, Inc. v. Harris Corp., 156 F.3d 1182, 1187 (Fed. Cir. 1998) (holding that proposed construction of claim 1 would violate the doctrine of claim differentiation by rendering claim 2 superfluous); see also Tandon Corp. v. USITC, 831 F.2d 1017, 1023 (Fed. Cir. 1987). Here, the Boards construction, which ignores precharge information as mere nonfunctional descriptive material, would render claim 33 superfluous as compared to claim 29, and is therefore presumptively incorrect. See Comark, 156 F.3d at 1187. C. The Boards Alternative Determination that an Operation Code Containing Both a Read Instruction and Precharge Information Would Have Been Obvious in 1990 Lacks Substantial Evidence

There is no dispute that the primary references relied on by the Board, i.e., Bennett, iAPX, and iRAM, do not discuss precharging at all and, therefore, do not disclose the concept of combining a read instruction and precharge information in a single operation code. (Supra III.D.1.) There is also no dispute that the secondary references relied on by the Board, i.e., Olson, Wicklund, and Bowater, likewise fail to disclose the concept of combining read and precharge operations in 51

Case: 13-1339

Document: 18-1

Page: 62

Filed: 06/18/2013

a single operation code since those operations are in fact uncombinable in the prior art, i.e., they must be carried out by separate transition-based signals. (Supra III.D.2.) Thus, despite the Boards ipse dixit conclusion that this concept would have been obvious to a person of ordinary skill in the art in 1990, not one of the six prior-art references relied upon by the Board actually discloses or enables it. If the concept were so obvious, as the Board unilaterally insists, why has Micron been unable to find a single reference that discloses this allegedly obvious concept prior to 1990? In fact, the unrebutted evidence presented to the examiner overwhelmingly showed that this concept was not obvious at the time of the invention. For

instance, Rambus presented two unrebutted declarations of Mr. Murphy, an expert in the field, who testified that, in prior-art devices like those described in Bennett and iAPX, (1) a write instruction and a precharge instruction came from different sources, making it impractical and illogical to combine them into one operation code; and (2) the triggers for the write and precharge instructions were different events because the operations necessarily occurred at different times, and a whole new system would have been required to combine them in a single operation code. (Supra III.E.1.a.) Specifically, Mr. Murphy explained that the localized operation of precharging DRAMs after the completion of a row access is not something that 52

Case: 13-1339

Document: 18-1

Page: 63

Filed: 06/18/2013

would be handled by the processors in Bennett that generate requests to memory as those processors would not be aware of the page boundaries for the particular memory devices within the memory modules of Bennett. (A2480[73].)

Mr. Murphy explained that the same is true of the iAPX and iRAM systems. (A2427-29[56-59]; A2467[31]; A2470[38].) Notably, Micron presented no expert evidence to the contraryonly attorney argument. Thus, the unrebutted evidence showed that, in Bennett and iAPX, precharge information, if it existed, would have come from within the large memory, while requests to memory, such as read, write, or read-modify-write, would have been sent across the primary bus from the CPU. (A2480-81[73]; A2427-29[56-59]; A2467[31]; A2470[38].) Because one request would have been generated internally and the other externally, it would have been impractical, and certainly not obvious, to combine them into a single operation code from an external source. (A2480-81[73]; A2427-29[5659]; A2467[31]; A2470[38].) Rambus further presented unrebutted evidence that one of ordinary skill in the art looking at Olson, Wicklund, and Bowater would not have tried to combine read and precharge instructions into a single operation code because those references teach away from such a solution. For instance, Wicklund teaches a prediction algorithm for determining when to precharge, and Bowater teaches a timing algorithm that assumes, in every case, that the next memory access will be 53

Case: 13-1339

Document: 18-1

Page: 64

Filed: 06/18/2013

in page mode. (Supra III.D.2.b-c.) Olson discloses an algorithm in which the memory controller does not precharge the sense amplifiers if the system is idle, to allow the next access to be to the same row. (A1763[1:8-14].) All of these precharge algorithms point away from combining a read/write instruction with precharge information, as Mr. Murphy explained. (A2481-84[76-87].) And as plainly shown by Bowaters Figure 2, in prior-art DRAMs, RAS is both used to hold a row open during column operations (held low for the duration) and signal a precharge when this is no longer necessary (by transitioning high). Thus, it is not simply a matter of deciding to combine these two operations; a whole new control signal scheme would be required, which is entirely missing from the prior-art references. This Court has held that, when the prior art teaches a different way of accomplishing a result from that taken by the applicant, that constitutes a teaching away from the invention. Pozen Inc. v. Par Pharm., Inc., 696 F.3d 1151, 1164-65 (Fed. Cir. 2012); see also In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994) (As reference may be said to teach away when a person of ordinary skill, upon reading the reference, . . . would be led in a direction divergent from the path that was taken by the applicant.). Accordingly, the Board erred in not considering that all of the secondary references it relied uponOlson, Wicklund, and Bowater teach away from the claimed invention. 54

Case: 13-1339

Document: 18-1

Page: 65

Filed: 06/18/2013

Moreover, the Boards findings regarding the alleged obviousness of the precharge limitation are unsupported by any record evidence, let alone substantial evidence. Consider, for instance, the Boards finding that it would have been obvious to a person of ordinary skill in the art in 1990, based on iAPX, iRAM, and Olson, to combine both a read instruction and precharge information in the same operation code. (A62-63.) The Board begins its analysis by acknowledging that the examiner found precisely the opposite, i.e., that this concept would not have been obvious from iAPX and iRAM in view of Olson: [T]he Examiner maintains that iAPX and Olson fails to disclose sending the precharge information of claim 33 with the first operation code which has block size information as recited in claims 26 and 29. (A62.) The Board next posits its erroneous claim-construction argument, in which it attempts to read the precharge information limitation out of claim 33 altogether. (Id.) Finally, as a fallback, the Board asserts as follows: But even if the information is functional, on this record, Microns response is persuasive. For example, sending one operation code with information as required to perform certain read operations would have been obvious for the purpose of keeping related read control information together in an existing (or modified) iAPX operation code. Based on the foregoing discussion, Micron shows that the Examiner erred in refusing to maintain the obviousness rejection of claim 33 based on iAPX, iRAM, and Olson.

55

Case: 13-1339

Document: 18-1

Page: 66

Filed: 06/18/2013

(A62-63.) Note that the Board provides no citations to the record to support this cursory conclusion that the claimed operation code would have been obvious in view of iPAX, iRAM, and Olson. Nor does the Board provide any explanation as to why the examiners opposite conclusion should be disregarded. Upon rehearing, the Board again made a conclusory finding without any supporting citations to the record. Specifically, in response to Rambuss argument that the Board overlooked evidence showing that the alleged combination would be unworkable because the controller in the iAPX system would have no perspective on where the page boundaries are located, (A29 (citation omitted)), the Board asserted: These arguments are beyond the scope of the memory device claimed which does not require a page mode or controllers. And even if a controller or other requestor is somehow implicitly required, skilled artisans would have recognized that an iAPX modified controller would have had sufficient perspective to send a precharge signal to an integrated DRAM in the same code as the read signal since the precharge signal normally would have followed the controllers read signal in prior art systems (especially where the claims do not require a page mode; i.e., a mode which requires such perspective according to Rambus). (Id.) Again, the Board failed to cite to any record evidence to support its opinion as to what skilled artisans would have recognized in 1990 in view of iAPX, iRAM, and Olson. The above passages may reflect the Boards opinion, but they are wholly divorced from, and unanchored to, the factual record, and in fact show a 56

Case: 13-1339

Document: 18-1

Page: 67

Filed: 06/18/2013

lack of understanding of the contrary facts in the record. See Brand, 487 F.3d at 870 (reversing Boards finding where the Board did not anchor in the record its conclusion that an artisan would have deduced the claimed invention from a particular drawing). Similarly, with Bennett, the Boards conclusory finding that the combined operation code would have been obvious was based on the unsupported assumption that the read-modify-write command disclosed in Bennett comprises multiple functions (which it does not) and that those functions would have rendered it obvious in 1990 to combine the unrelated read/write instruction and precharge information of a DRAM, which are issued from different sources and cannot overlap, into a single operation code. (A58; A25; A27.) The Boards reliance on the conventional read-modify-write command is a red herring. As Rambus

explained (but the Board ignored), that instruction does not contain two independent and distinctly identifiable instructions. (See A3324-25.) That is, when Bennetts system is instructed to read-modify-write to a memory address, as shown in Figure 34 of Bennett, it reads the data in that memory address and writes a new value to that same address, all based on a single instruction. (See A1357; A1635[91:13-23].) The read-modify-write instruction has no independent portion that would allow it to, for example, only read or only write. (A1357;

57

Case: 13-1339

Document: 18-1

Page: 68

Filed: 06/18/2013

A1635[91:13-23].) The Board failed to cite any contrary evidence or provide any explanation as to why Rambuss evidence on this topic should be ignored. This type of ipse dixit conclusion by the Boardcompletely devoid of record support and failing to address any of the contrary evidence, including even the examiners opposing viewpointcannot constitute substantial evidence. As this Court has held, [u]nder the substantial evidence standard of review, [the Court] search[es] for evidence, clearly set forth in the record below, to justify the conclusions that the Board has drawn. Brand, 487 F.3d at 868 (emphasis added). Here, the Board failed to justify its obviousness conclusions, and there is simply no evidence in the record to support those conclusions. In fact, the great weight of the evidence clearly contradicts the Boards findings of obviousness. For instance, the same examiners findings in the related 037 reexamination further show that it would not have been obvious to employ an operation code that includes both a read/write instruction and precharge information. Specifically, the examiner considered the fact that Olson, Wicklund, and Bowater all include precharging, yet he found that none of these references discloses an operation code containing both a read/write instruction and precharge information. (A3530

(concluding that Olson contains no suggestion to include any precharge information with the same operation code since [Olson does not teach] precharging automatically after written data); A3533; A3538 (concluding that Wicklund does 58

Case: 13-1339

Document: 18-1

Page: 69

Filed: 06/18/2013

not disclose . . . [a] precharging instruction [that] came within the same operation code as the specifying of the sampling of the data to be written); A3541 (concluding that there is no support for including [precharge] information along with write request since that would defeat the purpose of the essential counter [in Bowater] (emphasis added)); see also A3550; A3553; A3466 (concluding in 120 reexamination that iAPX and Olson fail[ ] to disclose the sending of [precharge] information to the memory device with respect to the same operation code that is used to perform a read operation).) The examiner also acknowledged the fact that Bennett includes an operation code and that the prior art generally includes the traditional read-modify-write command, yet he still concluded that combining a read/write instruction with precharge information in the same operation code would not have been obvious to a person of ordinary skill in the art in 1990. (A3552; A3544; A3536-37; A3580-81; A3553.) Given all of Rambuss evidence supporting nonobviousness, including the unrebutted testimony of Mr. Murphy, the operation of the prior art, the examiners findings in the 037 reexamination, and the objective evidence of nonobviousness (see supra III.C), and given the Boards lack of evidence to support its opposite conclusion, the Boards determination of obviousness should be reversed as lacking substantial evidence. See, e.g., Brand, 487 F.3d at 870-71.

59

Case: 13-1339

Document: 18-1

Page: 70

Filed: 06/18/2013

D.

The Board Erred in Finding, Without Any Prior-Art Examples of Synchronous DRAMs, that Synchronous DRAMs Would Have Been Obvious Based on Bennett or iAPX in View of iRAM

The record created by the examiner shows that synchronous DRAMs would not have been obvious based on either Bennett or iAPX in view of iRAM. None of the prior-art references discloses synchronous DRAMs. As the evidence

overwhelmingly established, Bennetts Versatile Busthe backbone of a mainframe computer system circa 1982was not designed to directly interface with a single DRAM chip, in the manner suggested by the Board. And, as the examiner explained and the evidence established, iAPX, like Bennett, was designed to attach many asynchronous DRAMs to a single memory controller, which was then attached to the primary bus. iRAM, while disclosing a single chip attached to a bus, did not disclose any memory chip attached synchronously to a bus because iRAMs memory was not clocked. Accordingly, the Boards finding that synchronous DRAMs would have been obvious in 1990 is not supported by substantial evidence. See In re Glatt Air Techniques, Inc., 630 F.3d 1026, 1029-30 (Fed. Cir. 2011). As explained above, Bennett discloses only one type of memory that Micron asserted could have included DRAMs, namely, Bennetts large memory. As also explained above, this large memory in Bennett would have contained many DRAM chips connected to a controller on a separate, secondary bus and operated 60

Case: 13-1339

Document: 18-1

Page: 71

Filed: 06/18/2013

asynchronously. (Supra III.E.1.b.) Indeed, an expert retained by Micron in litigation readily conceded that the large memory described in Bennett would have been composed of multiple chips, and that each chip would have at least one memory array. (A3683; see also A2383; A2475-76[55]; A3764 (Samsung

conceding same in 037 reexamination request).) Thus, although the Versatile Bus in Bennett operates on a clock signal (i.e., synchronously), to the extent DRAMs would have been implemented in Bennett (despite not being taught), the evidence shows that each individual DRAM would have operated on a separate, secondary bus connected to a memory controller, and they would have been controlled asynchronously, as in iAPX, Olson, Wicklund, and Bowater. (A3683; A2383; A2475-76[55]; A3764.) Indeed, Bennetts disclosure of a large memory

including up to 232 addresses of 32-bit words (A2475-76[55] (citing A1637[95:58-59])), a number that even now cannot be contained on a single DRAM chip, shows that Bennett did not envision attaching a single DRAM chip directly to the primary bus for its large memory (see A2413[15]). For those reasons, the examiner correctly found that Bennett did not disclose the synchronous DRAM limitation or render it obvious. (A1140.) The Board, however, attempted to piece together other teachings from Bennett to assert that Bennett would have rendered obvious the use of synchronous DRAMs. Specifically, the Board relied on Bennetts use of memory chips as 61

Case: 13-1339

Document: 18-1

Page: 72

Filed: 06/18/2013

preferred devices over cards. (A57.) The Board presumably was referring to Bennetts use of synchronous very large scale integrated circuit (VLSIC) devices. (See A1595[12:14-38].) But VLSIC devices were not, contrary to the Boards assertions, simply memory chips, nor were they interchangeable with DRAMs. Indeed, VLSIC devices did not necessarily include memory at all. (See id. (broadly discussing VLSIC as a single chip, but not mentioning memory); A1596[14:19-24] (same); A1607[35:59-68] (stating that Users may be

implemented as modules, or multi-chip devices, and that [t]hese modules may themselves be implemented as VLSIC devices, but never stating that memory in particular could be implemented as anything other than a multi-chip device); A1609[39:57-63] (describing layout of VBI); A1622-23[66:9-67:18] (comparing asynchronous and synchronous primary buses).) And the Boards only response to Rambuss argument that Bennetts large memory is too large to fit on a single chip even todayasserting that the memory did not have to be that large and hypothesizing that Bennett in 1982 envisioned bigger chips than are even available today (A21-22)simply constitutes conjecture, not evidence. The Board did not point to any evidence suggesting that a person of ordinary skill in the art in 1990 would have been motivated to implement DRAMs as anything other than the known prior-art configuration, e.g., as multiple asynchronous DRAMs connected asynchronously via a secondary bus to a memory 62

Case: 13-1339

Document: 18-1

Page: 73

Filed: 06/18/2013

controller, as shown in iAPX, Olson, Wicklund, and Bowater. This entire group could have been connected to Bennetts primary bus via a VBI interface, and there appears to be no dispute that such a configuration would not have satisfied the synchronous DRAM limitation of claim 33, because the DRAMs themselves would have been asynchronous. Moreover, the evidence is overwhelming that this is how a person of ordinary skill in the art in 1990 would have implemented DRAMs in Bennett, had he chosen to do so. (A2475-76[55]; A2477-78[61-64]; A3683; A2383; A3764.) The Board never really acknowledged Rambuss evidence on this point but concluded, nevertheless, that it would have been obvious to implement a singlechip synchronous DRAM in Bennett merely because asynchronous DRAMs were ubiquitous at the time. (A56-57; see A21.) Contrary to the Boards apparent logic, the mere fact that asynchronous DRAMs were ubiquitous in 1990 does not, in and of itself, mean it would have been obvious to implement them as synchronous memory chips, solving all the problems solved by the 120 inventors in creating a new DRAM interface and overcoming the difficulties identified by Mr. Murphy with attaching a single DRAM chip directly to a primary bus. To the extent DRAMs were ubiquitous in 1990, they were ubiquitous as groups of asynchronous DRAMs controlled by a separate controller. Indeed, to this day, even synchronous DRAMs are controlled by a separate controller on a dedicated 63

Case: 13-1339

Document: 18-1

Page: 74

Filed: 06/18/2013

bus and not connected directly to a primary bus, and neither Micron nor the Board has cited any real-world examples of a single DRAM chip attached directly to a primary bus. The Boards conclusion that there was an implicit motivation to improve the speed and power of chips (A57 n.18) is simply an example of hindsight bias, which the Supreme Court and this Court have warned against. See Graham v. John Deere Co., 383 U.S. 1, 36 (1966) (warning against a temptation to read into the prior art the teachings of the invention in issue and instructing courts to guard against slipping into [the] use of hindsight (citation omitted)); NTP, 654 F.3d at 1298-99 (reversing Boards finding of obviousness because Board improperly relied on hindsight reasoning to piece together elements to arrive at the claimed invention). In hindsight, the 120 patents synchronous DRAM

technology has proven to be faster than the prior-art asynchronous DRAM technology, but the fact that the invention constitutes an improvement on the prior art cannot render a claim obvious. NTP, 654 F.3d at 1298-99 (Care must be taken to avoid hindsight reconstruction by using the patent in suit as a guide through the maze of prior art references, combining the right references in the right way so as to achieve the result of the claims in suit. (citation omitted)). In short, there is no evidence to support the Boards finding that a person of ordinary skill in the art in 1990 would have been motivated to take a single DRAM 64

Case: 13-1339

Document: 18-1

Page: 75

Filed: 06/18/2013

chip out of a large prior-art DRAM array, such as that shown in iAPX, Olson, Wicklund, or Bowater, and attach it directly to the primary bus of Bennetts mainframe computer system, without any intervening memory controller or secondary bus. To be sure, there is no evidence that anyone skilled in the art ever did so, nor is there any evidence suggesting that they would have wanted to do so in 1990. Further compounding its error, the Board failed to cite any evidence (let alone substantial evidence) showing that a clock would have been provided to a DRAM in Bennett. The Board dismissed Rambuss clock argument as a

variation of Rambuss numerous single-chip arguments. (A24.) In other words, the Board apparently assumed that the claimed clocked DRAM would have necessarily been present in Bennett based on its previous assumption that Bennett renders obvious a synchronous DRAM device. Yet this is simply circular. As explained above, providing a clock to a DRAM chip and supplying clock-based operation codes and clock-based data timing to render the device synchronous was a counterintuitive step over the asynchronous prior-art devices. (Supra III.B.2.) Thus, the Board erred in failing to provide evidence that the clocked DRAM limitation was rendered obvious by any of the prior-art references. Cf. NTP, 654 F.3d at 1302 (reversing Boards finding of inherent anticipation when prior-art reference was silent on the limitation). 65

Case: 13-1339

Document: 18-1

Page: 76

Filed: 06/18/2013

Similarly, with respect to the combination of iAPX and iRAM, the Board reversed the examiner, despite the examiners abundant evidence and with no supporting evidence of its own. First, it is undisputed that iAPX does not disclose synchronous DRAM. Second, with respect to iRAM, although the Board asserted that the reference disclosed synchronous iRAM chips (A61), that assertion was unsupported by even Microns argument. In fact, both Mr. Murphy and the EPO explained that iRAMs synchronous chips have nothing to do with receiving an external clock signal, a hallmark of synchronous chips, and the iRAM references drawing of the chip itself supports that. (See supra III.E.2.b.) Likewise, there was no evidence to support the Boards conclusion that combining iAPX and iRAM would somehow result in a single synchronous DRAM chip. As the examiner found, supported by the testimony of the architects of iAPX, replacing the memory in iAPX with iRAM chips would have entailed replacing each asynchronous DRAM chip with an iRAM chip, resulting in an array of asynchronous iRAM chips collectively connected to a memory controller. (Supra III.E.1.b.) As the Intel designers explained, the DRAMs of iAPX were designed to be interchangeable with other types of memory devices, and replacing the whole memory card with a single iRAM chip would defeat that goal of iAPX since the MCU [memory control unit] would have to be physically removed and placed into each individual iRAM. (A1178; see also A1177.) The examiners 66

Case: 13-1339

Document: 18-1

Page: 77

Filed: 06/18/2013

evidence also included several functions of iAPX that would have been inoperable if the entire memory card had been replaced with a single iRAM chip. Specifically, iAPXs error checking and correction could occur only if the chips were collectively controlled by a single memory controller, and the same is true for iAPXs use of a spare DRAM chip to replace any faulty DRAM chip. (A118081.) The Board, rather than addressing all of that evidence, simply determined, as it had with Bennett, that integrating functions onto a single chip is an implicit motivation to create that chip. (A59-60.) But, again, the Boards reliance on such an implicit motivation to create what turned out to be a faster chip, as described in the 120 patent, merely constitutes impermissible hindsight bias. NTP, 654 F.3d at 1298-99. VI. CONCLUSION For the foregoing reasons, this Court should reverse the Boards decision finding claim 33 of the 120 patent invalid as obvious and reinstate the examiners finding of nonobviousness.

67

Case: 13-1339

Document: 18-1

Page: 78

Filed: 06/18/2013

Dated: June 18, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen Aidan C. Skoyles FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 Attorneys for Appellant Rambus Inc.

68

Case: 13-1339

Document: 18-1

Page: 79

Filed: 06/18/2013

CERTIFICATE OF COMPLIANCE I certify that the foregoing BRIEF FOR RAMBUS INC. contains 13,887 words as measured by the word-processing software used to prepare this brief.

Dated: June 18, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen Aidan C. Skoyles FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000

Case: 13-1339

Document: 18-1

Page: 80

Filed: 06/18/2013

CERTIFICATE OF SERVICE I hereby certify that copies of the foregoing BRIEF FOR RAMBUS INC. were served upon registered counsel by operation of the Courts CM/ECF system on this 18th day of June, 2013. Henry A. Petri, Jr. Novak Druce Connolly Bove + Quigg, LLP 1875 Eye Street, NW, 11th Floor Washington, DC 20001 henry.petri@novakdruce.com

/s/ Kay Wylie