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Datasheet TL072
Datasheet TL072
Features
Low Power Consumption Wide Common-Mode and Differential Voltage Ranges Low Input Bias and Offset Currents Output Short-Circuit Protection Low Total Harmonic Distortion0.003% Typ Low Noise Vn= 18nV
Typ at f=1kHz
General Description
The JFET-input operational amplifiers in the TL072 are similar to the TL082, with low input bias and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL072 ideally suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a single monolithic chip.
High Input ImpedanceJFET-Input Stage Internal Frequency Compensation Latch-Up-Free Operation High Slew Rate13V/s Typ Common-Mode Input Voltage Range Includes VCC+ SOP-8L: Available in Green Molding Compound (No Br, Sb) Lead Free Finish/ RoHS Compliant (Note 1)
Applications
Ordering Information
TL 072 S G - 13
Package S : SOP-8L Green G : Green Packing
Device TL072SG-13
Notes:
Package Code S
13 Tape and Reel Quantity Part Number Suffix 2500/Tape & Reel -13
1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html 2. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
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LOW NOISE JFET INPUT OPERATIONAL AMPLIFIERS
Pin Assignments
(1) Dual channel SOP-8L
( Top View ) OUTPUT1 1 INVERTING INPUT1 2 NON-INVERTING INPUT1 3 VCC- 4 SOP-8L 8 VCC+ TL072 7 OUTPUT2 6 INVERTING INPUT2 5 NON-INVERTING INPUT2
Pin Descriptions
Pin Name OUTPUT1 INVERTING INPUT1 NON-INVERTING INPUT1 VCCNON-INVERTING INPUT2 INVERTING INPUT2 OUTPUT2 VCC+ Pin No. 1 2 3 4 5 6 7 8 Description Channel 1 Output Channel 1 Inverting Input Channel 1 Non-inverting Input Supply Voltage Channel 2 Non-inverting Input Channel 2 Inverting Input Channel 2 Ouput Supply Voltage
Block Diagram
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(Note 8)
Parameter Human Body Model ESD Protection Machine Model ESD Protection Supply Voltage + (Note 3) Supply Voltage - (Note 3) Input voltage (Notes 3 and 5) Differential input Voltage, VID (Note 4) Duration of output short circuit (Note 6) Power Dissipation (Note 7) Operating Junction Temperature Range Storage Temperature Range
Unit KV V V V V V mW o C o C
3. ALL voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC-. 4. Differential voltage are at the non-inverting input terminal with respect to the inverting input terminal. 5. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15V, whichever is less. 6. The output may be shorted to ground or either supply. Temperature and/or supply voltage must be limited to ensure that the dissipation rating is not exceeded. 7. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD=(TJ(max)-TA)/ JA . Operating at the absolute maximum TJ of 150 can affect reliability
(Note 8)
Rating
Unit V C
15
-40 to +85
8. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
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LOW NOISE JFET INPUT OPERATIONAL AMPLIFIERS
Electrical Characteristics
Symbol VIO
Min
Typ. 3 18 5 65
Max 6 8
Unit mV V/ oC
vIO
VOM
Temperature Coefficient VO=0, RS=50, TA= full range of Input Offset Voltage TA=25 oC Input Offset Current VO=0 TA= full range o TA=25 C Input Bias Current VO=0 TA= full range Common Mode Input Voltage Range o RL=10k, TA=25 C Maximum Peak RL10k, Output Voltage Swing TA= full range RL2k Large Signal Differential VO=10V, RL2k Voltage Amplification Unity Gain Bandwidth Input Resistance Common Mode Rejection Ratio Supply Voltage Rejection Ratio (VCC/VIO) Supply Current (each amplifier) Crosstalk Attenuation TA=25 oC TA= full range
100 2 200 20
pA nA pA nA V
11 12 12 10 50 25
-12~+15 13.5
V 200 3 1012
TA=25 oC VIC=VICRmin, VO=0 RS=50, TA=25 oC VCC=9 to 15V VO=0 RS=50, TA=25 oC VO=0, TA=25 oC No load AVD=100, TA=25 oC V =10V, CL=100pF, RL=2k Slew Rate at Unity Gain I (See Figure 1) Rise Time VI=20mV, RL=2k, CL=100pF (See Figure 1) Overshoot Factor Equivalent Input Noise Voltage RS=20 f=1kHz f=10 Hz to 10kHz RS=20, f=1kHz VIrms=6V, AVD=1, RL2k, RS1k, f=1kHz SOP-8L (Note 9) SOP-8L (Note 9)
75 80
Vn In THD JA JC
Notes:
V
pA HZ
Equivalent Input Noise Current Total Harmonic Distortion Thermal Resistance Junction-to-Ambient Thermal Resistance Junction-to-Case
%
o
C/W C/W
9. Test condition for SOP-8L: Devices mounted on FR-4 substrate PC board, with minimum recommended pad layout.
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LOW NOISE JFET INPUT OPERATIONAL AMPLIFIERS
Maximum Peak Output Voltage vs Temperature VOM -Maximum Peak Output Voltage(V) 15.0 RL=10k 12.5 RL=2k 10.0 7.5 5.0 2.5 0.0 0
Maximum Peak Output Voltage vs Load Resistance VOM -Maximum Peak Output Voltage(V) 15.0 VCC=15V 12.5 10.0 TA =25 See Figure 2
Maximum Peak Output Voltage vs Frequency 15.0 VOM -Maximum Peak Output Voltage(V) VCC=15V 12.5 RL=10k TA =25 See Figure 2 VCC=10V
7.5 5.0
VCC=5V
2.5 0.0 0 0.1 10 0.2 0.4 0.7 100 1 2 4 71000 10 Load Resistance (k)
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(Continued)
Maximum Peak Output Voltage vs Frequency VOM -Maximum Peak Output Voltage(V) VOM -Maximum Peak Output Voltage(V) 15.0 RL=2k 12.5 10.0 VCC=10V 7.5 5.0 2.5 0 0.0 100 VCC=15V TA =25 See Figure 2 15.0
Maximum Peak Output Voltage vs Frequency TA =-40 12.5 10.0 7.5 5.0 2.5 0.0 0 10000 10k TA =25 TA =85 VCC=15V RL=2k See Figure 2
VCC=5V
1k
10k
100k
1M
10M
Frequency (Hz)
400k1000000 1M
4M 10000000 10M
Frequency (Hz)
Input Bias Current vs Temperature 100.00 100 VCC=15V IIB -Input Bias Current(nA) 10.00 10 AVD -Differential Voltage Amplification (V/mV) 1000.0 1000 400 200 100 100.0 40 20 10 10.0 4 2 1.0 1
1 1.00
0.10 0.1
-50
100
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(Continued)
Supply Current vs Supply Voltage 2.0 1.8 ICC -Supply Current(mA) ICC -Supply Current(mA) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.0 0 2 4 6 8 10 12 14 16 |Vcc| Supply Voltage (V) TA =25 No Signal No Load 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.0 -50
Total Power Dissipation vs Temperature 150 PD -Total Power Disspation(mW) 125 100 75 50 25 0 -50 -25 0 25 50 75 100 TA-Free Air Temperature ( ) VCC=15V No Signal No Load CMRR -Common-Mode Rejection Ratio(dB) 98
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(Continued)
Equivalent Input Noise Voltage vs Frequency Vn - Equivalent Input Noise Voltage(nV/ Hz) 50 VCC=15V 40 RS=20 TA =25 30 Input and Output Voltages(V) AVD=10 4 2 0 6
20
Output -2 -4 -6
10
0 10 10
40
100
400 1000 1k
4k 10000 10k
-0.5
0.5
Frequency (Hz)
1.5 2 t-Time-s
2.5
3.5
Total Harmonic Distortion vs Frequency 11 0.4 Total Harmonic Distortion(%) VCC=15V AVD=1 VO -Output Voltage(mV) VI(RMS)=6V 0.1 0.1 0.04 TA =25 24 20 16 12 8 4 10% 0 28
Overshoot
90
-4 400 1k 4k 10k 1 10 Frequency(Hz) 40k 100k 100 -0.1 0 0.1 0.2 0.3 0.4 t-Elapsed Time-s 0.5 0.6 0.7
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Test Circuit
10k 1k OUT RL CL=100pF
Marking Information
(1) SOP-8L
( Top View )
8 5
G : Green YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal Code
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Package Information
(1) Package type: SOP-8L
( All Dimensions in mm )
3.85/3.95
5.90/6.10
0.10/0.20
0.254 0.62/0.82
Detail "A"
0.35max. 45
7~9
Detail "A"
0/8
1.27typ 4.85/4.95
0.3/0.5
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