3138

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013

Modeling and Reduction of Conducted EMI of Inverters With SiC JFETs on Insulated Metal Substrate
Xun Gong, Member, IEEE, Ivan Josifovi c, Member, IEEE, and Jan Abraham Ferreira, Fellow, IEEE
AbstractThis paper presents the suppression of conducted common-mode (CM) electromagnetic interference (EMI) in an inverter for motor drive with discrete silicon carbide (SiC) JFETs attached on top of the insulated metal substrate (IMS). The EMC performance of the IMS inverter is compared with that of a heat sink inverter in a similar circuit layout. Both are under the same inuence of parasitic capacitive couplings between the SiC JFET drains and the substrate base plate. It is found that although the application of conventional CM lters effectively suppresses the emitted noise in the low-frequency (LF) range, the inuence of this capacitive coupling results in slight or no improvement in the middle-frequency (MF) and high-frequency (HF) ranges. To deal with this problem, a system CM equivalent circuit model with extracted parasitic parameters is proposed. The model is able to evaluate the lter insertion losses over a broad conducted EMI frequency band, which is essential to achieve an optimized lter design balanced between performance and cost. The presented experimental and calculated results form the step-by-step guideline that effectively suppresses the generated EMI to comply with the standard prescribed by IEC61800-3 C2: Qp. Index TermsCommon mode (CM), electromagnetic interference (EMI), insulated metal substrate (IMS), motor drive, silicon carbide (SiC).

I. INTRODUCTION

HE high switching speed and temperature capabilities of silicon carbide (SiC) offer many signicant performance improvements for the switching devices in power electronics [1]. New SiC JFETs increase the power efciency of converters, accelerate the miniaturization of power electronic systems, and enable them to operate under less stringent cooling requirements [2]. To keep pace with the resulting power density increase, thermal management must be enhanced due to the reduced magnetic component surface area available for cooling. Among those thermal managements for medium power converters, implementing the insulated metal substrate (IMS) is one of the most effective methods [3], [4]. On the other hand, IMS is also well known for its susceptibility to electromagnetic interference (EMI). Fig. 1(a) illustrates the typical structure of

Fig. 1. (a) Construction of the IMS. (b) Photograph of the investigated IMS inverter prototype. (c) Extensive capacitive couplings created due to the implementation of the discrete SiC JFETs attached on top of the IMS.

Manuscript received May 29, 2012; revised July 31, 2012; accepted September 20, 2012. Date of current version December 24, 2012. Recommended for publication by Associate Editor P. Tenti. The authors are with the Electrical Power Processing Group, Department of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, 2628 CD, Delft, The Netherlands (e-mail: x.gong@tudelft.nl; i.josifovic@tudelft.nl; J.A.Ferreira@tudelft.nl). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2221747

IMS. It can be seen that because of the very thin dielectric layer (typically 40180 m) placed between the circuit copper foil and the metal (typically aluminum or copper) base plate, a large amount of stray capacitance is formed, which creates a path closing a loop with considerable EMI propagations especially for the high-frequency (HF) noise. This effect becomes much more critical when the IMS is used to cool active power devices, especially when SiC JFETs drain plates are attached on top as illustrated in Fig. 1(b). The capacitive couplings, together with the fast switching of SiC, result in signicant degradation to the conducted/radiated EMC performance and also to the

0885-8993/$31.00 2012 IEEE

GONG et al.: MODELING AND REDUCTION OF CONDUCTED EMI OF INVERTERS WITH SiC JFETs ON INSULATED METAL SUBSTRATE

3139

circuit operation performance [5]. As a result, costly and increased ltering is needed to suppress the emitted noise below the stringent EMI standard. This has become the main barrier to the increase in power density. Additionally, EMC design methods that enable EMC performance evaluation over a broad frequency band have become the trend and are increasingly popular these years. It is possible to predict the EMC and prevent the situation where noise is suppressed in some frequency range but is amplied in other frequency range. This is especially critical when dealing with the increased HF noise of the inverters with SiC JFETs on top of the IMS. Filter designs targeting a restricted low-frequency (LF) band may become inadequate. In the past, many EMI lter design methods were developed to suppress the conducted EMI [6][10]. However, most of them fail to predict EMI and require a trial-and-error process for a certain HF range. For example, a common-mode (CM) input lter design procedure is introduced in [11] for a three-phase buck-type rectier. A two-stage CM lter is designed to suppress the conducted EMI to comply with the standard. However, the suppression performance beyond 10 MHz is overlooked due to the oversimplication of the model. A step-by-step design procedure is proposed in [12] and proved to be effective below 1 MHz, unfortunately beyond that frequency, the ltering performance prediction begins to deviate. In [13] and [14], lters are designed according to the noise level at the start (150 kHz) or at the frequency requiring maximum attenuation in the conducted frequency range. However, other frequencies are not considered. A broadband EMI lter design has been presented in [15]; however, the small signal-based methods require very precise measurements, which are not easily obtained. This paper investigates and proposes an equivalent circuit model to suppress the conducted EMI for a SiC JFET inverter for motor drives. The inverter is implemented with discrete SiC JFETs and their corresponding external antiparallel diodes are directly attached on top of the IMS copper foil, which creates extensive capacitive coupling between the power device drain and the aluminum metal plate. A comprehensive and broadband lter design is proposed to handle this problem. First, a simplied equivalent circuit model is established. The CM current waveforms of the system are obtained from simulation to verify the inuence of the capacitive couplings. The conducted EMI of the IMS inverter prototype is compared with a heat sink inverter for similar circuit layout as both are under the same inuence of parasitic capacitive couplings. Second, the proposed model is further developed with the extraction of all the parasitic elements to evaluate the lter performance. The group of calculated insertion losses shows good agreement with the measurements over a broad conducted EMI range, making the proposed model signicantly better in predicting and handling the increased EMI in the HF range. Third, different lter designs are compared with the model and the optimal lter design that results in the best attenuation with respect to the IMS capacitive coupling is identied. Finally, based on the modeling results, methods to suppress the HF EMI are proposed. The emitted EMI of the IMS inverter driven motor system is effectively suppressed to comply with the IEC61800-3 Qp standard.

Fig. 2.

Capacitive couplings in the inverter bridge leg conguration.

II. CAPACITIVE COUPLING INFLUENCE OF THE IMS A. IMS Capacitive Coupling Inuence on CM Fig. 2 illustrates the conguration of the IMS inverter bridge leg that shows the capacitive coupling effects. Due to the very thin dielectric layer placed between the circuit copper foil and the metal base plate, large amount of stray capacitance is formed between the signal layer and the metal plate. Due to safety reasons when the metal plate is required to be connected to the earth, those stray capacitors create extensive EMI coupling paths, closing loops with considerable EMI noise propagations. To illustrate the effect, a simplied CM equivalent circuit model for the IMS inverter driven motor system is established as shown in Fig. 3(a), where Vinv is the CM noise source. R1 , C1 , and L1 are the equivalent impedance of LISN, L2 is the lumped inductance between LISN and inverter switches, Ycap is the added lter capacitor, Lout is the lumped inductance between inverter output and motor, Rsf , Cw f 1 , Cw f 2 , and Lg f are the equivalent impedance of the motor with cables, and Ig is the earth current. The critical elements are L3 , C2 , L4 , and C3 which represent the created stray elements network between the circuit foil layer and the IMS base plate. The simulated waveforms of the CM current Ig with and without the stray element network are shown in Fig. 3(b). A CM capacitor (also known as Y capacitor) is applied at the inverter input. It can be seen that the CM parasitic oscillations and overshoots are signicantly increased under the inuence of the stray elements network. The oscillation frequency becomes lower because of the increased capacitance at the inverter output side. The elements applied in the model are determined based on the following considerations. The photograph of the investigated IMS inverter prototype is shown in Fig. 4(a). The SiC JFET (SJEP120R100) is packaged in TO-247 with the drain of Al back plate and the surface area As = 20.3 15.3 = 310.59 mm2 . The added antiparallel diode (C2D05120A) is in TO-220 package with the cathode surface area Ad = 9.65 14.3 = 138.0 mm2 . The total surface area As + Ad causes parasitic capacitance Cdh 1 and Cdh 2 (see Fig. 2). With 0.08-mm-thick Kapton dielectric layer (r = 5)

3140

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013

PCB traces is directly measured with an impedance analyzer (Aglient 4294A). The rest are extracted through curve tting of the impedance-frequency characteristics. The details can be found in [16]. B. IMS Capacitive Coupling Inuence on DM In addition to degradation of the EMC CM performance by introducing extensive noise propagation paths, the IMS capacitive couplings also greatly deteriorate the DM EMC performance. The rst reason is the interaction within one inverter leg that consists of two switches. As shown in Fig. 2, when IMS base plate is oating, the parasitic capacitors Cdh 1 , Cdh 2 , and Cdh 3 are in Y -connection. Through Y transformation, the three capacitors are equivalently added in parallel to the switch, appearing as the increased values of parasitic capacitance Cj p 1 and Cj p 2 . As a consequence, two degradation effects are produced on DM performance: 1) slow down the switching speed, which potentially leads to the increased switching losses and prolonged switching transient time; and 2) increase the current overshoot at the switching transients. When one switch is switched ON/OFF (e.g., J2 in Fig. 2), the parasitic capacitor Cj p 1 in parallel to the opposite switch determines the overshoot magnitude. Therefore with the increased capacitance in parallel to the switch, the parasitic overshoot magnitude and oscillations are also increased. Moreover, the shoot-through problems are potentially induced. It must be mentioned that these capacitive couplings also have the effect of slowing down the switching speed of J1 and J2 , and consequently decreasing the values of switching dv/dts. This could be a benet from the EMC point of view. However, because the parasitic capacitance value is relatively small and it is dependent on the imposed voltage, this impact is majorly negative. The second reason is the noise couplings among the three inverter legs. According to the PWM switching technique, when the upper switch in one inverter leg [e.g., J1 in Fig. 1(c)] is switched ON, while at the mean time, the lower switch in another inverter leg [e.g., J4 in Fig. 1(c)] is at OFF state, pulsed voltage (dv/dt) appears between these two inverter leg output nodes. As a result, the existing parasitic capacitors between the leg output nodes and IMS base plate form a path that propagates the HF noise from one node to the other. Therefore, each of the three inverter leg output nodes acts as a noise source, which is expressed by E1 , E2 , and E3 as shown in Fig. 1(c). C. Experiment Conguration The EMC performance of the IMS SiC JFET inverter prototype is compared with a heat sink SiC JFET inverter with similar layout as shown in Fig. 4(a) and (b), respectively. The difference in their layout designs is due to the following reasons: for IMS inverter, the drain plates of the SiC JFETs are soldered on top of the IMS copper coil directly to achieve better cooling effect. Therefore, the foil traces of the dc bus are soldered together with the drain/cathode plate of the semiconductors. The components are placed closer to each other. However for the heat sink inverter, the thermal Sil-pads ( 150 m) must be inserted between to provide electrical insulation; therefore, the PCB is used

Fig. 3. (a) Simplied CM equivalent circuit model of the IMS inverter system for CM current overshoot and oscillations. (b) Comparison of the simulated waveforms from the model with and without the capacitive couplings.

Fig. 4. Photographs of the SiC JFET inverters. (a) IMS inverter: very thin dielectric layer between the SiC JFET drain plate and the aluminum base ( 80 m). (b) Heat sink inverter: SiC JFET drain and SiC diode cathodes are insulated by thermal Sil-pads from the aluminum heat sink ( 150 m).

Cdh 2 is calculated as Cdh 2 = r 0 (As + Ad )/l = 249 pF. Cdh 3 is the parasitic capacitance between the dc bus and the substrate. For a heat sink inverter with a power PCB, Cdh 3 is much lower than one with the IMS due to its larger distance between the dc bus and the substrate. The thickness of the isolation pad is inversely proportional to the parasitic capacitance. In the threephase inverter, all the top six power devices (SiC JFETs plus SiC diodes) are at the same potential as the dc+ bus voltage; therefore, they all contribute to the equivalent value of Cdh 1 . According to the PWM switching technique, pulsed dv/dts appear between the node of bridge-leg output phase (summed area of SiC JFET drain and diode cathode at the low side) and the substrate. In the model, the total capacitance of C2 + C3 in the stray element network represents the coupled capacitance which is 6. Cdh 2 = 1494 pF. The lumped inductance of the

GONG et al.: MODELING AND REDUCTION OF CONDUCTED EMI OF INVERTERS WITH SiC JFETs ON INSULATED METAL SUBSTRATE

3141

HF performance since the HF noise level is even higher than that of the LF range. As a result, it is crucial to suppress the increased noise level to comply with the standard IEC61800-3 C2 Qp. Therefore for the IMS inverter, the added capacitor that is conventionally found in the lter must be carefully designed due to the extensive capacitive coupling inuence. In the following sections, this impact is explained with a CM equivalent circuit model and the lter insertion loss calculations. The lter design that is able to suppress this inuence is presented.
Fig. 5. Experiment conguration of the IMS and heat sink SiC JFET inverters.

III. BROAD BAND MODELING TO PREDICT THE FILTER INSERTION LOSSES The treatment of the crucial HF noise in the IMS inverter requires the applied method to predict the relative noise attenuation performance in a broad conducted EMC range. Therefore, the situation as shown in Fig. 6 where noise is suppressed in LF range but increases in MF and HF ranges can be predicted and avoided. In the following sections, the model shown in Fig. 3(a) is further rened by adding detailed parasitic elements. The goal is to provide a broadband prediction on the lter insertion loss, thereby selecting the optimal lter design that has better performance while requiring less ltering components. All the following experiments are performed on the IMS inverter. This study focuses only on the CM noise which plays the predominant role in total EMI spectrum of motor drive system [17], [18]. The DM noise is not considered. A. Creation of the Modeling Bases The considered CM lter topologies are illustrated in Fig. 7, which are named C , LC, LCL, and LCLC, respectively. These topologies are chosen because they are widely adopted as the CM lter for inverter driven motor systems. Among them, the easy-to-implement topologiesC and LCare used to create modeling bases. The conguration with only two pairs of DM capacitors positioned in the dc bus (see Fig. 5) is taken as the case without CM lter. The noise emitted from this conguration is dened as the noise baseline. Fig. 8 shows the required lter insertion loss which is calculated according to the difference between the IEC61800-3 C2 standard and the noise baseline. The measured insertion loss of the applied C (470 nF) and LC (250 H 470 nF) lters for the IMS inverter is illustrated in Fig. 9. It can be seen that noise suppression in the MF range is not sufcient and greatly degraded. This is within the expectation due to the IMS capacitive couplings as analyzed in Section III-A. The values of the inductor and capacitor are selected with reference to the actual EMI ltering component values from commercial motor drives. Additionally, the design of the inductor value avoids saturation of the selected core. B. Final Model for Filter Insertion Losses With the insertion losses from the created experimental bases with C and LC lters as shown in Fig. 9, the model of Fig. 3(a) is further rened into the model shown in Fig. 10 which includes the detailed parasitic elements. The values of stray elements

Fig. 6. Comparison of measured total noise spectra between the IMS SiC JFET inverter and the heat sink SiC JFET inverter.

and placed between the upper and lower switches. Although the aforementioned differences exist, the EMI levels from the two inverters are comparable making it possible to characterize the capacitive coupling inuence. Because both inverter prototypes are implemented with the same type of discrete SiC JFETs and antiparallel external SiC diodes in the same package on top of the substrates, the coupling mechanism is assumed to be the same. Their experiment conguration for EMI measurement is illustrated in Fig. 5. The two inverters are placed in the same EMC testing environment with the same measuring equipments. The inverters are powered by a dc power supply at 550 V dc through an LISN (Crange VN3-100S). A 2.2-kW induction motor as the load is driven at 50 Hz modulation frequency by programming the driving signal source from a DSP. The inverter and motor are grounded to the same copper plate. The EMC spectrum analyzer is set for 9 kHz resolution bandwidth, 18 s sweep time, and peak detection mode for measurement convenience. D. EMI Comparison Fig. 6 presents the measured EMI spectra of the two inverter systems. An identical and conventional purely capacitive lter (470 nF) is placed at the input of both inverter systems. The schematic diagram of the lter is shown in Fig. 7(a). It can be seen that the emitted noise in an IMS inverter is signicantly higher than that in the heat sink inverter especially in the middle frequency (MF) range (37 MHz), which is due to the higher HF current overshoot inuenced by the extensive capacitive couplings as modeled in Fig. 3(b). Although the LF noise is dramatically suppressed, this inuence results in no improved

3142

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013

Fig. 7.

Considered lter topologies: (a) C , (b) LC, (c) LCL, and (d) LCLC.

Fig. 8. lter.

Required lter insertion loss calculated from the noise baseline without

Fig. 9. Measured lter insertion losses with the implemented CM lter of C (C = 470 nF) and LC (L = 250 H, C = 470 nF).

network is lowered in steps to capture the resonances that occur around 4.5 MHz according to the measured insertion losses of Fig. 9. Extraction of the elements including the lter and the motor with cables will be introduced in Section III-C. The voltage appearing across R1 is the emitted noise voltage measured by the spectrum analyzer. The calculated insertion losses of the IMS inverter with C and LC lters are illustrated in Fig. 11(a). It can be seen that the modeled results of Fig. 11(a) agree well with the measurements of Fig. 9. The rst spike at 2.5 MHz is caused by the CM intrinsic resonance of the motor with cables. The second spike at 4.5 MHz is caused by the resonance that occurs in the stray elements network which is fundamentally caused by the capacitive coupling inuence of the IMS inverter.

The calculated insertion losses with applied pure C lter (470 nF) at the input of both the IMS inverter and the heat sink inverter are shown in Fig. 11(b). When calculating the insertion loss for the heat sink inverter, the stray elements network in the model is removed. It can be seen that the main difference occurs at the second spike at 4.6 MHz. Additionally, the noise magnitude of the IMS inverter in the LF range is around 6 dB higher than that of heat sink inverter. The results agree well with the experimental results of Fig. 6. Therefore, the established model is proven to be capable of evaluating the lter performance over a broad conducted frequency band. The spike at 4.5 MHz is mainly caused by the capacitive couplings and is critical for the lter design.

GONG et al.: MODELING AND REDUCTION OF CONDUCTED EMI OF INVERTERS WITH SiC JFETs ON INSULATED METAL SUBSTRATE

3143

Fig. 10.

Final model with extracted elements.

Fig. 11. Comparison of the modeled lter insertion losses. (a) IMS inverter with the implemented CM lter of C (470 nF) and LC (250 H, 470 nF) (b) between the heat sink inverter (without stray elements network of capacitive couplings) and the IMS inverter with C (470 nF) CM lter.

Fig. 12. Elements extraction for the motor with cables based on the curve tting of the CM impedance-frequency characteristic. (a) Experiment conguration. (b) Experimental result as opposed to calculated result.

C. Elements Extraction The elements extraction method is based on curve tting of the equivalent circuits CM impedance-frequency characteristic for each circuit portion in the system. In addition to the stray capacitance between the circuit copper foil and the substrate base plate, the other main parasitic components are determined as follows. Fig. 12(a) illustrates the experimental setup to measure the CM impedance-frequency characteristic of the motor with

cables. The Agilent 4294A impedance analyzer is used as the measurement tool. The test pins of the analyzer are connected to the three-phase motor terminals and the motor PE cable, respectively. The measured and calculated results are illustrated in Fig. 12(b). The extracted elements are Lout , Lw f , Cw f 1 , Rsf , Cw f 2 , Rg f , and Lg f as shown in Fig. 10. The total CM capacitance Cw f 1 + Cw f 2 is derived from the LF slope k1 . The capacitance in the circuit parallel branch with fewer components (Cw f 1 ) determines the slope of k2 in the MF range. The summed

3144

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013

Fig. 13. Model of the applied LCL lter [L 1 = 250 H, C 1 = 400 nF, L 2 = 200 H shown in Fig. 7(c)] with extracted elements.

Fig. 15. lters.

Comparison of the calculated insertion losses with different applied

clamping. It can be seen that the connection of current probe introduces an additional inductance of 7 nH at 5 MHz where the main frequency is the concern. It hardly shows any effect in the HF range beyond 10 MHz. Because of the higher inductance in the power cables (L2 and Lout as shown in Fig. 10), the current probe inductance is neglected in the model. D. Evaluation of Different Filter Topologies With the developed model, the calculated insertion losses of each lter (C , LCL, and LCLC) are compared against each other as shown in Fig. 15. The selection of the component values is based on four considerations. 1) The components should fulll the calculated lter attenuation to the level required by the insertion loss as shown in Fig. 8. 2) The component values in each order of the lter are the same; therefore, the selected lter topologies as shown in Fig. 7 are comparable in volume. 3) The core saturation caused by both CM and DM leakage magnetic elds must be avoided; therefore, the applied lter inductors is able to fulll their attenuation ability. It can be seen with reference to the required insertion loss that the LCL lter exhibits the best performance which effectively suppresses the noise spike in the MF range while still obtaining adequate attenuation ability in the HF range. The results are illustrative of an optimized EMI lter design with no excessive components involved. Although the LCLC lter utilizes more components, it does not give better performance in suppressing the capacitive coupling inuence. The aforementioned benets can only be achieved by the broadband modeling of the conducted EMI. IV. TOWARD THE STANDARD COMPLIANCE A. Implementation of the LCL Filter Consequently, LCL CM lter is selected as the nal design and implemented in the IMS inverter driven motor system. The component values are the same as those in the calculated results shown in Fig. 15. The achieved EMI spectrum is compared with that of the LCLC lter which is shown in Fig. 16. It can be seen that the measurements agree well with the calculations of Fig. 15. The noise spike caused by the capacitive couplings at MF range (around 4.5 MHz) is effectively suppressed. However,

Fig. 14. Measured inductance-frequency characteristic of a 110 nH wire with and without being clamped by the current probe.

inductance of Lout + Lw f + Lg f and capacitance Cw f 2 create the resonance of rst zero point Z1 . Rsf determines the magnitude of Z1 . The summed inductance of Lout + Lg f and capacitance Cw f 2 create the resonance of fz 2 in the HF range. More details of the model calculations are presented in [16]. Elements extraction for the lter is split into different orders of the inductor or capacitor, respectively. Each inductor or capacitor branch is measured and extracted separately. The CM equivalent circuit model of the applied LCL lter is shown in Fig. 13, where the model branch of the third-order inductor (250 H) comprises Rf 1 , Cf 1 , and Lf 1 , the model branch of the rst-order inductor (200 H) comprises Rf 2 , Cf 2 , and Lf 2 , and the model branch of the second-order capacitor (400 nF) comprises Rf 3 , Cf 3 , and Lf 3 . Taking the CM capacitor parasitics extraction as an example, Rf 3 and Lf 3 are the self equivalent series resistance (ESR) and the equivalent series inductance (ESL) of the capacitor, respectively. In the measured impedance-frequency characteristic of the capacitor, Cf 3 is extracted according to the slope in the LF range. The capacitor parasitic inductance Lf 3 is calculated from the resonance occurring in the MF range. Rf 3 is equal to the minimum value of the impedances. Another important factor that needs to be considered is the inuence of adding current probe to the parasitics during the measurements. This impact is determined according to the measured results as shown in Fig. 14 which is the measured inductancefrequency characteristic of a 110 nH wire with and without probe

GONG et al.: MODELING AND REDUCTION OF CONDUCTED EMI OF INVERTERS WITH SiC JFETs ON INSULATED METAL SUBSTRATE

3145

Fig. 16. Comparison of the measured total noise spectra between the system with the LCLC (250 H, 400 nF, 200 H, 400 nH) lter and LCL (250 H, 400 nF, 200 H) lter.

Fig. 18. Comparison of the measured total noise spectra before and after applying the improved approaches.

Fig. 17. Comparison of the calculated LCL lter insertion loss between before and after optimization.

to the case after optimization. With the added ferrite beads, the inductance at the inverter output phases (Ls 3 ) is increased to 3 H. The comparison of the experimental results before and after applying the optimization solutions is shown in Fig. 18. It can be seen that the HF noise is effectively reduced as predicted by the model. The LF noise reduction is resulted from the increase of the inductance of the rst-order lter. Combined with the effects, the emitted EMI of the IMS inverter system is effectively suppressed to comply with the standard prescribed by IEC61800-3 C2 Qp.

the noise at the initial frequency of 150 kHz and HF range still fails to conform to the standard. This can, however, be achieved by a few adjustments which will be introduced in the following section. B. Optimization To further reduce the LF noise, the inductance of the rstorder lter [L2 in Fig. 7(c)] is increased to 280 H. Reduction of the HF noise can be achieved with two solutions. 1) Decrease the grounding inductance (Lf 3 in Fig. 13) of the Y -capacitors. The grounding inductance of Y -capacitors is lowered by using copper strips instead of wires to connect the capacitor leads to the ground. 2) Increase the inductance which must be effective for HF noise suppression between the inverter output phases and the motor (Ls 3 in Fig. 10). The HF effective inductance of Ls 3 is increased to 3 H by adding ferrite beads (ZCAT3035 TDK) across the unshielded cables that connect the inverter and the motor. The equivalent circuit of the ferrite bead is a series connection of a frequencydependent resistor and inductor, which damps and dissipates the HF oscillations. Consequently, the calculated results are shown in Fig. 17, where the application of LCL (250 H 400 nF 200 H) shown in Fig. 15 corresponds to the case before optimization. Application of the proposed HF improvement solutions corresponds

V. CONCLUSION Applying IMS to improve thermal management of motor drives potentially deteriorates the EMC performance, even more so when SiC power devices are used and attached directly on top of the IMS. The extensive capacitive couplings between the circuit copper foil and the IMS base plate result in the increased current overshoot and oscillations. It is shown that with conventional CM lters, the emitted noise in the IMS inverter is signicantly higher than that in the heat sink inverter when they are implemented in the same circuit layout. Although the LF noise is effectively suppressed, the inuence of capacitive coupling results in little or even no improvement in the MF and HF noise ranges. In this paper, a CM equivalent circuit model which enables prediction of the lter performance over a broad conducted EMI frequency range is developed. Through the model, the optimal lter design is achieved through the insertion loss comparison of various lter topologies. It is found that for the IMS inverter, the performance of the third-order lter LCL is much better than the others which include the fourthorder lterLCLC; hence, the lter size and cost are reduced. Additionally, the methods to further improve HF performance, reducing the crucial parasitics and increasing the inductance at inverter output phases, are proposed according to the modeling results. Consequently, the emitted EMI of the IMS inverter is effectively suppressed to comply with the IEC61800-3 C2 Qp standard.

3146

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013

REFERENCES
[1] J. Biela, M. Schweizer, S. Wafer, and J. W. Kolar, SiC versus Si Evaluation of potentials for performance improvement of inverter and dcdc converter systems by SiC power semiconductors, IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 111, 2010. [2] P. Friedrichs, SiC power devices for industrial applications, in Proc. IEEE Power Electron. Conf., Sapporo, Japan, Jun. 2010, pp. 32413248. [3] C. Van Godbold, A. V. Sankaran, and L. J. Hudgins, Thermal analysis of high-power modules, IEEE Trans. Power Electron., vol. 12, no. 1, pp. 311, Jan. 1997. [4] S. Asai, M. Funaki, H. Sawa, and K. Kato, Fabrication of an insulated metal substrate (IMS), having an insulating layer with a high dielectric constant, IEEE Trans. Compon., Manuf. Technol., vol. 16, no. 5, pp. 499 504, Aug. 1993. [5] I. Josifovic, J. Popovic, and J. A. Ferreira, Improving SiC JFET switching behavior under inuence of circuit parasitics, IEEE Trans. Power Electron., vol. 27, no. 8, pp. 38433854, Aug. 2012. [6] M. Hartmann, H. Ertl, and J. Kolar, EMI lter design for a 1 MHz, 10 kW three-phase/level PWM rectier, IEEE Trans. Power Electron., vol. 26, no. 4, pp. 11921204, Apr. 2011. [7] G. Grandi, D. Casadei, and U. Reggiani, Analysis of common- and differential-mode HF current components in PWM inverter-fed ac motors, in Proc. IEEE Power Electron. Spec. Conf., 1998, vol. 2, pp. 1146 1151. [8] L. Palma and P. Enjeti, An inverter output lter to mitigate dv/dt effects in PWM drive system, in Proc. 17th Annu. Appl. Power Electron. Conf., 2002, vol. 1, pp. 550556. [9] D. A. Rendusara and P. N. Enjeti, An improved inverter output lter conguration reduces common and differential modes dv/dt at the motor terminals in PWM drive systems, IEEE Trans. Power Electron., vol. 13, no. 6, pp. 11351143, Nov. 1998. [10] J. L. Kotny, X. Margueron, and N. Idir, High-frequency model of the coupled inductors used in EMI lters, IEEE Trans. Power Electron., vol. 27, no. 6, pp. 28052812, Jun. 2012. [11] T. Nussbaumer, M. Heldwein, and J. W. Kolar, Common mode EMC input lter design for a three-phase buck-type PWM rectier system, in Proc. IEEE Appl. Power Electron. Conf. Expo., TX, Mar. 2006, pp. 714. [12] F. Shih, D. Chen, Y. Wu, and Y. Chen, A procedure for designing EMI lters for ac line applications, IEEE Trans. Power Electron., vol. 11, no. 1, pp. 170181, Jan. 1996. [13] H. Akagi and T. Shimizu, Attenuation of conducted EMI emissions from an inverter-driven motor, IEEE Trans. Power Electron., vol. 23, no. 1, pp. 282290, Jan. 2008. [14] C. Po-Shen and L. Yen-Shin, Effective EMI lter design method for three-phase inverter based upon software noise separation, IEEE Trans. Power Electron., vol. 25, no. 11, pp. 27972806, Nov. 2010. [15] V. Tarateeraseth, K. Y. See, F. G. Canavero, and R. W.-Y. Chang, Systematic electromagnetic interference lter design based on information from in-circuit impedance measurements, IEEE Trans. Electromagn. Compat., vol. 52, no. 3, pp. 588598, Aug. 2010. [16] X. Gong and J. A. Ferreira, Extracting the parameters of a common mode EMI equivalent circuit model for a drive inverter, in Proc. IEEE Power Electron. Conf., Sapporo, Japan, Jun. 2010, pp. 892899. [17] K. Pengju, Y. Jiang, and F. C. Lee, Common mode EMI noise characteristics of low-power acdc converters, IEEE Trans. Power Electron., vol. 27, no. 2, pp. 731738, Feb. 2012. [18] X. Lei and S. Jian, Conducted common-mode EMI reduction by impedance balancing, IEEE Trans. Power Electron., vol. 27, no. 3, pp. 10841089, Mar. 2012.

Xun Gong (M12) received the B.Sc. and M.Sc. degrees in control theory and control engineering from the Dalian University of Technology, Dalian, China, in 2006 and 2009, respectively. During his master thesis, he developed a soft-starter prototype for asynchronous electrical machines. In 2008, he became a Ph.D. Researcher at Electrical Power Processing Group, Delft University of Technology, Delft, The Netherlands. His research interests include EMC strategies, high power density design, and construction of motor drives. His current research interests include power electronics, design and implementation of high power density, and high efciency power converters.

Ivan Josifovi c (M09) was born in Kraljevo, Serbia, in 1982. He received the B.Sc. and M.Sc. degrees from the Department of Power, Electronics, and Telecommunication from the University of Novi Sad, Serbia, Faculty of Technical Sciences, in 2005 and 2007, respectively. In his master project, he realized a dc motor drive and applied dSpace development system for implementation of a control algorithm. He is currently a Researcher with Electrical Power Processing (EPP) Group, Delft University of Technology, Delft, The Netherlands. His research interests include high power density packaging and automated construction of power electronics. His work involves implementation of compact and efcient power converters using wide-band gap semiconductors and innovative passive components.

Jan Abraham Ferreira (M88SM01F05) was born in Pretoria, South Africa. He received the B.Sc.Eng. (cum laude), M.Sc..Eng. (cum laude), and Ph.D. degrees in electrical engineering from the Rand Afrikaans University, Johannesburg, South Africa. In 1981, he did research on battery vehicles at the Institute of Power Electronics and Electric Drives, Technical University of Aachen, and worked in industry as a Systems Engineer at ESD (Pty) Ltd from 1982 to 1985. From 1986 until 1997, he was at the Faculty of Engineering, Rand Afrikaans University, where he held the Carl and Emily Fuchs Chair of Power Electronics in later years. In 1998, he became a Professor of Power Electronics and Electrical machines at the Delft University of Technology, Delft, The Netherlands. Dr. Ferreira was the Chairman of the South African Section of the IEEE during 19931994. He is the Founding Chairman of the IEEE Joint IAS/PELS Benelux Chapter. He served in 19951996 as the Chairman of the IEEE IAS Power Electronic Devices and Components committee. He is an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS and served as treasurer and vice president meetings of the IEEE PELS. He was the Chairman of the CIGRE SC14 National Committee of the Netherlands from 1999 to 2002 and is a member of the executive committee of the European Power Electronic Association EPE Society (19992003; 2008present).