Saa 7824

INTEGRATED CIRCUITS
DATA SHEET
T
AF
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SAA7824
D
CD audio decoder, digital servo &
filterless DAC with integrated
pre-amp & laser control
Preliminary specification 2002 Mar 26
Draft PhonIC data sheet
File under Integrated Circuits, IC01
Philips Semiconductors Preliminary specification
CD audio decoder, digital servo & filterless DAC

SAA7824
with integrated pre-amp & laser control
CONTENTS 7.15.3 Loop characteristics

7.15.4 FIFO overflow
1 FEATURES 7.16 Servo part
2 GENERAL DESCRIPTION 7.16.1 Diode signal processing
3 ORDERING INFORMATION 7.16.2 Signal conditioning
7.16.3 Focus servo system
4 QUICK REFERENCE DATA 7.16.4 Radial servo system
5 BLOCK DIAGRAM 7.16.5 Off-track counting
6 PINNING 7.16.6 Defect detection
7.16.7 Off-track detection
7 FUNCTIONAL DESCRIPTION
7.16.8 High-level features
7.1 Data acquisition & HF data path 7.16.9 Driver interface
7.2 Decoder part
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7.16.10 Laser interface
7.2.1 Principal operating modes of the decoder 7.17 Microcontroller interface
7.2.2 Decoding speed and crystal frequency 7.17.1 Microcontroller interface (4-wire bus mode)
7.2.3 Lock-to-disc mode 7.17.2 Microcontroller interface (I2C-bus mode)
7.2.4 Standby modes 7.17.3 Decoder registers and shadow registers
7.3 Crystal oscillator 7.17.4 Summary of functions controlled by decoder
AF
7.4 Data slicer and bit clock regenerator registers 0 to F
7.5 DC offset cancellation 7.17.5 Summary of functions controlled by shadow
7.5.1 Offset cancellation registers
7.5.2 Reading back the DC offset value 7.17.6 Summary of servo commands
7.6 Demodulator 7.17.7 Summary of servo command parameters
7.6.1 Frame sync protection
8 LIMITING VALUES
7.6.2 EFM demodulation
7.7 Subcode data processing 9 CHARACTERISTICS
7.7.1 Q-channel processing 10 OPERATING CHARACTERISTICS
7.7.2 EIAJ 3 and 4-wire subcode (CD graphics) (SUBCODE INTERFACE TIMING)
interfaces
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11 OPERATING CHARACTERISTICS (I2S-BUS
7.7.3 V4 subcode interface TIMING)
7.7.4 CD-text interface
7.8 FIFO and error corrector 12 OPERATING CHARACTERISTICS
7.8.1 Flags output (CFLG) (MICROCONTROLLER INTERFACE TIMING)
7.9 Audio functions 13 APPLICATION INFORMATION
7.9.1 De-emphasis and phase linearity 14 PACKAGE OUTLINE
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7.9.2 Digital oversampling filter
15 SOLDERING
7.9.3 Concealment
7.9.4 Mute, full-scale, attenuation and fade 15.1 Introduction to soldering surface mount
7.9.5 Peak detector packages
7.10 DAC interface 15.2 Reflow soldering
7.10.1 Internal bitstream digital-to-analog 15.3 Wave soldering
converter (DAC) 15.4 Manual soldering
7.10.2 External DAC interface 15.5 Suitability of surface mount IC packages for
7.11 EBU interface wave and reflow soldering methods
7.11.1 Format 16 DATA SHEET STATUS
7.12 KILL features 17 DEFINITIONS
7.12.1 The KILL circuit
7.12.2 Silence injection 18 DISCLAIMERS
7.13 Audio features off 19 PURCHASE OF PHILIPS I2C COMPONENTS
7.14 The versatile pins interface
7.15 Spindle motor control
7.15.1 Motor output modes
7.15.2 Spindle motor operating modes
2002 Mar 26 2

SAA7824
1 FEATURES
• Decoder and servo parts based upon SAA732X design
(original features maintained).
• Software compatibility maintained with SAA732X by
using similar register structure (new features controlled
from new shadow registers).
• 1X, 2X, & 4x speed.
• LF (servo) signals converted to digital representations • Integrated CD-text decoder with separate micro
by 6 oversampling bitstream ADCs. interface.
• HF part summed from signals D1-D4 and converted to a • Dedicated 4MHz or 12MHz clock output for
digital signal by a data slicer. microcontroller (configurable).
• On chip buffering and filtering of the diode signals from • Configured for N-sub monitor diode.
the mechanism for signal optimisation.
• On-chip clock multiplier allows the use of 8.4672 or
• Selectable DC offset cancellation of quiescent
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16.9344 MHz crystals or ceramic resonators
mechanism voltages and dark currents.
• On-chip laser power control (up to 120mA).
2 GENERAL DESCRIPTION
• Laser on/off control, including ‘soft’ start control (zero to
nominal power in 1ms). The SAA7824 is a CD audio decoder IC which combines
output power throughout laser life.
components.
AF
• Monitor control and feedback circuit to maintain nominal
• Dynamic element matching DAC with minimal external
• DAC performance of -80dB THD+N and 90dB SNR

A-weighted.
• Separate left and right channel digital silence detect
available on KILL pins.
• Digital silence detection on internal data and loop-back
the function of the SAA732X IC with the pre-amp and laser
control functions previously found in the (A)DALAS IC. The
design is intended to reduce the external component count
and hence BOM.
Supply of this Compact Disc IC does not convey an
implied license under any patent right to use this IC in any
Compact Disc application.
(external) data.
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• 5 versatile pins, 2 input & 3 output.
3 ORDERING INFORMATION
TYPE PACKAGE
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NUMBER NAME DESCRIPTION VERSION

SAA7824HL LQFP80 plastic low profile quad flat package; 80 leads (lead length SOT315-1
1.0 mm); body 12 × 12 × 1.4 mm
2002 Mar 26 3

SAA7824
4 QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VDDC Supply voltage, digital core 1.65 1.8 1.95 V
VDDP Supply voltage, digital pad cells 3.0 3.3 3.6 V
VDDA Supply voltage, analogue 3.0 3.3 3.6 V
IDD supply current − 60 − mA
fxtal crystal frequency 8.4672 - 16.9344 MHz
Tamb ambient temperature 0 − +70 °C
Tstg storage temperature −55 − +125 °C
S/NDAC onboard DAC signal-to-noise ratio − −90 − dB
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AF
R
D
2002 Mar 26 4

SAA7824
5 BLOCK DIAGRAM
EXTFILTER
D1 D2 D3 D4 R1 R2 MONITOR SENSE LPOWER
DC OFFSET COMPENSATION LASER

MONITOR POWER CON- LASER
LASER
ADC TROL LOGIC
VOLTAGE BUFFER
HF & LF CAPTURE ANTI ALIAS
IREF BIAS D1-D4

RA
GENERATOR DSIC ADC OUTPUT
VREF_OUT SUM
STAGES FO
T
CONTROL SL
PART HFPASS FILTER CONTROL FUNCTION
SCL CSLICE
DATA SLICER &
MICRO THRESHOLD CON- MOTOR MOTO1
SDA CONTROL
INTERFACE TROL
MOTO2
RAB
SILD
TEST1
TEST2
TEST3
TEST4
OSCIN
OSCOUT
CLK16
CLK4_12
TEST
TIMING
AF DIGITAL
PLL
EFM
DEMODULATOR
SRAM
AUDIO
PROCESSOR
ERROR
CORRECTOR
FLAGS
EBU
INTERFACE
SERIAL
DATA
INTERFACE
CFLG
DOBM
EF
SCLK
WCLK
R
RAM DATA
CDT_RDY ADDRESSER
CD-TEXT
CDT_DATA INTERFACE
SERIAL SCLI
CDT_CLK DATA
(LOOPBACK) WCLI
SFSY INTERFACE SDI
INTERFACE
SUB CONTROL SUBCODE
DAC_VPO
D
PROCESSOR PEAK
RCK DAC_RP
DETECT
SBSY DAC_RN
DEM DAC
DAC_LP
DAC_LN
DAC_VREF
DECODER DAC_GND
MICRO-
STATUS CONTROLLER BUF_IN_R
INTERFACE VERSATILE PINS
HEADPHONE BUF_IN_L
INTERFACE KILL BUFFERS
BUF_OUT_R
BUF_OUT_L
RESET
BUF_VPOS
V1 V2 V3 V4 V5 LKILL RKILL
BUF_GND
Fig.1 Block diagram.
2002 Mar 26 5

SAA7824
6 PINNING
SYMBOL PIN DESCRIPTION

LPOWER 1 Laser power supply
EXTFILTER 2 10 nF capacitor for Laser start-up control
MONITOR 3 Laser monitor diode
SENSE 4 OPU ground reference point for MONITOR measurement
VSSA1 5 Analogue ground 1
IREF 6 Reference current pin (24KΩ resister to analogue ground)
VDDA1 7 Analogue supply voltage 1
VREF_OUT 8 Servo reference voltage
D1 9 Diode voltage/current input (central diode signal input)
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R1 13 Diode voltage/current input (satellite diode signal input)
R2 14 Diode voltage/current input (satellite diode signal input)
CSLICE 15 10nF capacitor for adaptive HF dataslicer
VDDA2
VSSA2
OSCOUT
OSCIN
VSSA3
DAC_GND
DAC_RP
DAC_RN
DAC_VREF
DAC_LN
16
17
18
19
20
21
22
23
24
25
AF
Analogue supply voltage 2
Analogue ground 2
Crystal/resonator output
Crystal/resonator input
Analogue ground 3
Audio DAC ground
Audio DAC right channel differential output (positive)
Audio DAC right channel differential output (negative)
Audio DAC decoupling point (10uF//100nF to ground)
Audio DAC left channel differential output (negative)
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DAC_LP 26 Audio DAC left channel differential output (positive)
DAC_VPOS 27 Audio DAC positive supply
BUF_VPOS 28 Audio buffer positive supply
BUF_IN_R 29 Audio buffer right input
BUF_OUT_R 30 Audio buffer right output
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BUF_OUT_L 31 Audio buffer left output

BUF_IN_L 32 Audio buffer left input
BUF_GND 33 Audio buffer ground
LKILL 34 Kill output for left channel (configurable as open drain)
RKILL 35 Kill output for right channel (configurable as open drain)
CDT_RDY 36 CD-Text to micro ready flag
CDT_DATA 37 CD-Text data to micro
CDT_CLK 38 CD-Text micro clock
CFLAG 39 Correction flag output (open drain)
VSSD1 40 Digital ground 1
VDDD1 41 Digital supply voltage 1
SDI 42 Serial data input (loopback)
WCLI 43 Word clock input (loopback)
2002 Mar 26 6

SAA7824
SYMBOL PIN DESCRIPTION

SCLI 44 Serial bit clock (loopback)
EF 45 C2 error flag
DATA 46 Serial data output
WCLK 47 Word clock output
SCLK 48 Serial clock output
CLK16 49 16MHz clock
CLK4_12 50 Configurable 4MHz or 12MHz clock
RESET 51 Power on reset (active low)
SDA 52 Micro interface data I/O line (open drain output)
SCL 53 Micro interface clock line
RAB 54 Micro interface R/W & load control line (4-wire)
SILD 55 Micro interface R/W & load control line (4-wire)
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STATUS 56 Servo interrupt request line/decoder status register/DC offset value readback
RCK 57 Subcode clock
SUB 58 P to W subcode
SFSY 59 Subcode frame sync
SBSY
VSSD2
DOBM
VDDD2
RA
FO
SL
MOTO1
MOTO2
VSSD3
60
61
62
63
64
65
66
67
68
69
AF
Subcode block sync
Digital ground 2
Bi-phase mark output (externally buffered)
Digital supply voltage 2
Radial actuator
Focus actuator
Sledge actuator
Motor output 1
Motor output 2
Digital ground 3
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VDDD3 70 Digital supply voltage 3
V1 71 Versatile pin 1
D
TEST1 76 Test pin
TEST2 77 Test pin
TEST3 78 Test pin
TEST4 79 Test pin
LASER 80 Laser drive
2002 Mar 26 7

SAA7824
68 MOTO2
67 MOTO1
70 VDDD3
63 VDDD2
80 LASER
69 VSSD3
61 VSSD2
79 TEST4
78 TEST3
77 TEST2
76 TEST1
62 DOBM
65 FO
64 RA
75 V5
74 V4
73 V3
72 V2
71 V1
66 SL
LPOWER 1 60 SBSY
EXTFILTER 2 59 SFSY
MONITOR 3 58 SUB
SENSE 4 57 RCK
VSSA1 5 56 STATUS
IREF 6 55 SILD
VDDA1 7 54 RAB
VREF_OUT 8 53 SCL
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D1 9 52 SDA
D2 10 51 RESET
SAA7824
D3 11 50 CLK4_12
D4 12 49 CLK16
R1 13 48 SCLK
R2 14
CSLICE 15
VDDA2 16
VSSA2 17
OSCOUT 18
OSCIN 19
VSSA3 20
AF 47 WCLK
46 DATA
45 EF
44 SCLI
43 WCLI
42 SDI
41 VDDD1
DAC_GND 21
DAC_RP 22
DAC_RN 23
DAC_VREF 24
DAC_LN 25
DAC_LP 26
DAC_VPOS 27
BUF_VPOS 28
BUF_IN_R 29
BUF_OUT_R 30
BUF_OUT_L 31
BUF_IN_L 32
BUF_GND 33
LKILL 34
RKILL 35
CDT_RDY 36
CDT_DATA 37
CDT_CLK 38
CFLAG 39
VSSD1 40
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Fig.2 Pin configuration.
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7 FUNCTIONAL DESCRIPTION 7.2 Decoder part

7.1 Data acquisition & HF data path 7.2.1 PRINCIPAL OPERATING MODES OF THE DECODER
The SAA7824 removes the need for an external diode The decoding part supports a full audio specification and
signal pre-amp. can operate at single-speed (n = 1), double-speed (n = 2),
and quad-speed (n = 4). The factor ‘n’ is called the
A simplified diagram of the HF data path can be found in
overspeed factor. A simplified data flow through the
Fig.3. The high-pass filter, equalising filter, HF gain and
decoder part is illustrated in Fig.7.
adaptive slicer are all register programmable, enabling the
SAA7824 to be optimised for the intended application.
2002 Mar 26 8

SAA7824
hf_gain 5:0
d1_hf Adaptive slicer
d2_hf Summing amp bypass
67.7MHz
d3_hf -
op-amp -
d4_hf
+ comp sliced data
Vref +
- op-amp
- Equalising Threshold
op-amp
+
+ Vana Filter control
High pass filter
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Fig.3 Simplified block diagram of HF data path and adaptive slicer
7.2.2 DECODING SPEED AND CRYSTAL FREQUENCY
AF
The SAA7824 is a1x, 2x, and 4x (three speed) decoding
device, with an internal Phase-Locked Loop (PLL) clock
multiplier. Table 1 shows the playback speeds that are
achievable in conjunction with crystal frequency,
mechanism, and internal clock settings (selectable via
decoder register B).
7.2.3 LOCK-TO-DISC MODE

7.2.4 STANDBY MODES
The SAA7824 may be placed in two standby modes
selected by decoder register B (it should be noted that the
device core is still active):
• Standby 1: CD-STOP mode; most I/O functions are
switched off
• Standby 2: CD-PAUSE mode; audio output features
are switched off, but the motor loop, the motor output
and the subcode interfaces remain active; this is also
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For electronic shock absorption applications, the called a ‘Hot Pause’.
SAA7824 can be put into lock-to-disc mode. This allows
In the standby modes the various pins will have the
Constant Angular Velocity (CAV) disc playback with
following values:
varying input data rates from the inside-to-outside of the
disc. • MOTO1 and MOTO2: put in to high-impedance, PWM
mode (standby 1 and reset: operating in standby 2); put
In the lock-to-disc mode, the FIFO is blocked and the
D
in high-impedance, PDM mode (standby 1 and reset:

decoder will adjust its output data rate to the disc speed. operating in standby 2)
Hence, the frequency of the I2S-bus (WCLK and SCLK)
clocks are dependent on the disc speed. In the • SCL and SDA: no interaction; normal operation
lock-to-disc mode there is a limit on the maximum continues
variation in disc speed that the SAA7824 will follow. Disc • SCLK, WCLK, DATA, EF and DOBM: 3-state in both
speeds must always be within 25% to 100% range of their standby modes; normal operation continues after reset
nominal value. The lock-to-disc mode is enabled/disabled • OSCIN, OSCOUT, CLK16 and CLK4_12: no
by decoder register E. interaction; normal operation continues
• V1, V2, V3, V4, V5 and CFLG: no interaction; normal
operation continues.
2002 Mar 26 9

SAA7824
Table 1 Playback speeds
CRYSTAL FREQUENCY (MHz)

REGISTER B REGISTER E
8.4672 16.9344
00XX 0XXX n=1 −
01XX 0XXX − n=1
10XX 0XXX n = 2 (Note 1) −
11XX 0XXX − n = 2 (Note 1)
00XX 1XXX n = 4 (Note 1) −
01XX 1XXX − n = 4 (Note 1)
Notes
1. Voltage mode only.
T
7.3 Crystal oscillator
The crystal oscillator is a conventional 2-pin design
Table 2 External capacitor selection based upon crystal
capable of operating between 1 and 50 MHz and can also
type
operate with ceramic resonators. The external
on the internal clock settings used.
SAA7824
OSCILLATOR
AF
components used around the crystal are shown in Fig 4
along with component values (C1 & C2) for a given crystal
type in Table 2. Oscillator frequencies that can be used
with the SAA7824 are 8.4672 & 16.9344 MHz, depending
CRYSTAL LOAD
CAPACITANCE,
CL
10 pF
20 pF
30 pF
MAX. SERIES CRYSTAL
RESISTANCE,
8MHZ
<300Ω,
<300Ω,
<300Ω,
RS
16MHZ
<220Ω
<140Ω
<80Ω
EXTERNAL
LOAD
CAPACITORS,
C1 & C2
8 pF, 8 pF
27 pF, 27pF
47 pF, 47pF
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required
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and the bit clock is not output. The PLL has two registers
OSCIN
xstal
OSCOUT (8 and 9) for selecting bandwidth and equalization.
The PLL response is shown in Fig.5.
For certain applications an off-track input is necessary.
This is internally connected from the servo part (its
C1 C2 polarity can be changed by the foc_parm1 parameter),
D
but may be input via the V1 pin if selected by register C.

If this flag is HIGH, the SAA7824 will assume that its
servo part is following the wrong track, and will flag all
incoming HF data as incorrect.
Fig.4 Crystal configuration.
7.4 Data slicer and bit clock regenerator

The SAA7824 has an integrated adaptive dataslicer
which is clocked at 67MHz. The slice level is controlled by
internal current sources which are switched onto and
integrated by the external capacitor connected to the
CSLICE pin. The currents are switched under the control
of a Digital Phase-Locked Loop (DPLL).
2002 Mar 26 10

SAA7824
The measurement time of the DC offset is regulated by

new shadow register C bank 2. A longer time will yield
more accurate results but will result in greater
handbook, halfpage measurement durations.
PLL New shadow register 3 bank 3 is used to select which
loop
response diode is to be measured.
7.5.2 READING BACK THE DC OFFSET VALUE
3. PLL, LPF The micro needs to be able to read the DC offset

measurements in order to calculate the correct
cancellation value (for writing back to new shadow
f
register 7 bank 3).
2. PLL bandwidth
This is achieved by using the STATUS pin and setting
1. PLL integrator decoder register 7 to XX10. Shadow register C bank 3
MGS178
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can then be used to control the STATUS pin output (see
Table 19 for register settings).
Once the measurement time has been set and the diode
1, 2 and 3 are all programmable via decoder register 8. selected, the STATUS pin should be set to read the DC
offset ready flag (new shadow reg. C bank 3 = X01X).
7.5
Fig.5 Digital PLL loop response.
DC offset cancellation
Unwanted DC offsets can exist within the photo-diode
AF
signals and are defined as the DC present in the system
when the laser diode is switched off. They arise from
various sources of imperfection within the system such as
leakage in the photodiodes and offsets in the OPU
This signal will toggle high after the presribed
measurement time. Changing the diode selection will
result in the measurement timer automatically being
reset.
The micro can read back the measurement by setting the
STATUS pin to output the DC offset value (new shadow
reg. C bank 3 = X10X). The offset value is repeatedly
streamed out through the STATUS pin and is UART
compatible. It should be noted that the MSB is inverted
and will require re-inverting after the offset value has been
captured. Timing information for this signal can be found
R
electronics.
in Figure 6.
The SAA7824 is capable of measuring these offsets and
minimising them. The final DC cancellation value (as calculated by the
micro) can then be written to new shadow register 7 bank
7.5.1 OFFSET CANCELLATION
3. This is a multiple write register containing the
A number of registers are associated with the DC offset cancellation values for all six diodes.
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cancellation function and are given in Table 3.
2002 Mar 26 11

SAA7824
Table 3 Registers relating to DC offset cancellation
SHADEN SHADOW
ADDRESS DATA FUNCTION INITIAL
BITS REGISTER
10 C 1100 XX00 Settling time = 354 µs reset
(bank 2) DC offset XX01 Settling time = 1ms −
measurement XX10 Settling time = 2ms −
times XX11 Settling time = 10ms −
11 3 0011 0000 Select D1 reset
(bank 3) Diode 0001 Select D1 −
selection for 0010 Select D2 −
DC offset 0011 Select D3 −
measurement
−
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0100 Select D4
0101 Select R1 −
0110 Select R2 −
0111 Select D1 −
C 1100 X00X STATUS pin outputs decoder status reset
STATUS pin
control
7
DC
cancellation
levels
AF
0111
X01X
X10X
Multi-write
(9 x 4 bits)
register information
STATUS pin outputs DC offset ready
flag
STATUS pin outputs DC offset value
DC cancellation values for diodes
D1-D4 and R1-R2
See Table 20 for further information.
−
−
R
D
2.19/n ms
D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
272.1/n µs
n = disc speed
Fig.6 Serial data format for DC offset data
2002 Mar 26 12
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2002 Mar 26
Philips Semiconductors
handbook, full pagewidth
New shadow reg. 7 bank 2:
CD-TEXT CDT_RDY
0XXX = pass all data
1XXX = pass correct data only CDT_CLK
INTERFACE
CDT_DATA
1
V4
0 RCK
T
0: reg D = XX01 CD GRAPHICS
SBSY
SFSY
INTERFACE
SUB
V4 SUBCODE MICROCONTROLLER
SDA
INTERFACE INTERFACE
reg F
SUBCODE
PROCESSOR EBU
output from
data slicer
DIGITAL PLL
AND
DEMODULATOR
1:decoder
1: decoder reg
0:decoder
0:
1
0
AF
reg AA== XX0X
XX0X
reg AA=≠ XX1X
decoder reg XX1X
1: decoder reg 3 = XX10

(1fs mode)
0: decoder reg 3 ≠ XX10
INTERFACE
decoder reg A
1: no pre-emphasis detected
OR reg D = 01XX
DOBM
1: shadow reg 7 = XX1X

0: shadow reg 7 = XX0X
1
0
SCLK
WCLK
DATA
EF
13
FIFO (de-emphasis signal at V5) DAC_RP

0: pre-emphasis detected DAC_LP LN
ONBOARD
AND reg D ≠ 01XX 1
DAC DAC_RN LP
0
DAC_LN RN
RP
1 PHASE 1 Vneg
ERROR FADE/MUTE/ DIGITAL COMPENSATION 1
0 0
1
R
CORRECTOR INTERPOLATE FILTER 0 I2S/EIAJ BUS 1: shadow reg 7 = XXX1
INTERFACE 1 0: shadow reg 7 = XXX0
0
0
decoder reg 3 DE-EMPHASIS
FILTER 1: shadow reg 7 = XX1X
Internal KILL decoder 0: shadow reg 7 = XX0X
KILL reg 3
KILL V3
0 LKILL I2S/EIAJ
Loop-back RKILL 1: decoder reg 3 ≠ 101X LOOPBACK
decoder reg C 1
KILL 0: decoder reg 3 = 101X INTERFACE
D
(CD-ROM modes)
WCLI
SCLI
SDI MGS180
Preliminary specification
0:New shadow reg A bank 2 = 0XXX
1:New shadow reg A bank 2 = 1XXX
SAA7824
Fig.7 Simplified data flow of decoder functions.

SAA7824
7.6 Demodulator 7.7.3 V4 SUBCODE INTERFACE

Data of subcode channels, Q-to-W, may be read via
7.6.1 FRAME SYNC PROTECTION
pin V4 if selected via decoder register D. The format is
A double timing system is used to protect the demodulator similar to RS232 and is illustrated in Fig.9. The subcode
from erroneous sync patterns in the serial data. sync word is formed by a pause of (200/n) µs minimum.
The master counter is only reset if: Each subcode byte starts with a logic 1 followed by 7 bits
• A sync coincidence is detected; sync pattern occurs (Q-to-W). The gap between bytes is variable between
588 ±1 EFM clocks after the previous sync pattern (11.3/n) µs and (90/n) µs.
• A new sync pattern is detected within ±6 EFM clocks of The subcode data is also available in the EBU output
its expected position. (DOBM) in a similar format.
The sync coincidence signal is also used to generate the 7.7.4 CD-TEXT INTERFACE
PLL lock signal, which is active HIGH after 1 sync
coincidence is found, and reset LOW if during 61 R to W subcode data is captured and stored until a
consecutive frames no sync coincidence is found. The complete CD-text PACK is formed. The least significant
T
PLL lock signal can be accessed via the SDA or STATUS 16 bits of the PACK are used for CRC.
pins selected by decoder registers 2, 7, and new shadow
The behaviour of the CD-text interface is controlled by
register C, bank 3.
new shadow register 7 bank 2. The interface can either
Also incorporated in the demodulator is a Run Length 2 flag all data (i.e. - passed or failed CRC) or it can flag good
(RL2) correction circuit. Every symbol detected as RL2 data only.
7.6.2 EFM DEMODULATION

AF
will be pushed back to RL3. To do this, the phase error of
both edges of the RL2 symbol are compared and the
correction is executed at the side with the highest error
probability.
The 14-bit EFM data and subcode words are decoded

into 8-bit symbols.
7.7 Subcode data processing

The data ready flag is monitored via the CDT_RDY pin
and is active low.
When a PACK becomes available, the initial value of the
CDT_DATA pin indicates the CRC result (high = passed;
low = failed). The micro can fetch the data by applying a
clock signal (max. frequency = 5MHz) to the CDT_CLK
pin and reading the subsequent bitstream on
CDT_DATA.
The 128 data bits are streamed out LSB first. A complete
R
CD-text PACK consists of 4 header bytes, 12 data bytes,
7.7.1 Q-CHANNEL PROCESSING and 2 CRC bytes although the latter 2 bytes are dropped
The 96-bit Q-channel word is accumulated in an internal internally once the CRC calculation is complete. Please
buffer. The last 16 bits are used internally to perform a refer to the Red Book for further details relating to the
Cyclic Redundancy Check (CRC). If the data is good, the format of a CD-text PACK.
SUBQREADY-I signal will go LOW. SUBQREADY-I can The timing diagram for the CD text interface can be found
D
be read via the SDA or STATUS pins, selected via in Figure 10.
decoder registers 2, 7, and new shadow register C, bank
3. Good Q-channel data may be read from SDA.
7.7.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)

INTERFACES
Data from all the subcode channels (P-to-W) may be read

via the subcode interface, which conforms to
EIAJ CP-2401. The interface is enabled and configured
as either a 3 or 4-wire interface via decoder register F.
The subcode interface output formats are illustrated in
Fig.8, where the RCK signal is supplied by another device
such as a CD graphics decoder.
2002 Mar 26 14

SAA7824
handbook, full pagewidth SF0 SF1 SF2 SF3 SF97 SF0 SF1
SBSY
SFSY
RCK
P-W P-W P-W

SUB
EIAJ 4-wire subcode interface
SF0 SF1 SF2 SF3 SF97 SF0 SF1
SFSY
T
RCK
P-W P-W P-W

SUB
EIAJ 3-wire subcode interface
SFSY
RCK
SUB AF P Q R S T U
Fig.8 EIAJ subcode (CD graphics) interface format.

V W
MBG410
R
D
200/n µs 11.3/n 11.3/n µs min

min µs 90/n µs max
W96 1 Q R S T U V W 1 Q
MBG401
11.3/n
µs
n = disc speed.
Fig.9 Subcode format and timing on pin V4.
2002 Mar 26 15

SAA7824
134/n µs
CDT_RDY
CDT_CLK
CDT_DATA CRC flag D0 D1 D2 D3 D126 D127
~1/n ns
T
200 ns (min)
n = disc speed.
7.8 FIFO and error corrector AF

Fig.10 CD-text interface format and timing.
The SAA7824 has a ±8 frame FIFO. The error corrector is

a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols
are used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
7.8.1 FLAGS OUTPUT (CFLG)
The flags output pin CFLG shows the status of the error
corrector and interpolator and is updated every frame
(7.35 × n kHz). In the SAA7824 chip, 8 1-bit flags are
present on the CFLG pin as illustrated in Fig.11. This
signal shows the status of the error corrector and
R
up to four errors on the C2 level. interpolator.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot The first flag bit, F1, is the absolute time sync signal, the
ascertain if the symbols are definitely good. C1 generates FIFO-passed subcode sync and relates the position of the
output flags which are read after de-interleaving by C2, to subcode sync to the audio data (DAC output). This flag
help in the generation of C2 output flags. may also be used in a super FIFO or in the
D
synchronization of different players. The output flags can

The C2 output flags are used by the interpolator for
be made available at bit 4 of the EBU data format (LSB of
concealment of uncorrectable errors. They are also
the 24-bit data word), if selected by decoder register A.
output via the EBU signal (DOBM). The EF output will flag
bytes in error in both audio and CD-ROM modes.
handbook, full pagewidth 11.3/n

33.9/n µs µs 33.9/n µs
F8 F1 F2 F3 F4 F5 F6 F7 F8 F1
MBG425
n = disc speed.
Fig.11 Flag output timing diagram.
2002 Mar 26 16

SAA7824
Table 4 Output flags
F1 F2 F3 F4 F5 F6 F7 F8 DESCRIPTION
0 X X X X X X X no absolute time sync
1 X X X X X X X absolute time sync
X 0 0 X X X X X C1 frame contained no errors
X 0 1 X X X X X C1 frame contained 1 error
X 1 0 X X X X X C1 frame contained 2 errors
X 1 1 X X X X X C1 frame uncorrectable
X X X 0 0 X X 0 C2 frame contained no errors
X X X 0 0 X X 1 C2 frame contained 1 error
X X X 0 1 X X 0 C2 frame contained 2 errors
T
X X X 1 1 X X 1 C2 frame uncorrectable
X X X X X 0 0 X no interpolations
X X X X X 0 1 X at least one 1-sample interpolation
7.9
X
X
7.9.1
X
X
X
X
Audio functions
X
X
X
X
DE-EMPHASIS AND PHASE LINEARITY

AF
1
1
When pre-emphasis is detected in the Q-channel

0
1
subcode, the digital filter automatically includes a

de-emphasis filter section. When de-emphasis is not
required, a phase compensation filter section controls the
X
X
at least one hold and no interpolations
at least one hold and one 1-sample interpolation
Table 5 Filter specification
PASS BAND
0 to 9 kHz
19 to 20 kHz
−
−
STOP BAND
−
−
24 kHz
24 to 27 kHz
ATTENUATION
≤0.001 dB
≤0.03 dB
≥25 dB
≥38 dB
phase of the digital oversampling filter to ≤ ±1° within the
R
band 0 to 16 kHz. With de-emphasis the filter is not phase − 27 to 35 kHz ≥40 dB
linear. − 35 to 64 kHz ≥50 dB
If the de-emphasis signal is set to be available at V5, − 64 to 68 kHz ≥31 dB
selected via decoder register D, then the de-emphasis − 68 kHz ≥35 dB
filter is bypassed.
− 69 to 88 kHz ≥40 dB
D
7.9.2 DIGITAL OVERSAMPLING FILTER

7.9.3 CONCEALMENT
For optimizing performance with an external DAC, the
A 1-sample linear interpolator becomes active if a single
SAA7824 contains a 2 to 4 times oversampling IIR filter.
sample is flagged as erroneous but cannot be corrected.
The filter specification of the 4 times oversampling filter is
The erroneous sample is replaced by a level midway
given in Table 5.
between the preceding and following samples. Left and
These attenuations do not include the sample-and-hold at right channels have independent interpolators. If more
the external DAC output or the DAC post filter. When than one consecutive non-correctable sample is found,
using the oversampling filter, the output level is scaled the last good sample is held. A 1-sample linear
−0.5 dB down to avoid overflow on full-scale sine wave interpolation is then performed before the next good
inputs (0 to 20 kHz). sample (see Fig.12).
2002 Mar 26 17

SAA7824
In CD-ROM modes (i.e. the external DAC interface is 7.9.5 PEAK DETECTOR
selected to be in a CD-ROM format) concealment is not
The peak detector measures the highest audio level
executed.
(absolute value) on positive peaks for left and right
channels. The 8 most significant bits are output in the
7.9.4 MUTE, FULL-SCALE, ATTENUATION AND FADE
Q-channel data in place of the CRC bits. Bits 81 to 88
A digital level controller is present on the SAA7824 which contain the left peak value (bit 88 = MSB) and
performs the functions of soft mute, full-scale, attenuation bits 89 to 96 contain the right peak value (bit 96 = MSB).
and fade; these are selected via decoder register 0: The values are reset after reading Q-channel data via pin
• Mute: signal reduced to 0 in a maximum of 128 steps; SDA.
(3/n) ms
• Attenuation: signal scaled by −12 dB
• Full-scale: ramp signal back to 0 dB level; from mute
takes (3/n) ms
• Fade: activates a 128 stage counter which allows the
T
signal to be scaled up/down by 0.07 dB steps
– 128 = full-scale
– 120 = −0.5 dB (i.e. full-scale if oversampling filter
used)
– 32 = −12 dB
– 0 = mute.
AF
Interpolation Hold Interpolation
R
OK Error OK Error Error Error OK OK
D
MGA372
Fig.12 Concealment mechanism.
2002 Mar 26 18

SAA7824
7.10 Audio DAC interface

7.10.1 INTERNAL DYNAMIC ELEMENT MATCHING DIGITAL-TO-ANALOG CONVERTER (DAC)
The onboard audio DEM DAC operates at an oversampling rate of 96fs and is designed for operation with an audio input
at 1fs. The DAC is equipped with two pairs of stereo outputs for driving medium impedance line-outputs and for directly
driving low impedance headphones. A pair of analogue inputs are provided to enable external audio sources to make
use of the headphone output buffers.
Audio data from the decoder part of the SAA7824 can be routed as described in Sections 7.10.1.1 and 7.10.1.2.
Table 6 Shadow register
SHADEN SHADOW
ADDRESS DATA FUNCTION RESET
BITS REGISTER
01 7 0111 0000 Use external DAC or route audio data back reset
into onboard DAC (loopback mode)
T
(bank 1) control of
onboard DAC 0010 Route audio data directly into onboard DAC −
(non-loopback mode)
7.10.1.1 Use of internal DAC In this mode, a wide range of data formats to the external
AF
Setting shadow register 7 to 0010 will route audio data
from the decoder into the internal DAC. To enable the
on-board DAC, the DAC interface format (set by
register 3) must be set to 16-bit 1fs mode, either I2S or
EIAJ format. CD-ROM mode can also be used if
interpolation is not required. The serial data output pins
for interfacing with an external DAC (SCLK, WCLK,
DATA and EF) are set to high-impedance.
7.10.1.2 Loopback external data into onboard DAC

ESA IC can be programmed as shown in Table 7.
However, the serial input on the SAA7824 will always
expect the input data from the ESA IC to be 16-bit 1fs and
the same data format, either I2S-bus or EIAJ, as the serial
output format (set by decoder register 3).
R
The onboard DAC can also be set to accept serial data
inputs from an external source, e.g. an Electronic Shock
Absorption (ESA) IC. This is known as loopback mode
and is enabled by setting shadow register 7 to 0000. This
enables the serial data output pins (SCLK, WCLK, DATA
and EF) so that data can be routed from the SAA7824 to
D
an external ESA system (or external DAC).

The serial data from an external ESA IC can then also be
input to the onboard DAC on the SAA7824 by utilising the
serial data input interface (SCLI, SDI and WCLI).
2002 Mar 26 19

SAA7824
7.10.2 EXTERNAL DAC INTERFACE All formats are MSB first and 1fs is 44.1KHz. The polarity
of the WCLK and the data can be inverted; selectable by
Audio data from the SAA7824 can be sent to an external
decoder register 7. It should be noted that EF is only a
DAC, identical to the SAA732x series, in ‘loopback’ mode
defined output in CD-ROM and 1fs modes.
(i.e. shadow register 7 is set to 0000). The SAA7824 is
compatible with a wide range of external DACs. Eleven When using an external DAC (or when using the onboard
formats are supported and are given in Table 7. DAC in non-loopback mode), the serial data inputs to the
Figures 13 and 14 show the Philips I2S-bus and the EIAJ onboard DAC (SCLI, SDI and WCLI) should be tied to
data formats respectively. When the decoder is operated ground.
in lock-to-disc mode, the SCLK frequency is dependent
on the disc speed factor ‘d’.
Table 7 DAC interface formats
SAMPLE NUMBER OF
REGISTER 3 SCLK (MHz) FORMAT INTERPOLATION
T
FREQUENCY BITS
1010 fs 16 2.1168 × n CD-ROM (I2S-bus) no
1011 fs 16 2.1168 × n CD-ROM (EIAJ) no
1110 fs 16/18(1) 2.1168 × n Philips I2S-bus 16/18 bits(1) yes
2.1168 × n
Note
0010
0110
0000
0100
1100
0011
0111
1111
fs
fs
4fs
4fs
4fs
2fs
2fs
2fs
AF 16
18
16
18
18
16
18
18
2.1168 × n
8.4672 × n
8.4672 × n
8.4672 × n
4.2336 × n
4.2336 × n
4.2336 × n
EIAJ 16 bits
EIAJ 18 bits
EIAJ 16 bits
EIAJ 18 bits
Philips I2S-bus 18 bits
EIAJ 16 bits
EIAJ 18 bits
Philips I2S-bus 18 bits
yes
yes
yes
yes
yes
yes
yes
yes
R
1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated
then the first 18 bits contain data.
D
2002 Mar 26 20
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2002 Mar 26
Philips Semiconductors
SCLK
DATA 1 0 15 14 1 0 15 14
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)
T
WCLK
EF
(CD-ROM LSB error flag MSB error flag LSB error flag MSB error flag
AND Ifs MODES ONLY)
MBG424
AF
Fig.13 Philips I2S-bus data format (16-bit word length shown).
21
R
SCLK
DATA 0 17 0 17
LEFT CHANNEL DATA
D
WCLK
EF
Preliminary specification
(CD-ROM MSB error flag LSB error flag MSB error flag
AND Ifs MODES ONLY)
MBG423
SAA7824
Fig.14 EIAJ data format (18-bit word length shown).

SAA7824
7.11 EBU interface 7.11.1 FORMAT

The bi-phase mark digital output signal at pin DOBM is in The digital audio output consists of 32-bit words
accordance with the format defined by the IEC 958 (‘subframes’) transmitted in bi-phase mark code (two
specification. Three different modes can be selected via transitions for a logic 1 and one transition for a logic 0).
decoder register A: Words are transmitted in blocks of 384. The EBU frame
• DOBM pin held LOW format is given in Table 8.
• Data taken before concealment, mute and fade (must

always be used for CD-ROM modes)
• Data taken after concealment, mute and fade.
Table 8 EBU frame format
T
FUNCTION BITS DESCRIPTION
Sync 0 to 3 −
Auxiliary 4 to 7 not used; normally zero
Error flags 4 CFLG error and interpolation flags when selected by register A
Audio sample 8 to 27 first 4 bits not used (always zero); 2’s complement; LSB = bit 12, MSB = bit 27
Validity flag
User data
Channel status
Parity bit
Sync:
28
29
30
31 AF
valid = logic 0
used for subcode data (Q-to-W)
control bits and category code
even parity for bits 4 to 30
The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.
Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample
(no block start) and sync W: word contains right sample.
Audio sample: Left and right samples are transmitted alternately.
R
Validity flag: Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This
flag remains the same even if data is taken after concealment.
User data: Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is
asynchronous with the block rate.
Channel status: The channel status bit is the same for left and right words. Therefore a block of 384 words contains
D
192 channel status bits. The category code is always CD. The bit assignment is given in Table 9.
Table 9 Bit assignment
FUNCTION BITS DESCRIPTION

Control 0 to 3 copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis
Reserved mode 4 to 7 always zero
Category code 8 to 15 CD: bit 8 = logic 1, all other bits = logic 0
Clock accuracy 28 to 29 set by register A; 10 = level I; 00 = level II; 01 = level III
Remaining 6 to 27 and 30 to 191 always zero
2002 Mar 26 22

SAA7824
7.12 KILL features 7.13 Audio features off

7.12.1 THE KILL CIRCUIT The audio features can be turned off (selected by decoder
register E) which affects the following functions:
The KILL circuit detects digital silence by testing for an
all-zero or all-ones data word in the left and right channel. • Digital filter, fade, peak detector, internal KILL circuit
This occurs in two places; prior to the digital filter (internal (although RKILL & LKILL outputs still active) are
KILL), and in the digital DAC (loopback/external KILL). disabled
Programming bit 3 of new shadow register A bank 2 • V5 (if selected to be the de-emphasis flag output) and
determines whether internal or external data is used. The the EBU outputs become undefined.
output is switched to active high when silence has been
detected for at least 270 ms, or if mute is active, or in It should be noted that the EBU output should be set low
CD-ROM mode. Two KILL modes are available which can prior to switching the audio features off and after
be selected by decoder register C: switching the audio features back on, a full-scale
command should be given.
1. Mono KILL: LKILL & RKILL both active high when
silence detected on left & right channels 7.14 The versatile pins interface
T
simultaneously.
The SAA7824 has five pins that can be reconfigured for
2. Stereo KILL: LKILL & RKILL active high
different applications.
independently of each other when silence detected
on either channel respectively. The functions of these versatile pins are identical to the
SAA732x series and can be programmed by decoder
7.12.2 SILENCE INJECTION
AF
The silence inject function monitors the left and right KILL
signals and forces the analogue DAC into silence when
KILL is asserted. This improves the internal SNR by
preventing any spurious noise from reaching the DAC.
The silence inject function can be enabled/disabled by
programming bit 2 of new shadow register A bank 2.
PIN REGISTER REGISTER

registers C, D, and shadow register 3 bank 1 as shown
below in Table 10.
Table 10 Pin applications
PIN NAME TYPE FUNCTION

R
NUMBER ADDRESS DATA
V1 71 input 1100 XXX1 external off-track signal input
− XXX0 internal off-track signal used input may be read
via decoder status bit; selected via register 2
V2 72 input − − input may be read via decoder status bit;
selected via register 2
D
V3 73 output 1100 00XX output = 0

− 01XX output = 1
V4 74 output 1101 0000 4-line motor drive (using V4 and V5)
− XX01 Q-to-W subcode output
− XX10 output = 0
− XX11 output = 1
V5 75 output 1101 01XX de-emphasis output (active HIGH)
− 10XX output = 0
− 11XX output = 1
2002 Mar 26 23

SAA7824
7.15 Spindle motor control 7.15.1.1 Pulse density output mode

7.15.1 MOTOR OUTPUT MODES In the pulse density mode the motor output pin (MOTO1)
is the pulse density modulated motor output signal.
The spindle motor speed is controlled by a fully integrated
A 50% duty factor corresponds with the motor not
digital servo. Address information from the internal ±8
actuated, higher duty factors mean acceleration, lower
frame FIFO and disc speed information are used to
mean braking. In this mode, the MOTO2 signal is the
calculate the motor control output signals. Several output
inverse of the MOTO1 signal. Both signals change state
modes, selected by decoder register 6, are supported:
only on the edges of a (1 × n) MHz internal clock signal.
• Pulse density, 2-line (true complement output),
(1 × n) MHz sample frequency 7.15.1.2 PWM output mode (2-line)
• PWM output, 2-line, (22.05 × n) kHz modulation
In the PWM mode the motor acceleration signal is put in
frequency
pulse-width modulation form on the MOTO1 output.
• PWM output, 4-line, (22.05 × n) kHz modulation The motor braking signal is pulse-width modulated on the
frequency MOTO2 output. The timing is illustrated in Fig.15. A
T
• CDV motor mode. typical application diagram is illustrated in Fig.16.
t rep = 45 µs t dead 240 ns
MOTO1
MOTO2
AF
Accelerate
Fig.15 2-line PWM mode timing.
Brake MGA366
R
+
D
10 Ω 100 nF
MOTO1 MOTO2
VSS MGA365 - 2
Fig.16 Motor 2-line PWM mode application diagram.
2002 Mar 26 24

SAA7824
7.15.1.3 PWM output mode (4-line)

Using two extra outputs from the versatile pins interface, it is possible to use the SAA7824 with a 4-input motor bridge.
The timing is illustrated in Fig.17. A typical application diagram is illustrated in Fig.18.
t rep = 45 µs t dead 240 ns
MOTO1
MOTO2
V4
T
V5
t ovl = 240 ns MGA367 - 1
Accelerate Brake
AF Fig.17 4-line PWM mode timing.

R
+
V4 V5
D
10 Ω 100 nF
MOTO1 MOTO2
VSS MGA364 - 2
Fig.18 Motor 4-line PWM mode application diagram.
2002 Mar 26 25

SAA7824
7.15.1.4 CDV/CAV output mode percentage of the maximum possible voltage, via
register 6, to limit current drain during start and stop.
In the CDV motor mode, the FIFO position will be put in
pulse-width modulated form on the MOTO1 pin [carrier The following power limits are possible:
frequency (300 × d) Hz], where ‘d’ is the disc speed • 100% (no power limit), 75%, 50%, or 37% of maximum.
factor. The PLL frequency signal will be put in
pulse-density modulated form (carrier frequency 7.15.3 LOOP CHARACTERISTICS
4.23 × n MHz) on the MOTO2 pin. The integrated motor
servo is disabled in this mode. The gain and crossover frequencies of the motor control
loop can be programmed via decoder registers 4 and 5.
The PWM signal on MOTO1 corresponds to a total The following parameter values are possible:
memory space of 20 frames, therefore the nominal FIFO
position (half full) will result in a PWM output of 60%. • Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32
• Crossover frequency f4: 0.5 × n Hz, 0.7 × n Hz,
In the lock-to-disc (CAV) mode the CDV motor mode is
1.4 × n Hz and 2.8 × n Hz
the only mode that can be used to control the motor.
• Crossover frequency f3: 0.85 × n Hz, 1.71 × n Hz and
T
7.15.2 SPINDLE MOTOR OPERATING MODES 3.42 × n Hz.
The operating modes of the motor servo is controlled by It should be noted that the crossover frequencies f3 and f4
decoder register 1 (see Table 11). are scaled with the overspeed factor ‘n’ whereas the
gains are not.
In the SAA7824 decoder there is an anti-windup mode for
7.15.2.1 Power limit AF

the motor servo, selected via decoder register 1. When
the anti-windup mode is activated the motor servo
integrator will hold if the motor output saturates.
In start mode 1, start mode 2, stop mode 1 and stop

mode 2, a fixed positive or negative voltage is applied to
the motor. This voltage can be programmed as a
Table 11 Operating modes

7.15.4 FIFO OVERFLOW
If FIFO overflow occurs during Play mode (e.g.: as a
result of motor rotational shock), the FIFO will be
automatically reset to 50% and the audio interpolator will
conceal as much as possible to minimize the effect of
data loss.
R
MODE DESCRIPTION
Start mode 1 The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved
and the PLL is reset. No disc speed information is available for the microcontroller.
Start mode 2 The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the
disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status
D
signals selectable via register 2 are valid.

Jump mode Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is
possible to read the subcode. It should be noted that in the CD-ROM modes the data, on EBU and
the I2S-bus is not muted.
Jump mode 1 Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large
change in disc speed.
Play mode FIFO released after resetting to 50%. Audio mute released.
Stop mode 1 Disc is braked by applying a negative voltage to the motor. No decisions are involved.
Stop mode 2 The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc
reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal
speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode.
Off mode Motor not steered.
2002 Mar 26 26

SAA7824
MGA362 - 2
G
f4 f3 BW f
T
Fig.19 Motor servo mode diagram.
AF
R
D
2002 Mar 26 27

SAA7824
7.16 Servo part The low frequency content of the six (five if single
Foucault) photo diode inputs are converted to digital
7.16.1 DIODE SIGNAL PROCESSING
Pulse-Density-Modulated bitstreams by six Sigma-delta
The photo detector in conventional two-stage three-beam ADCs. These support a range of OPUs interfacing to
Compact Disc systems normally contains six discrete Voltage mode mechanisms and by having sixteen
diodes. Four of these diodes (three for single foucault selectable gain ranges in two sets, one set for D1-D4 and
systems) carry the Central Aperture signal (CA) while the the other for R1 and R2.
other two diodes (satellite diodes) carry the radial tracking
information. The CA signals are summed into an
HF signal for the decoder function and are also
differenced (after analogue to digital conversion) to
produce the low frequency focus control signals.
T
Table 12 Shadow register settings to control diode voltage ranges
SHADEN SHADOW
ADDRESS DATA VOLTAGE INITIAL
BITS REGISTER
01 A 1010 0000 20 mV −
signal magnitude −
(bank 1)
control for diodes
D1 to D4
(LF only)
AF 0001
0010
0011
0100
0101
0110
0111
1000
1001
25 mV
30 mV
40 mV
60 mV
75 mV
100 mV
120 mV
150 mV
200 mV
−
−
−
−
−
−
−
−
R
1010 270 mV −
1011 350 mV −
1100 450 mV −
1101 600 mV −
1110 720 mV −
D
1111 960 mV reset
2002 Mar 26 28

SAA7824
SHADEN SHADOW
ADDRESS DATA VOLTAGE INITIAL
BITS REGISTER
01 C 1100 0000 20 mV −
signal magnitude 0001 25 mV −
(bank 1)
control for diodes
0010 30 mV −
R1 and R2
0011 40 mV −
(LF only)
0100 60 mV −
0101 75 mV −
0110 100 mV −
0111 120 mV −
1000 150 mV −
1001 200 mV −
T
1010 270 mV −
1011 350 mV −
1100 450 mV −
1101 600 mV −
−
7.16.2 SIGNAL CONDITIONING

The digital codes retrieved from the ADCs are applied to
logic circuitry to obtain the various control signals.
The signals from the central aperture diodes are
processed to obtain a normalised focus error signal.
AF 1110
1111
720 mV
960 mV reset
The radial or tracking error signal is generated by the

satellite detector signals R1 and R2. The radial error
signal can be formulated as follows:
REs = (R1 − R2) × re_gain + (R1 + R2) × re_offset
where the index ‘s’ indicates the automatic scaling
R
D1 – D2 D3 – D4 operation which is performed on the radial error signal.
FE n = --------------------- – --------------------- This scaling is necessary to avoid non-optimum dynamic
D1 + D2 D3 + D4
range usage in the digital representation and reduces the
where the detector set-up is assumed to be as shown in radial bandwidth spread. Furthermore, the radial error
Fig.20. signal will be made free from offset during start-up of the
In the event of single Foucault focusing method, the disc.
D
signal conditioning can be switched under software The four signals from the central aperture detectors,
control such that the signal processing is as follows: together with the satellite detector signals generate a
Track Position Signal (TPI) which can be formulated as
D1 – D2
FE n = 2 × --------------------- follows:
D1 + D2
TPI = sign [(D1 + D2 + D3 + D4) − (R1 + R2) × sum_gai
The error signal, FEn, is further processed by a
n]
Proportional Integral and Differential (PID) filter section.
where the weighting factor sum_gain is generated
A Focus OK (FOK) flag is generated by means of the
internally by the SAA7824 during initialization.
central aperture signal and an adjustable reference level.
This signal is used to provide extra protection for the
Track-Loss (TL) generation, the focus start-up procedure
and the dropout detection.
2002 Mar 26 29

SAA7824
SATELLITE SATELLITE SATELLITE

DIODE R1 DIODE R1 DIODE R1
D1
D1 D2 D1
D2
D3
D3
D2 D4 D3
D4
T
SATELLITE SATELLITE SATELLITE
DIODE R2 DIODE R2 DIODE R2
single Foucault astigmatic focus double Foucault
MBG422
7.16.3
7.16.3.1
FOCUS SERVO SYSTEM
Focus start-up
AFFig.20 Detector arrangement.
differentiating (foc_pole_lead, part of foc_parm1) action

of the PID and a digital low-pass filter (foc_pole_noise,
part of foc_parm2) following the PID. The fifth coefficient
R
Five initially loaded coefficients influence the start-up foc_gain influences the loop gain.
behaviour of the focus controller. The automatically
generated triangular voltage can be influenced by 7.16.3.3 Dropout detection
3 parameters; for height (ramp_height) and DC offset
This detector can be influenced by one parameter
(ramp_offset) of the triangle and its steepness
(CA_drop). The FOK signal will become false and the
(ramp_incr).
integrator of the PID will hold if the CA signal drops below
D
For protection against false focus point detections two this programmable absolute CA level. When the FOK
parameters are available which are an absolute level on signal becomes false it is assumed, initially, to be caused
the CA signal (CA_start) and a level on the FEn signal by a black dot.
(FE_start). When this CA level is reached the FOK signal
becomes true. 7.16.3.4 Focus loss detection and fast restart
If the FOK signal is true and the level on the FEn signal is Whenever FOK is false for longer than approximately
reached, the focus PID is enabled to switch-on when the 3 ms, it is assumed that the focus point is lost. A fast
next zero crossing is detected in the FEn signal. restart procedure is initiated which is capable of restarting
the focus loop within 200 to 300 ms depending on the
7.16.3.2 Focus position control loop programmed coefficients of the microcontroller.
The focus control loop contains a digital PID controller
7.16.3.5 Focus loop gain switching
which has 5 parameters that are available to the user.
These coefficients influence the integrating (foc_int), The gain of the focus control loop (foc_gain) can be
proportional (foc_lead_length, part of foc_parm3) and multiplied by a factor of 2 or divided by a factor of 2 during
2002 Mar 26 30

SAA7824
normal operation. The integrator value of the PID is controlled, or provided with step pulses to reduce power
corrected accordingly. The differentiating (foc_pole_lead) consumption using the filtered value of the radial PID
action of the PID can be switched at the same time as the output. Alternatively, the microcontroller can read the
gain switching is performed. average voltage on the radial actuator and provide the
sledge with step pulses to reduce power consumption.
7.16.3.6 Focus automatic gain control loop Filter coefficients of the continuous sledge control can be
preset by the user.
The loop gain of the focus control loop can be corrected
automatically to eliminate tolerances in the focus loop.
7.16.4.4 Access
This gain control injects a signal into the loop which is used
to correct the loop gain. Since this decreases the optimum The access procedure is divided into two different modes
performance, the gain control should only be activated for (see Table 13), depending on the requested jump size.
a short time (for example, when starting a new disc).
Table 13 Access modes
7.16.4 RADIAL SERVO SYSTEM
ACCESS ACCESS
JUMP SIZE(1)
T
7.16.4.1 Level initialization TYPE SPEED
During start-up an automatic adjustment procedure is Actuator jump 1 - brake_distance decreasing
activated to set the values of the radial error gain (re_gain), velocity
offset (re_offset) and satellite sum gain (sum_gain) for TPI Sledge jump brake_distance - 32768 maximum
level generation. The initialization procedure runs in a power to
start-up time period:
AF
radial open loop situation and is ≤300 ms. This start-up
time period may coincide with the last part of the motor
• Automatic gain adjustment: as a result of this

initialization the amplitude of the RE signal is adjusted to
within ±10% around the nominal RE amplitude
• Offset adjustment: the additional offset in RE due to the
limited accuracy of the start-up procedure is less than
±50 nm
• TPI level generation: the accuracy of the initialization
Note
1. Microcontroller presettable.
sledge(1)
The access procedure makes use of a track counting

mechanism, a velocity signal based on a fixed number of
tracks passed within a fixed time interval, a velocity set
point calculated from the number of tracks to go and a user
programmable parameter indicating the maximum sledge
R
procedure is such that the duty factor range of TPI performance.
becomes 0.4 < duty factor < 0.6 (default duty If the number of tracks remaining is greater than the
factor = TPI HIGH/TPI period). brake_distance then the sledge jump mode should be
activated or, the actuator jump should be performed.
7.16.4.2 Sledge control The requested jump size together with the required sledge
The microcontroller can move the sledge in both directions breaking distance at maximum access speed defines the
D
via the steer sledge command. brake_distance value.

During the actuator jump mode, velocity control with a
7.16.4.3 Tracking control PI controller is used for the actuator. The sledge is then
The actuator is controlled using a PID loop filter with user continuously controlled using the filtered value of the radial
defined coefficients and gain. For stable operation PID output. All filter parameters (for actuator and sledge)
between the tracks, the S-curve is extended over 0.75 of are user programmable.
the track. On request from the microcontroller, S-curve In the sledge jump mode maximum power (user
extension over 2.25 tracks is used, automatically changing programmable) is applied to the sledge in the correct
to access control when exceeding those 2.25 tracks. direction while the actuator becomes idle (the contents of
Both modes of S-curve extension make use of a the actuator integrator leaks to zero just after the sledge
track-count mechanism. In this mode, track counting jump mode is initiated). The actuator can be electronically
results in an ‘automatic return-to-zero track’, to avoid damped during sledge jump. The gain of the damping loop
major disturbances in the audio output and providing is controlled via the hold_mult parameter.
improved shock resistance. The sledge is continuously
2002 Mar 26 31

SAA7824
The fast track jumping circuitry can be enabled/disabled 1. Protected state: used in normal play situations. A
via the xtra_preset parameter. good protection against false detection caused by
disc defects is important in this state.
7.16.4.5 Radial automatic gain control loop 2. Slow counting state: used in low velocity track jump
The loop gain of the radial control loop can be corrected situations. In this state a fast response is important
automatically to eliminate tolerances in the radial loop. rather than the protection against disc defects (if the
This gain control injects a signal into the loop which is phase relationship between TL and RP of 1⁄2π radians
used to correct the loop gain. Since this decreases the is affected too much, the direction cannot then be
optimum performance, the gain control should only be determined accurately).
activated for a short time (for example, when starting a 3. Fast counting state: used in high velocity track jump
new disc). situations. Highest obtainable velocity is the most
This gain control differs from the level initialization. The important feature in this state.
level initialization should be performed first.
The disadvantage of using the level initialization without 7.16.6 DEFECT DETECTION
T
the gain control is that only tolerances from the front-end A defect detection circuit is incorporated into the
are reduced. SAA7824. If a defect is detected, the radial and focus
error signals may be zeroed, resulting in better playability.
7.16.5 OFF-TRACK COUNTING The defect detector can be switched off, applied only to
focus control or applied to both focus and radial controls
The Track Position Signal (TPI) is a flag which is used to
under software control (part of foc_parm1).
AF
indicate whether the radial spot is positioned on the track,
with a margin of ±1⁄4 of the track-pitch. In combination with
the Radial Polarity flag (RP) the relative spot position over
the tracks can be determined.
These signals can have uncertainties caused by:
• Disc defects such as scratches and fingerprints
• The HF information on the disc, which is considered as
noise by the detector signals.
In order to determine the spot position with sufficient
The defect detector (see Fig.21) has programmable set
points selectable by the parameter defect_parm.
7.16.7 OFF-TRACK DETECTION

During active radial tracking, off-track detection has been
realised by continuously monitoring the off-track counter
value. The off-track flag becomes valid whenever the
off-track counter value is not equal to zero. Depending on
the type of extended S-curve, the off-track counter is reset
R
accuracy, extra conditions are necessary to generate a after 0.75 extend or at the original track in the 2.25 track
Track Loss signal (TL) and an off-track counter value. extend mode.
These extra conditions influence the maximum speed and
this implies that, internally, one of the following three
counting states is selected:
D

+ DECIMATION FAST SLOW DEFECT PROGRAMMABLE defect
sat1
FILTER FILTER FILTER GENERATION HOLD-OFF output
−
sat2 MBG421
Fig.21 Block diagram of defect detector.
2002 Mar 26 32

SAA7824
7.16.8 HIGH LEVEL FEATURES 7.16.8.3 Automatic error handling

7.16.8.1 Interrupt mechanism and STATUS pin Three Watchdogs are present:
The STATUS pin is an output which can be configured by • Focus: detects focus dropout of longer than 3 ms, sets
decoder register 7 and new shadow register C bank 3 for focus lost interrupt, switches off radial and sledge
one of three different modes of operation. These are: servos, disables drive to disc motor
• Output the interrupt signal generated by the servo part • Radial play: started when radial servo is in on-track
(Note: Selection of this mode will override all other mode and a first subcode frame is found; detects when
modes). maximum time between two subcode frames exceeds
the time set by playwatchtime parameter; then sets
• Output the decoder status bit (active low) selected by
radial error interrupt, switches radial and sledge servos
decoder register 2 (only available in 4-wire bus mode).
off, puts disc motor in jump mode
• Output dc offset information (Note: This mode is used in
• Radial jump: active when radial servo is in long jump or
conjunction with the decoder status mode - see Section
short jump modes; detects when the off-track counter
7.5).
value decreases by less than 4 tracks between two
T
Eight signals from the interrupt status register are readings (time interval set by jumpwatchtime
selectable from the servo part via the interrupt_mask parameter); then sets radial jump error, switches radial
parameter. The interrupt is reset by sending the read and sledge servos off to cancel jump.
high-level status command. The 8 signals are as follows:
The focus Watchdog is always active, the radial
• Focus lost: dropout of longer than 3 ms Watchdogs are selectable via the radcontrol parameter.
• Subcode ready
• Subcode absolute seconds changed
later than previous subcode time

AF
• Subcode discontinuity detected: new subcode time
before previous subcode time, or more than 10 frames
• Radial error: during radial on-track, no new subcode

frame occurs within time defined by the ‘playwatchtime’
parameter; during radial jump, less than 4 tracks have
been crossed during time defined by the
7.16.8.4 Automatic sequencers and timer interrupts
Two automatic sequencers are implemented (and must be
initialized after power-on):
• Autostart sequencer: controls the start-up of focus,
radial and motor
• Autostop sequencer: brakes the disc and shuts down
servos.
When the automatic sequencers are not used it is possible
‘jumpwatchtime’ parameter
R
to generate timer interrupts, defined by the
• Autosequencer state change time_parameter coefficient.
• Autosequencer error
• Subcode interface blocked: the internal decoder 7.16.8.5 High-level status
interface is being used. The read high-level status command can be used to obtain
the interrupt, decoder, autosequencer status registers and
D
It should be noted that if the STATUS pin is configured to

output decoder status information (decoder register 7 = the motor start time. Use of the read high-level status
XX10 and new shadow register C bank3 = X00X) and command clears the interrupt status register, and
either the microcontroller writes a different value to re-enables the subcode read via a servo command.
decoder register 2 or the decoder interface is enabled then
the STATUS output will change. 7.16.9 DRIVER INTERFACE
The control signals (pins RA, FO and SL) for the
7.16.8.2 Decoder interface mechanism actuators are pulse density modulated.
The decoder interface allows decoder and shadow The modulating frequency can be set to either 1.0584 or
registers to be programmed and subcode Q-channel data 2.1168 MHz; controlled via the xtra_preset parameter. An
to be read via servo commands. The interface is analog representation of the output signals can be
enabled/disabled by the preset latch command (and the achieved by connecting a 1st-order low-pass filter to the
xtra_preset parameter). outputs.
During reset (i.e. RESET pin is held low) the RA, FO,
and SL pins are high-impedance. At all other times, when
2002 Mar 26 33

SAA7824
the laser is switched off, the RA and FO pins output a • 4-wire bus mode: where:
2MHz 50% duty cycle signal. – SCL = serial clock
– SDA = serial data
7.16.10 LASER INTERFACE
– RAB = R/W control and data strobe (active HIGH)
The laser diode pre-amp function is built onto the for writing to decoder registers 0 to F, reading status
SAA7824 and is illustrated in Fig.22. The current can be bit selected via decoder register 2 and reading
regulated, up to 120mA, in four steps ranging from 58% Q-channel subcode
up to full power. New shadow register A bank 2 & new
shadow register 3 bank 3 are used to select the step – SILD = R/W control and data strobe (active LOW)
values. for servo commands.
• I2C-bus mode: I2C-bus protocol where the SAA7824
The voltage derived from the monitor diode is maintained
behaves as slave device, activated by setting
at a steady state by the laser drive circuitry, regulating the
RAB = HIGH and SILD = LOW where:
current through the laser diode. The type of monitor diode
being used (150mV or 180mV) must be selected by new – I2C-bus slave address (write mode) = 30H
T
shadow register 7 bank 2 (reset state = 150mV). – I2C-bus slave address (read mode) = 31H
The laser can be switched on or off by the xtra_preset – Maximum data transfer rate = 400 kbits/s.
parameter; it is automatically driven if the focus control
It should be noted that when using I2C-bus mode, only
loop is active.
servo commands can be used. Therefore, writing to
decoder registers 0 to F, reading decoder status and
7.17 Microcontroller interface
AF
Communication on the microcontroller interface can be
set-up in two different modes:
Floating
reference
vdda
reading Q-channel subcode data must be performed by
servo commands.
Laser Power Control (Bank 2 Reg A & Bank 3 Reg 3)

R
Error amplifier Power
amplifier LPOWER
mech_sel
+
gm + gm
D
-
pwd OR
LASER off
VSENSE MONITOR EXTFILTER LASER
47nF Laser
Monitor diode
diode
Fig.22 Simplified block diagram of laser driver
2002 Mar 26 34

SAA7824
7.17.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MOTOR-OV: HIGH if the motor servo output stage
MODE) saturates
7.17.1.1 Writing data to registers 0 to F The status read protocol is shown in Fig.25. It should be
noted that SILD must be held HIGH.
The sixteen 4-bit programmable configuration registers,
0 to F (see Table 15), can be written to via the
7.17.1.5 Reading Q-channel subcode
microcontroller interface using the protocol shown in
Fig.23. It should be noted that SILD must be held HIGH; To read the Q-channel subcode direct in the 4-wire bus
A3 to A0 identifies the register number and D3 to D0 is mode, the SUBQREADY-I signal should be selected as
the data. The data is latched into the register on the status signal. The subcode read protocol is illustrated in
LOW-to-HIGH transition of RAB. Fig.26.
It should be noted that SILD must be held HIGH; after
7.17.1.2 Writing repeated data to registers 0 to F
subcode read starts, the microcontroller may take as long
The same data can be repeated several times (e.g. for a as it wants to terminate the read operation. When enough
fade function) by applying extra RAB pulses as shown in subcode has been read (1 to 96 bits), terminate reading
T
Fig.24. It should be noted that SCL must stay HIGH by pulling RAB LOW.
between RAB pulses.
Alternatively, the Q-channel subcode can be read using a
servo command as follows:
7.17.1.3 Multiple-writes to the new shadow registers
• Use the read high-level status command to monitor the
Some of the new shadow registers (see Section 17) are a
AF
multiple of four bits in length and require a number of write
operations to fill them up. They must be completely filled
before writing to another register, otherwise unpredictable
behaviour may result.
The protocol for writing to these registers is exactly the
same as the decoder registers (see Figure 23). The write
command must be executed multiple times with the same
address content. The first four bits of data in a sequence
of write commands represent the most significant nibble
of the register, while the last four represent the least
subcode ready signal
• Send the read subcode command and read the
required number of bytes (up to 12)
• Send the read high-level status command; to re-enable
the decoder interface.
7.17.1.6 Behaviour of the SUBQREADY-I signal

When the CRC of the Q-channel word is good, and no
subcode is being read, the SUBQREADY-I status signal
will react as shown in Fig.27. When the CRC is good and
R
significant. The data content can change from one write to the subcode is being read, the timing in Fig.28 applies.
the next without consequence. If t1 (SUBQREADY-I status LOW to end of subcode read)
is below 2.6/n ms, then t2 = 13.1/n ms (i.e. the
7.17.1.4 Reading decoder status information on SDA microcontroller can read all subcode frames if it
There are several internal status signals, selected via completes the read operation within 2.6/n ms after the
register 2, which can be made available on the SDA line: subcode is ready). If these criteria are not met, it is only
D
possible to guarantee that t3 will be below 26.2/n ms

SUBQREADY-I: LOW if new subcode word is ready in
(approximately).
Q-channel register
MOTSTART1: HIGH if motor is turning at 75% or more If subcode frames with failed CRCs are present, the
of nominal speed t2 and t3 times will be increased by 13.1/n ms for each
defective subcode frame.
MOTSTART2: HIGH if motor is turning at 50% or more
of nominal speed It should be noted that in the lock-to-disc mode ‘n’ is
MOTSTOP: HIGH if motor is turning at 12% or less of replaced by ‘d’, which is the disc speed factor.
nominal speed; can be set to indicate 6% or less
(instead of 12% or less) via register E 7.17.1.7 Write servo commands
PLL lock: HIGH if sync coincidence signals are found A write data command is used to transfer data (a number
of bytes) from the microcontroller, using the protocol
V1: follows input on pin V1
shown in Fig.29. The first of these bytes is the command
V2: follows input on pin V2
2002 Mar 26 35

SAA7824
byte and the following are data bytes; the number It should be noted that more than one command can be
(between 1 and 7) depends on the command byte. sent in one write sequence.
It should be noted that RAB must be held LOW; the The sequence for a read data command (that reads
command or data is interpreted by the SAA7824 after the 2 data bytes) is as follows:
HIGH-to-LOW transition of SILD; there must be a 1. Send START condition
minimum time of 70 µs between SILD pulses.
2. Send address 30H (write)
7.17.1.8 Writing repeated data in servo commands 3. Write command byte
The same data byte can be repeated by applying extra 4. Send STOP condition
SILD pulses as illustrated in Fig.30. SCL must be HIGH 5. Send START condition
between the SILD pulses. 6. Send address 31H (read)
7.17.1.9 Read servo commands 7. Read data byte 1

8. Read data byte 2
A read data command is used to transfer data (status
T
information) to the microcontroller, using the protocol 9. Send STOP condition.
shown in Fig.31. The first byte written determines the type It should be noted that the timing constraints specified for
of command. After this byte a variable number of bytes the read and write servo commands must still be adhered
can be read. It should be noted that RAB must be held to.
LOW; after the end of the command byte (LOW-to-HIGH
7.17.2
AF
transition on SILD) there must be a delay of 70 µs before
reading data is started (i.e. the next HIGH-to-LOW
transition on SILD); there must be a minimum time of
70 µs between SILD pulses.
MICROCONTROLLER INTERFACE (I2C-BUS MODE)

Bytes are transferred over the interface in groups (i.e.
servo commands) of which there are two types: write data
commands and read data commands.
The sequence for a write data command (that requires
R
3 data bytes) is as follows:
1. Send START condition
2. Send address 30H (write)
3. Write command byte
4. Write data byte 1
D

7. Send STOP condition.
2002 Mar 26 36

SAA7824
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller) A3 A2 A1 A0 D3 D2 D1 D0
SDA
(SAA782X) high-impedance
T
GSA097
AF
Fig.23 Microcontroller write protocol for registers 0 to F.
R
RAB
(microcontroller)
SCL
(microcontroller)
D
SDA
(microcontroller) A3 A2 A1 A0 D3 D2 D1 D0
SDA
(SAA782X) high-impedance
GSA098
Fig.24 Microcontroller write protocol for registers 0 to F (repeat mode).
2002 Mar 26 37

SAA7824
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller) high-impedance
SDA
(SAA782X) STATUS
GSA099
T
AF
Fig.25 Microcontroller read protocol for decoder status on SDA.
R
RAB
(microcontroller)
SCL
(microcontroller)
D
CRC
SDA OK
(SAA782X)
Q1 Q2 Q3 Qn – 2 Qn – 1 Qn
STATUS GSA100
Fig.26 Microcontroller protocol for reading Q-channel subcode.
2002 Mar 26 38

SAA7824
RAB
(microcontroller)
SCL
(microcontroller)
SDA high-impedance
CRC OK CRC OK
(SAA782X)
GSA101
10.8/n ms 15.4/n ms
2.3/n
ms
T
READ start allowed
AF
Fig.27 SUBQREADY-I status timing when no subcode is read.
R
t2
t1 t3
RAB
(microcontroller)
D
SCL
(microcontroller)
SDA Q1 Q2 Q3 Qn
(SAA782X)
GSA102
Fig.28 SUBQREADY-I status timing when subcode is read.
2002 Mar 26 39

SAA7824
SILD
(microcontroller)
SCL
(microcontroller)
SDA D7 D6 D5 D4 D3 D2 D1 D0
(microcontroller)
command or data byte
SDA
(SAA782X)
high-impedance
microcontroller write (one byte: command or data)
SILD
(microcontroller)
T
SDA
COMMAND DATA1 DATA2 DATA3
(microcontroller)
GSA103
microcontroller write (full command)
AF
Fig.29 Microcontroller protocol for write servo commands.
R
SILD
D
(microcontroller)
SDA
COMMAND DATA1
(microcontroller)
MBG413
microcontroller write (full command)
Fig.30 Microcontroller protocol for repeated data in write servo commands.
2002 Mar 26 40

SAA7824
SILD
(microcontroller)
SCL
(microcontroller)
SDA (SAA782X) D7 D6 D5 D4 D3 D2 D1 D0
data byte
microcontroller read (one data byte)
SILD
(microcontroller)
SDA (SAA782X) DATA1 DATA2 DATA3
SDA
(microcontroller) COMMAND
T
GSA104
microcontroller read (full command)
Fig.31 Microcontroller protocol for read servo commands.
7.17.3
AF
DECODER REGISTERS AND SHADOW REGISTERS
To maintain compatibility with the SAA732x series,
decoder registers 0 to F and the shadow registers are
largely unchanged. However, to control the extra
functionality of SAA7824, the shadow registers have
been extended to include new shadow registers.
All shadow registers are accessed by using the two LSBs
(bits 0 & 1) of decoder register F. These bits are called
SHADEN1 and SHADEN2 respectively. These bits are
addresses are decoded by the main decoder registers
again.
Access to decoder register F is always enabled so that
SHADEN1 and SHADEN2 can be set or reset as
required.
The SHADEN bits and subsequent shadow registers are
programmed identically to the main decoder registers,
i.e. they can be directly programmed when using the
SAA7824 in 4-wire mode or programmed via the servo
decoded according to Table 14. interface when using 3-wire or I2C-bus modes. The main
R
decoder registers are given in Table 15 and the shadow
This two bit encoding allows the use of three shadow
registers, in Table 17. Details of the new shadow registers
register banks; bank 1 (SAA732X shadow registers), and
can be found in Tables18-21.
banks 2 & 3 (new shadow registers). Only the four
addresses 3, 7, A, & C are implemented in any one bank.
Any other addresses sent while accessing any of the
D
shadow register banks are invalid and have no effect.

When SHADEN1 and SHADEN2 are both set to logic 0
(decoder register F set to XX00) all subsequent
Table 14 Shadow register accessability
SHADEN2 SHADEN1 FUNCTION INITIAL

0 0 Access decoder registers 0 - F reset
0 1 Access SAA732X shadow registers - bank 1 −
1 0 Access new shadow registers - bank 2 −
1 1 Access new shadow registers - bank 3 −
2002 Mar 26 41

SAA7824
7.17.4 SUMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS 0 TO F

Table 15 Registers 0 to F
REGISTER ADDRESS DATA FUNCTION INITIAL(1)

0 0000 X000 Mute reset
(Fade and X010 Attenuate −
attenuation)
X001 Full-scale −
X100 Step down −
X101 Step up −
1 0001 X000 Motor off mode reset
(Motor mode) X 001 Motor stop mode 1 −
X010 Motor stop mode 2 −
X011 Motor start mode 1 −
T
X100 Motor start mode 2 −
X101 Motor jump mode −
X111 Motor play mode −
X110 Motor jump mode 1 −
2
Status control
0010
AF
1XXX
0XXX
0000
0001
0010
0011
0100
0101
0110
Anti-windup active
Anti-windup off
Status = SUBQREADY-I
Status = MOTSTART1
Status = MOTSTART2
Status = MOTSTOP
Status = PLL lock
Status = V1
Status = V2
−
reset
reset
−
−
−
−
−
−
R
0111 Status = MOTOR-OV −
3 0011 1010 I2S-bus; CD-ROM mode −
(DAC output) 1011 EIAJ; CD-ROM mode −
1100 I2S-bus; 18-bit; 4fs mode reset
1111 I2S-bus; 18-bit; 2fs mode −
D
1110 I2S-bus; 16-bit; fs mode −

0000 EIAJ; 16-bit; 4fs −
0011 EIAJ; 16-bit; 2fs −
0010 EIAJ; 16-bit; fs −
0100 EIAJ; 18-bit; 4fs −
0111 EIAJ; 18-bit; 2fs −
0110 EIAJ; 18-bit; fs −
2002 Mar 26 42

SAA7824

4 0100 0000 Motor gain G = 3.2 reset
(Motor gain) 0001 Motor gain G = 4.0 −
0010 Motor gain G = 6.4 −
0011 Motor gain G = 8.0 −
0100 Motor gain G = 12.8 −
0101 Motor gain G = 16.0 −
0110 Motor gain G = 25.6 −
0111 Motor gain G = 32.0 −
5 0101 XX00 Motor f4 = 0.5 × n Hz reset
(Motor XX01 Motor f4 = 0.7 × n Hz −
bandwidth)
XX10 Motor f4 = 1.4 × n Hz −
T
XX11 Motor f4 = 2.8 × n Hz −
00XX Motor f3 = 0.85 × n Hz reset
01XX Motor f3 = 1.71 × n Hz −
10XX Motor f3 = 3.42 × n Hz −
6
(Motor output
configuration)
7
0110
0111
AF
XX00
XX01
XX10
XX11
00XX
01XX
10XX
11XX
XX00
Motor power maximum 37%
MOTO1, MOTO2 pins 3-state
Motor PWM mode
Motor PDM mode
Motor CDV mode
Interrupt signal from servo only at STATUS pin
reset
−
−
−
reset
−
−
−
reset
R
(DAC output XX10 Status bit from decoder status register or dc −
and STATUS offset information at STATUS pin (see also new
pin control) shadow register C bank 3)
X0XX DAC data normal value reset
X1XX DAC data inverted value −
D
0XXX Left channel first at DAC (WCLK normal) reset

1XXX Right channel first at DAC (WCLK inverted) −
8 See Table 16 −
(PLL loop filter
bandwidth)
9 1001 0011 PLL loop filter equalization reset
(PLL 0001 PLL 30 ns over-equalization −
equalization)
0010 PLL 15 ns over-equalization −
0100 PLL 15 ns under-equalization −
0101 PLL 30 ns under-equalization −
2002 Mar 26 43

SAA7824

A 1010 XX0X EBU data before concealment −
(EBU output) XX1X EBU data after concealment and fade reset
X0X0 Level II clock accuracy (<1000 ppm) reset
X0X1 Level I clock accuracy (<50 ppm) −
X1X0 Level III clock accuracy (>1000 ppm) −
X1X1 EBU off - output low −
0XXX Flags in EBU off reset
1XXX Flags in EBU on −
B 1011 XX00 Standby 1: ‘CD-STOP’ mode reset
(speed control) XX10 Standby 2: ‘CD-PAUSE’ mode −
XX11 Operating mode −
T
X0XX 8.4672 MHz crystal present reset
X1XX 16.9344 MHz crystal present −
0XXX Single-speed mode reset
1XXX Double-speed mode −
C
(versatile pins
interface and
KILL function)
D
(versatile pins
1100
1101
AF
XXX1
XXX0
XX0X
XX1X
00XX
01XX
0000
XX01
External off-track signal input at V1
Internal off-track signal used (V1 may be read via
status)
Stereo KILL
Mono KILL
V3 = 0
V3 = 1
4-line motor (using V4 and V5)
Q-to-W subcode at V4
−
reset
−
reset
reset
−
−
−
R
interface)
XX10 V4 = 0 −
XX11 V4 = 1 reset
01XX De-emphasis signal at V5, no internal −
de-emphasis filter
10XX V5 = 0 −
D
11XX V5 = 1 reset
E 1110 XXX0 Motor brakes to 12% reset
XXX1 Motor brakes to 6% −
XX0X Lock-to-disc mode disabled reset
XX1X Lock-to-disc mode enabled −
X0XX Audio features disabled −
X1XX Audio features enabled reset
0XXX Quad speed mode disabled reset
1XXX Quad speed mode enabled −
2002 Mar 26 44

SAA7824

F 1111 X0XX Subcode interface off reset
(subcode X1XX Subcode interface on −
interface and
0XXX 4-wire subcode reset
shadow
register 1XXX 3-wire subcode −
enable) XX00 SHADEN bits = 00; shadow registers not reset
enabled; addresses will be decoded by main
decoder registers
XX01 SHADEN bits = 01; SAA732X shadow registers −
(bank 1) enabled; all subsequent addresses will
be decoded by shadow register bank 1, not
decoder registers
XX10 SHADEN bits = 10; new shadow registers (bank -
T
2) enabled; all subsequent addresses will be
decoded by shadow register bank 2.
XX11 SHADEN bits = 11; new shadow registers (bank -

3) enabled; all subsequent addresses will be
Note
REGISTER ADDRESS
AF
DATA
decoded by shadow register bank 3.
1. The initial column shows the Power-on reset state.
Table 16 Loop filter bandwidth
LOOP
FUNCTION
INTERNAL LOW-PASS INITIAL(1)
R
BANDWIDTH BANDWIDTH BANDWIDTH
(HZ) (HZ) (HZ)
8 1000 0000 1640 × n 525 × n 8400 × n −
(PLL loop filter 0001 3279 × n 263 × n 16800 × n −
bandwidth)
0010 6560 × n 131 × n 33600 × n −
D
0100 1640 × n 1050 × n 8400 × n −

0101 3279 × n 525 × n 16800 × n −
0110 6560 × n 263 × n 33600 × n −
1000 1640 × n 2101 × n 8400 × n −
1001 3279 × n 1050 × n 16800 × n reset
1010 6560 × n 525 × n 33600 × n −
1100 1640 × n 4200 × n 8400 × n −
1101 3279 × n 2101 × n 16800 × n −
1110 6560 × n 1050 × n 33600 × n −
Note
1. The initial column shows the Power-on reset state.
2002 Mar 26 45

SAA7824
7.17.5 SUMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS

Table 17 Bank 1 shadow register settings (single write)
SHADEN SHADOW
BITS REGISTER
01 3 0011 XX00 Select CLK4 on CLK4_12 output reset
control of XX01 Select CLK12 on CLK4_12 output −
(bank 1)
versatile and
X0XX Enable CLK16 output pin reset
clock pins
X1XX Set CLK16 output pin to high-impedance −
0XXX Set V3 output pin to high-impedance reset
1XXX Enable V3 output pin −
7 0111 0000 Use external DAC or route audio data back reset
control of into onboard DAC (loopback mode)
T
onboard DAC 0010 Route audio data directly into onboard DAC −
(non-loopback mode)
A 1010 0000 20mV −
signal 0001 25mV −
magnitude
0010 30mV −
control for
diodes
D1 to D4
(LF only)
AF 0011
0100
0101
0110
0111
1000
1001
1010
40mV
60mV
75mV
100mV
120mV
150mV
200mV
270mV
−
−
−
−
−
−
−
−
−
R
1011 350mV
1100 450mV −
1101 600mV −
1110 720mV −
1111 960mV reset
D
2002 Mar 26 46

SAA7824
SHADEN SHADOW
BITS REGISTER
01 C 1100 0000 20mV −
signal 0001 25mV −
(bank 1)
magnitude
0010 30mV −
control for
diodes 0011 40mV −
R1 and R2 0100 60mV −
(LF only) 0101 75mV −
0110 100mV −
0111 120mV −
1000 150mV −
1001 200mV −
T
1010 270mV −
1011 350mV −
1100 450mV −
1101 600mV −
−
SHADEN
BITS
10
(bank 2)
3
SHADOW
REGISTER
Power-down
control
AF
ADDRESS
0011
1110
1111
Table 18 Bank 2 new shadow register settings (single write)
DATA
XXX0
XXX1
XX0X
720mV
960mV
FUNCTION
Analogue front-end active

Analogue front-end powered down
Buffer amplifier on
reset
INITIAL
reset
−
reset
R
XX1X Buffer amplifier off (power saving) −
X0XX DAC active reset
X1XX DAC powered down −
3 0XXX Normal mode reset
DAC output 1XXX Current mode (bypass internal I-to-V −
D
mode converters).
7 0111 XX10 Voltage mechanism: 1.65*VDDA/3.3V
Mechanism & XX11 Voltage mechanism: 2.5*VDDA/3.3V −
voltage X0XX 150mV mechanism reset
reference X1XX 180mV mechanism −
selection
7 0XXX Flag all data (CRC pass and fail) reset
CD-text 1XXX Flag only data that passes the CRC −
control
2002 Mar 26 47

SAA7824
SHADEN SHADOW
BITS REGISTER
10 A 1010 XXX0 Approx 58% (Laser power control 2 = 0) reset
(bank 2) Laser power Approx 72% (Laser power control 2 = 1)
control 1
(See shadow register 3 bank 3)
XXX1 Approx 86% (Laser power control 2 = 0) −
Approx 100% (Laser power control 2 = 1)
(See shadow register 3 bank 3)
A XX0X Bypass PLL (external clock source) −
Clock source XX1X Select & enable PLL reset
T
A X0XX Disable silence injection reset
KILL control X1XX Enable silence injection −
0XXX Internal KILL reset
1XXX Loop-back KILL −
C
DC offset
measurement
times
C
Upsampler
dither
selection
AF
1100 XX00
XX01
XX10
XX11
00XX
01XX
10XX
11XX
Settling time = 354 µs
Settling time = 1ms
Settling time = 2ms
Settling time = 10ms
No dither selected
ac dither only
dc dither only
ac & dc dither selected
reset
−
−
−
−
−
−
reset
R
D
2002 Mar 26 48

SAA7824
SHADEN SHADOW
BITS REGISTER
11 3 0011 X000 Select D1 reset
(bank 3) Diode X001 Select D1 −
selection for X010 Select D2 −
DC offset X011 Select D3 −
measurement
X100 Select D4 −
X101 Select R1 −
X110 Select R2 −
X111 Select D1 −
T
3 0XXX 60% (Laser power control 1 = 0) reset
Laser power 87% (Laser power control 1 = 1)
control 2
(See shadow register A bank 2)
1XXX 73% (Laser power control 1 = 0) −
C
Enable
equaliser
C
STATUS pin
control
AF
1100 XXX0
XXX1
000X
001X
100% (Laser power control 1 = 1)
(See shadow register A bank 2)
Equaliser disabled and powered
down
Equaliser enabled
STATUS pin outputs decoder status
register information
STATUS pin outputs DC offset ready
reset
−
reset
−
flag
R
010X STATUS pin outputs DC offset value −
Table 20 Bank 3 new shadow register settings (multiple write)
SHADEN SHADOW SIZE (DATA

D
ADDRESS REGISTER ELEMENTS(1)

BITS REGISTER NIBBLES)
11 7 0111 9 <r2_off> <r1_off> <d4_off> <d3_off> <d2_off>
<d1_off>
(bank 3) DC
cancellation
levels
A 1010 4 <hp_filter_sel> <eq_speed_sel> <slicer_slew>
<hf_gain>
Analogue FE
control
Note
1. Register elements are described in Table 21.
2002 Mar 26 49

SAA7824
Table 21 Multiple write register element description
SHADOW ELEMENT BIT

DESCRIPTION
REGISTER NAME NUMBERS
7 (bank 3) <d1_off> <5:0> DC offset level for D1 (Reset value = 000000)
<d2_off> <11:6> DC offset level for D2 (Reset value = 000000)
<r1_off> <29:24> DC offset level for R1 (Reset value = 000000)
<r2_off> <35:30> DC offset level for R2 (Reset value = 000000)
A (bank 3) <hf_gain> <3:0> Data Description
0000 1.11V
T
0001 952mV
0010 588mV
0011 392mV
0100 1.11V
0101 952mV
AF 0110
0111
1000
1001
1010
1011
1100
1101
588mV
392mV
303mV
200mV
157mV
107mV
79mV
54mV
R
1110 39mV
1111 27mV
<slicer_slew> <7:4> Slicer threshold tracking slew-rate (ISlice code to current conversion)
Data Current (µA) Data Current (µA)
0000 10 (reset) 1000 100
D
0001 10 1001 110

0010 20 1010 120
0011 30 1011 130
0100 50 1100 150
0101 60 1101 160
0110 70 1110 170
0111 80 1111 180
<eq_speed_sel> <9:8> Equaliser operating speed: 00 = 1X (reset); 01 = 2X; 11 = 4X
2002 Mar 26 50

SAA7824
Table 21 Multiple write register element description
SHADOW ELEMENT BIT

DESCRIPTION
REGISTER NAME NUMBERS
A (bank 3) <hp_filter_sel> <15:10> High-pass filter frequency cut-off level (lowest roll-on)
Data Nominal Percentage Actual
Frequency Deviation Frequency
(kHz) (kHz)
000000 10 k Hz -37.5 % 6.367 (reset)
010000 -28.2 % 7.31
001000 -17.6 % 8.395
011000 -9.2 % 9.247
000100 0% 10.186
010100 +8.6 % 11.066
T
001100 +18 % 12.023
000010 20 k Hz -37.5 % 12.706
010010 -28.2 % 14.588
001010 -17.6 % 16.520
AF 011010
000110
010110
001110
000001
010001
001001
011001
30 k Hz
-9.2 %
0%
+8.6 %
+18 %
-37.5 %
-28.2 %
-17.6 %
-9.2 %
18.45
20.324
22.080
23.988
18.967
21.777
24.660
27.542
R
000101 0% 30.339
010101 +8.6 % 32.961
001101 +18 % 35.318
000011 40 k Hz -37.5 % 25.003
010011 -28.2 % 29.107
D
001011 -17.6 % 32.961

011011 -9.2 % 36.307
000111 0% 39.994
010111 +8.6 % 43.451
001111 +18 % 47.206
2002 Mar 26 51

SAA7824
7.17.6 SUMMARY OF SERVO COMMANDS

A list of the servo commands are given in Table 22. These are fully compatible with the SAA732X.
Table 22 SAA7824 servo commands
COMMANDS CODE BYTES PARAMETERS

Write commands
Write_focus_coefs1 17H 7 <foc_parm3> <foc_int> <ramp_incr> <ramp_height>
<ramp_offset> <FE_start> <foc_gain>
Write_focus_coefs2 27H 7 <defect_parm> <rad_parm_jump> <vel_parm2>
<vel_parm1> <foc_parm1> <foc_parm2> <CA_drop>
Write_focus_command 33H 3 <foc_mask> <foc_stat> <FFh>
Focus_gain_up 42H 2 <foc_gain> <foc_parm1>
T
Focus_gain_down 62H 2 <foc_gain> <foc_parm1>
Write_radial coefs 57H 7 <rad_length_lead> <rad_int> <rad_parm_play>
<rad_pole_noise> <rad_gain> <sledge_parm2>
<sledge_parm_1>
Preset_Latch 81H 1 <chip_init>
Radial_off
Radial_init
Short_jump
Long_jump
Steer_sledge
Preset_init
Write_decoder_reg(1)
Write_parameter
C1H
C1H
C3H
C5H
B1H
93H
D1H
A2H
AF 1
1
3
5
1
3
1
2
‘1CH’
‘3CH’
<tracks_hi> <tracks_lo> <rad_stat>
<brake_dist> <sledge_U_max> <tracks_hi> <tracks_lo>
<rad_stat>
<sledge_level>
<re_offset> <re_gain> <sum_gain>
<decoder_reg_data>
<param_ram_addr> <param_data>
R
Read commands
Read_Q_subcode(1)(2) 0H up to 12 <Q_sub1 to 10> <peak_l> <peak_r>
Read_status 70H up to 5 <foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi>
<tracks_lo>
Read_hilevel_status(3) E0H up to 4 <intreq> <dec_stat> <seq_stat> <motor_start_time>
D
Read_aux_status F0H up to 3 <re_offset> <re_gain> <sum_gain>
Notes
1. These commands only available when internal decoder interface is enabled.
2. <peak_l> and <peak_r> bytes are clocked out LSB first.
3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled.
2002 Mar 26 52

SAA7824
7.17.7 SUMMARY OF SERVO COMMAND PARAMETERS

Table 23 Servo command parameters
RAM
PARAMETER AFFECTS POR VALUE DETERMINES
ADDRESS
foc_parm_1 − focus PID − end of focus lead
defect detector enabling
foc_parm_2 − focus PID − focus low-pass
focus error normalising
foc_parm_3 − focus PID − focus lead length
minimum light level
foc_int 14H focus PID − focus integrator crossover frequency
foc_gain 15H focus PID 70H focus PID loop gain
T
CA_drop 12H focus PID − sensitivity of dropout detector
ramp_offset 16H focus ramp − asymmetry of focus ramp
ramp_height 18H focus ramp − peak-to-peak value of ramp voltage
ramp_incr − focus ramp − slope of ramp voltage
FE_start
rad_parm_play
rad_pole_noise
rad_length_lead
rad_int
rad_gain
rad_parm_jump
vel_parm1
vel_parm2
19H
28H
29H
1CH
1EH
2AH
27H
1FH
32H
AF
focus ramp
radial PID
radial PID
radial PID
radial PID
radial PID
radial jump
radial jump
radial jump
−
−
−
−
−
70H
−
−
−
minimum value of focus error
end of radial lead
radial low-pass
length of radial lead
radial integrator crossover frequency
radial loop gain
filter during jump
PI controller crossover frequencies
jump pre-defined profile
R
speed_threshold 48H radial jump − maximum speed in fastrad mode
hold_mult 49H radial jump 00H electronic damping
sledge bandwidth during jump
brake_dist_max 21H radial jump − maximum sledge distance allowed in fast
actuator steered mode
D
sledge_long_brake 58H radial jump FFH brake distance of sledge

sledge_Umax − sledge − voltage on sledge during long jump
sledge_level − sledge − voltage on sledge when steered
sledge_parm_1 36H sledge − sledge integrator crossover frequency
sledge_parm_2 17H sledge − sledge low-pass frequencies
sledge gain
sledge operation mode
sledge_pulse1 46H pulsed sledge − pulse width
sledge_pulse2 64H pulsed sledge − pulse height
defect_parm − defect detector − defect detector setting
playwatchtime 54H Watchdog − radial on-track Watchdog time
jumpwatchtime 57H Watchdog − radial jump Watchdog time-out
2002 Mar 26 53

SAA7824
RAM
PARAMETER AFFECTS POR VALUE DETERMINES
ADDRESS
radcontrol 59H Watchdog − enable/disable automatic radial off feature
chip_init − set-up − enable/disable decoder interface
xtra_preset 4AH set-up 38H laser on/off
RA, FO and SL PDM modulating frequency
fast jumping circuit on/off
cd6cmd 4DH decoder − decoder part commands
interface
interrupt_mask 53H STATUS pin − enabled interrupts
seq_control 42H autosequencer − autosequencer control
focus_start_time 5EH autosequencer − focus start time
−
T
motor_start_time1 5FH autosequencer motor start 1 time
motor_start_time2 60H autosequencer − motor start 2 time
radial_init_time 61H autosequencer − radial initialization time
brake_time 62H autosequencer − brake time
RadCmdByte 63H autosequencer − radial command byte
osc_inc
phase_shift
level1
level2
agc_gain
68H
67H
69H
6AH
6CH
AF
focus/radial
AGC
focus/radial
AGC
focus/radial
AGC
focus/radial
AGC
focus/radial
−
−
−
−
AGC control
frequency of injected signal
phase shift of injected signal
amplitude of signal injected
amplitude of signal injected
focus/radial gain
R
AGC
D
2002 Mar 26 54

SAA7824
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDD Supply voltage, internal rail -0.5 +2.5 V
VDDE Supply voltage, external rail -0.5 +3.6 V
VI(max) maximum input voltage
any input Notes 1,2, & 3 −0.5 VDDE + 0.5 V
5V tolerant pins −0.5 +6.0 V
VO output voltage (any output) −0.5 VDDE V
I DC supply current per supply pin Note 4 − 20 mA
I DC ground current per supply pin Note 4 − 20 mA
Ves electrostatic handling Note 5 −2000 +2000 V
T
Note 6 −200 +200 V
Tamb ambient temperature 0 +70 °C
Tstg storage temperature −55 +125 °C
Notes
1. Not to exceed 4.2V.
AF
2. Including voltage on outputs in tristate mode.
3. Only valid when both supply voltages are present.
4. The peak current is limited to 25 times the corresponding maximum current.
5. Human body model.
6. Machine model.
9 CHARACTERISTICS
VDD = 1.65 to 1.95 V; VSS = 0 V; Tamb = 0 to +70 °C; unless otherwise specified.
R
Supply
VDD supply voltage 1.65 1.8 1.95 V
IDD supply current n = 1 mode − 37 − mA
D
n = 2 mode − 39 − mA
n = 4 mode − 40 − mA
DEM DAC output (VDDD = 3.3 V, Vpos = 3.3 V; VSS = 0 V, Vneg = 0 V; Tamb = 25 °C)
DIFFERENTIAL OUTPUTS: PINS DAC_LN, DAC_LP, DAC_RN AND DAC_RP
S/N signal-to-noise ratio note 1 − 90 − dB
(THD + N)/S total harmonic distortion note 2 − − -80 dB
plus noise-to-signal ratio
Headphone buffer (VDDD = 3.3 V, Vpos = 3.3 V; VSS = 0 V, Vneg = 0 V; Tamb = 25 °C)
OUTPUTS: PINS BUF_OUT_R AND BUF_OUT_L
S/N signal-to-noise ratio − 85 − dB
2002 Mar 26 55

SAA7824

(THD + N)/S total harmonic distortion Note 3 − − -80 dB
INPUTS: PINS BUF_IN_R AND BUF_IN_L
Zi Input impedance − 47 - KΩ
Servo and decoder analog functions (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 °C)
REFERENCE GENERATOR: PIN IREF
VIref reference voltage level 1.14 1.2 1.26 V
Iref input reference current − 50 − µA
RIref external resistor ±2% − 24 − KΩ
PINS D1 TO D4; R1 AND R2
T
VD(max) maximum input voltage for 0 − 960 mV
central diode input signal
VR(max) maximum input voltage for 0 − 960 mV
satellite diode input signal
VRef internally generated Vref_sel=10 − 1.65*3.3/ − V
VRef
HF BW
HF Gtol
LF BW
LF THD + N
reference voltage
internally generated
reference voltage
HF bandwidth D1-D4
gain tolerance
LF bandwidth
D1-D4,R1-R2
total harmonic distortion
AF Vref_sel=11
at 0 dB
at 0 dB
at 0 dB
−
5
−20
20
−
VDDA
2.5*3.3/V
DDA
−50
−
+20
−
−30
V
MHz
%
kHz
dB
R
LF S/N signal-to-noise ratio 55 − dB
LF Gtol gain tolerance −20 0 +20 %
LF ∆Gv variation of gain between −3 − 3 %
channels
LF αcs channel separation − 60 − dB
D
Laser drive circuit (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 °C; RIref = 30 kΩ)
Iout Output current Vlaser=1V-(VDDA-0.6V) 10 50 120 mA
SNR Signal-to-noise ratio Iout=50mA;B/W=20MHz − 40 − dB
Ipmax Laser supply Iout=120mA − − 140 mA
Vinn1 Monitor diode voltage max. power; sel180=0 140 150 160 mV
Vinn2 Monitor diode voltage max. power; sel180=1 170 180 190 mV
Rin Input resistance 10 − − ΜΩ
Vsense Sense voltage -100 − +100 mV
Pstep Laser output power range 43 − 100 %
2002 Mar 26 56

SAA7824

Ipwd power down supply current − − 10 µA
Ioff Laser off current − − 30 µA
Digital inputs
PIN RESET (5V TOLERANT; TTL INPUTS WITH PULL-UP RESISTOR AND HYSTERESIS)
VIH High level input voltage 2.0 − − V
VIL Low level input voltage − − 0.8 V
Vhys Hysteresis voltage 0.3 − − V
IPU Pull-up current (Notes 4, 5) 0 < Vi < VDD -13 -50 -36 µA
tresL reset pulse width RESET only 1 − − µs
(active LOW)
T
PIN V1 & V2 (CMOS INPUTS)
PINS TEST1, TEST2, TEST3 & TEST4 (5V TOLERANT; TTL INPUTS WITH PULL-DOWN RESISTORS)
VIH
VIL
IPD
VIH
VIL
Iil
High level input voltage
Low level input voltage
High level input voltage

Low level input voltage
Low level input current
AF
Pull-down current (Notes 4, VDD < Vi < VDDE;
5)
Vi = 5V (Note 6)
PINS RCK, WCLI, SDI AND SCLI (5V TOLERANT; TTL INPUTS)
Vi = 0; no pull-up
2.0
−
20
2.0
−
-
−
−
50
−
−
−
−
0.8
75
−
0.8
1
V
V
µA
V
V
µA
R
Iih High level input current Vi = VDDE; no pull-down − − 1 µA
PINS SCL, SILD, RAB AND CDT_CLK (5 V TOLERANT TTL INPUTS WITH HYSTERESIS)
Iil Low level input current Vi = 0; no pull-up - − 1 µA
D
Iih High level input current Vi = VDDE; no pull-down − − 1 µA

Vhys Hysteresis voltage 0.3 − − V
3-state outputs
PINS SCLK, WCLK, DATA, CLK16, RA, FO, SL, SBSY, SFSY, CLK4_12, STATUS, MOTO1, & MOTO2
(5V TOLERANT CMOS OUTPUTS;10NS SLEW RATE LIMITED)
VOL Low-level output voltage IOL = 4mA - − 0.4 V
VOH High-level output voltage IOH = −4mA VDDE − 0.4 − - V
IOL Low-level output current VOL = 0.4V (Note 7) +4 − - mA
IOH High-level output current VOL = VDDE - 0.4V (Note -4 − - mA
7)
tTHL, tTLH Output transition time CL = 30pF 10.2 − 14.5 ns
2002 Mar 26 57

SAA7824

IOZ 3-state leakage current Vi = 0, VDDE; no − − 1 µA
pull-up/down device
PINS DOBM, V4, & V5 (5V TOLERANT CMOS OUTPUTS; 5NS SLEW RATE LIMITED)
7)
tTHL, tTLH Output transition time CL = 30pF − 10 13.8 ns
IOZ 3-state leakage current Vi = 0, VDDE − − 1 µA
Digital input/output
T
PIN V3 (5 V TOLERANT; TTL INPUT; 3-STATE OUTPUT)
Iil Low level input current Vi = 0; no pull-up - − 1 µA
Iih
VOL
VOH
IOL
IOH
tTHL, tTLH
IOZ
PINS
High level input current
Low-level output voltage
High-level output voltage
Low-level output current
High-level output current
Output transition time

3-state leakage current
AF
Vi = VDDE; no pull-down
IOL = 4mA
IOH = −4mA
VOL = 0.4V (Note 7)
VOL = VDDE - 0.4V (Note
7)
CL = 30pF
Vi = 0, VDDE
−
-
VDDE − 0.4
+4
-4
2.6
−
−
−
−
−
−
−
−
1
0.4
-
-
-
6.3
1
LKILL, RKILL, & CFLAG (5V TOLERANT; TTL INPUT WITH PULL-UP; 3-STATE OPEN-DRAIN OUTPUT; 10NS SLEW RATE
µA
V
V
mA
mA
ns
µA
R
LIMITED)

IPU Pull-up current (Notes 4, 5) 0 < Vi < VDD -13 -50 -36 µA
D

7)
tTHL, tTLH Output transition time CL = 30pF 8.6 10 13.8 ns
PINS CDT_RDY, CDT_DATA, EF, & SUB (5V TOLERANT; TTL INPUT; 3-STATE OUTPUT; 10NS SLEW RATE LIMITED)
Iil Low level input current Vi = 0 - − 1 µA
Iih High level input current Vi = VDDE − − 1 µA
2002 Mar 26 58

SAA7824

7)
tTHL, tTLH Output transition time CL = 30pF 8.6 10 13.8 ns
PIN SDA (5V TOLERANT; 400KHZ I2C PAD)
VIH High level input voltage 0.7 * VTOL − − V
VIL Low level input voltage VTOL = 5V (Note 8) − − 0.3 * VTOL V
Vhys Hysteresis voltage 0.05 * VTOL − − V
T
VOL Low-level output voltage IOL = 3 mA - − 0.4 V
tf Output fall time from VIH 20 + 0.1 * Cb − 250 ns
(Note 9)
to VIL (Bus capacitance,
Cb, from 10pF to 400pF)
Ilkg
VIL
VIH
Steady-state current input
signal (note 10)
Crystal oscillator
INPUT: PIN OSCIN (EXTERNAL CLOCK)
LOW-level input voltage
HIGH-level input voltage
OUTPUT: PIN OSCOUT; SEE FIG. 4
VOL Low-level output voltage
AFVi = VDDE
Vi = 5V
−
0.8*VDD
−
2
10
−
−
−
4
22
0.2*VDD
−
0.4
µA
µA
V
V
V
R
VOH High-level output voltage 0.85*VDD − − V
fxtal crystal frequency ±100 ppm 5 − 27 MHz
gm mutual conductance at 19.1 − 23.0 mA/V
start-up
Notes
D
1. Assumes use of external components as shown in the application diagram (Fig 38).
2. 10KΩ load.
3. 1KΩ load.
4. Pull up/down devices are protected by a pass-gate and do not behave as a normal resistor for external applications.
5. Pull up/down resistors are connected to external power supply (VDDE/GND).
6. Minimum condition for Vi = 4.5V. Maximum condition for Vi = 5.5V.
7. Accounts for 100mV voltage drop in both supply lines.
8. Minimum condition for VTOL = 4.5V, Maximum condition for VTOL = 5.5V.
9. Cb in pF.
10. Leakage path from pad to gnd.
2002 Mar 26 59

SAA7824
10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Subcode interface timing (single speed × n); see Fig.32; note 1
INPUT: PIN RCK
tCLKH input clock HIGH time 2/n 4/n 6/n µs
tCLKL input clock LOW time 2/n 4/n 6/n µs
tr input clock rise time − − 80/n ns
tf input clock fall time − − 80/n ns
td(SFSY-RCK) delay time SFSY to RCK 10/n − 20/n µs
OUTPUTS: PINS SBSY, SFSY AND SUB (CL = 20 PF)
Tcy(block) block cycle time 12.0/n 13.3/n 14.7/n ms
T
tW(SBSY) SBSY pulse width − − 300/n µs
Tcy(frame) frame cycle time 122/n 136/n 150/n µs
tW(SFSY) SFSY pulse width (3-wire mode only) − − 366/n µs
tSFSYH SFSY HIGH time − − 66/n µs
tSFSYL
td(SFSY-SUB)
td(RCK-SUB)
th(RCK-SUB)
Note
SFSY LOW time
AF
delay time SFSY to SUB (P data) valid
delay time RCK falling to SUB
hold time RCK to SUB
−
−
−
−
−
−
−
−
84/n
1/n
0
0.7/n
µs
µs
µs
µs
1. The subcode timing is directly related to the overspeed factor ‘n’ in normal operating mode. ‘n’ is replaced by the disc
speed factor ‘d’, in lock-to-disc mode.
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2002 Mar 26 60

SAA7824
handbook, full pagewidth tW(SBSY) Tcy(block)
SBSY
tSFSYH
SFSY
(4-wire mode)
tW(SFSY) Tcy(frame)
SFSY
(3-wire mode)
tSFSYL
T
SFSY
0.8 V
td(SFSY−RCK)
RCK
SUB
AF
td(SFSY−SUB)
tr
th(RCK−SUB)
tf
VDD – 0.8 V
td(RCK−SUB)
0.8 V
VDD – 0.8 V
0.8 V
R
MGL718
Fig.32 Subcode interface timing diagram.

D
11 OPERATING CHARACTERISTICS (I2S-BUS TIMING)

I2S-bus timing (single-speed × n); see Fig.33; note 1

CLOCK OUTPUT: PIN SCLK (CL = 20 PF)
Tcy output clock period sample rate = fs − 472.4/n − ns
sample rate = 2fs − 236.2/n − ns
sample rate = 4fs − 118.1/n − ns
2002 Mar 26 61

SAA7824

tCH clock HIGH time sample rate = fs 166/n − − ns
sample rate = 2fs 83/n − − ns
tCL clock LOW time sample rate = fs 166/n − − ns
OUTPUTS: PINS WCLK, DATA AND EF (CL = 20 PF)
tsu set-up time sample rate = fs 95/n − − ns
th hold time sample rate = fs 95/n − − ns
T
Note
1. The I2S-bus timing is directly related to the overspeed factor ‘n’ in the normal operating mode. In the lock-to-disc
SCLK
AF
mode ‘n’ is replaced by the disc speed factor ‘d’.
clock period Tcy

t CL t CH
V DD – 0.8 V
R
0.8 V
t su
th
V DD – 0.8 V
WCLK
DATA
EF 0.8 V
MBG407
D
Fig.33 I2S-bus timing diagram.
2002 Mar 26 62

SAA7824
12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)

NORMAL MODE LOCK-TO-DISC MODE

SYMBOL PARAMETER CONDITIONS UNIT
MIN. MAX. MIN. MAX.
Microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to F; reading Q-channel
subcode and decoder status); see Figs 34 and 35; note 1
INPUTS SCL AND RAB
tCL input LOW time 480/n + 20 − 2400/n + 20 − ns
tCH input HIGH time 480/n + 20 − 2400/n + 20 − ns
tr rise time − 480/n − 480/n ns
tf fall time − 480/n − 480/n ns
READ MODE (CL = 20 PF)
T
tdRD delay time RAB to SDA − 50 − 50 ns
valid
tPD propagation delay SCL to 720/n − 20 960/n + 20 720/n + 20 4800/n + 20 ns
SDA
tdRZ
thD
tsuCR
tdWZ
delay time RAB to SDA
high-impedance
WRITE MODE (CL = 20 PF)
tsuD set-up time SDA to SCL
hold time SCL to SDA
set-up time SCL to RAB
delay time SDA
high-impedance to RAB
AF
note 2
−
20 − 720/n
−
240/n + 20 −
0
50
−
960/n + 20 −
−
−
20 − 720/n
1200/n + 20 −
0
Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 34 and 36; note 2
50
−
4800/n + 20 ns
−
ns
ns
ns
ns
R
INPUTS SCL AND SILD
tL input LOW time 710 − 710 − ns
tH input HIGH time 710 − 710 − ns
tr rise time − 240 − 240 ns
− −
D
tf fall time 240 240 ns

READ MODE (CL = 20 PF)
tdLD delay time SILD to SDA − 25 − 25 ns
valid
tPD propagation delay SCL to − 950 − 950 ns
SDA
tdLZ delay time SILD to SDA − 50 − 50 ns
high-impedance
tsCLR set-up time SCL to SILD 480 − 480 − ns
thCLR hold time SILD to SCL 830 − 830 − ns
2002 Mar 26 63

SAA7824
NORMAL MODE LOCK-TO-DISC MODE

SYMBOL PARAMETER CONDITIONS UNIT
MIN. MAX. MIN. MAX.
WRITE MODE (CL = 20 PF)
tsD set-up time SDA to SCL 0 − 0 − ns
thD hold time SCL to SDA 950 − 950 − ns
tsCL set-up time SCL to SILD 480 − 480 − ns
thCL hold time SILD to SCL 120 − 120 − ns
tdPLP delay between two SILD 70 − 70 − µs
pulses
tdWZ delay time SDA 0 − 0 − ns
high-impedance to SILD
Notes
T
1. The 4-wire bus mode microcontroller interface timing for writing to decoder registers 0 to F, and reading Q-channel
subcode and decoder status, is a function of the overspeed factor ‘n’. In the lock-to-disc mode the maximum data
rate is lower.
2. Negative set-up time means that the data may change after clock transition.
RAB
tr
AF tf
VDD − 0.8 V
R
tr tf 0.8 V
t CH
VDD − 0.8 V
t dRD
SCL
0.8 V
t dRZ
D
t CL
t PD
VDD − 0.8 V
SDA (SAA782X)
high-impedance
0.8 V
GSA095
Fig.34 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information).
2002 Mar 26 64

SAA7824
tr t CH tf
t suCR V – 0.8 V
DD
RAB
0.8 V
t CH t CL
tf tr
VDD – 0.8 V
SCL
0.8 V
t CL t t dWZ
T
hD
t suD
V DD – 0.8 V
SDA
(microcontroller) high-impedance
0.8 V MBG405

AF
Fig.35 4-wire bus microcontroller timing; write mode (decoder registers 0 to F).
R
VDD − 0.8 V
SILD
0.8 V
t hCLR
t sCLR
D
VDD − 0.8 V
SCL
0.8 V
t dLD t PD t dLZ
VDD − 0.8 V
SDA
(SAA782X)
0.8 V
GSA096
Fig.36 4-wire bus microcontroller timing; read mode (servo commands).
2002 Mar 26 65

SAA7824

VDD - 0.8 V
SILD
0.8 V
tsCL tL
tH tdPLP
VDD – 0.8 V
SCL
0.8 V
thCL
tsD tL
T
tdWZ
thD
VDD – 0.8 V
SDA
(microcontroller)
0.8 V
AF MBG416
Fig.37 4-wire bus microcontroller timing; write mode (servo commands).

R
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2002 Mar 26 66

SAA7824
13 APPLICATION INFORMATION
T
AF
Fig.38 Typical application diagram
SAA7824
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2002 Mar 26 67

SAA7824
14 PACKAGE OUTLINE
T
AF
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SAA7824
15 SOLDERING
15.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for
surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often
used.
15.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the
printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times
(preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
T
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should
preferable be kept below 230 °C.
15.3 Wave soldering
AF
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with
a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
If wave soldering is used the following conditions must be observed for optimal results:
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2002 Mar 26 69

SAA7824
• Use a double-wave soldering method comprising a can be applied by screen printing, pin transfer or syringe
turbulent wave with high upward pressure followed by dispensing. The package can be soldered after the
a smooth laminar wave. adhesive is cured.
• For packages with leads on two sides and a pitch (e): Typical dwell time is 4 seconds at 250 °C.
– larger than or equal to 1.27 mm, the footprint A mildly-activated flux will eliminate the need for removal
longitudinal axis is preferred to be parallel to the of corrosive residues in most applications.
transport direction of the printed-circuit board;
15.4 Manual soldering
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the Fix the component by first soldering two
printed-circuit board. diagonally-opposite end leads. Use a low voltage (24 V or
The footprint must incorporate solder thieves at the less) soldering iron applied to the flat part of the lead.
downstream end. Contact time must be limited to 10 seconds at up to
300 °C.
• For packages with leads on four sides, the footprint
must be placed at a 45° angle to the transport direction When using a dedicated tool, all other leads can be
T
of the printed-circuit board. The footprint must soldered in one operation within 2 to 5 seconds between
incorporate solder thieves downstream and at the side 270 and 320 °C.
corners.
15.5 Suitability of surface mount IC packages for
During placement and before soldering, the package
wave and reflow soldering methods
must be fixed with a droplet of adhesive. The adhesive
BGA, SQFP
PACKAGE
PLCC(3), SO, SOJ

LQFP, QFP, TQFP
SSOP, TSSOP, VSO
AF not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
suitable
WAVE
not recommended(3)(4)
not recommended(5)
SOLDERING METHOD
suitable
suitable
suitable
suitable
suitable
REFLOW(1)
R
Notes 0.8 mm; it is definitely not suitable for packages with
1. All surface mount (SMD) packages are moisture a pitch (e) equal to or smaller than 0.65 mm.
sensitive. Depending upon the moisture content, the 5. Wave soldering is only suitable for SSOP and TSSOP
maximum temperature (with respect to time) and packages with a pitch (e) equal to or larger than
body size of the package, there is a risk that internal 0.65 mm; it is definitely not suitable for packages with
or external package cracks may occur due to a pitch (e) equal to or smaller than 0.5 mm.
D
vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack
information in the “Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering
as a solder joint between the printed-circuit board and
heatsink (at bottom version) can not be achieved, and
as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package
must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate
solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and
QFP packages with a pitch (e) equal to or larger than
2002 Mar 26 70

SAA7824
16 DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS DEFINITIONS (1)
STATUS
Objective specification Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification Production This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
T
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
17 DEFINITIONS
AF
Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are
stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics
sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information  Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified
use without further testing or modification.
R
18 DISCLAIMERS
Life support applications  These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify
Philips Semiconductors for any damages resulting from such application.
D
Right to make changes  Philips Semiconductors reserves the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or
performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or
warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise
specified.
2002 Mar 26 71

SAA7824
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
T
AF
R
D
2002 Mar 26 72

SAA7824
NOTES
T
AF
R
D
2002 Mar 26 73

SAA7824
Printed in The Netherlands 753503/02/pp76 Date of release: 2002 Mar 26 Document order number: 9397 750 069
2002 Mar 26 74
Philips Semiconductors – a worldwide company
Argentina: see South America Middle East: see Italy
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Tel. +31 40 27 82785, Fax. +31 40 27 88399
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Tel. +64 9 849 4160, Fax. +64 9 849 7811
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, Norway: Box 1, Manglerud 0612, OSLO,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belgium: see The Netherlands Pakistan: see Singapore
Brazil: see South America Philippines: Philips Semiconductors Philippines Inc.,
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
51 James Bourchier Blvd., 1407 SOFIA, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +48 22 5710 000, Fax. +48 22 5710 001
Tel. +1 800 234 7381, Fax. +1 800 943 0087 Portugal: see Spain
China/Hong Kong: 501 Hong Kong Industrial Technology Centre, Romania: see Italy
72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +852 2319 7888, Fax. +852 2319 7700 Tel. +7 095 755 6918, Fax. +7 095 755 6919
Colombia: see South America Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Czech Republic: see Austria Tel. +65 350 2538, Fax. +65 251 6500
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T
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Tel. +34 93 301 6312, Fax. +34 93 301 4107
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Tel. +353 1 7640 000, Fax. +353 1 7640 200

AF
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
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Tel. +39 039 203 6838, Fax +39 039 203 6800
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TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
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Tel. +66 2 361 7910, Fax. +66 2 398 3447
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ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
R
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
Tel. +82 2 709 1412, Fax. +82 2 709 1415 MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Uruguay: see South America
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Vietnam: see Singapore
D
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, For all other countries apply to: Philips
Tel. +381 11 3341 299, Fax.+381 11 3342 553
© Philips Electronics N.V. Semi SCAco

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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2002 Mar 26 76

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INTEGRATED CIRCUITS

CD audio decoder, digital servo & filterless DAC

CONTENTS 7.15.3 Loop characteristics

CD audio decoder, digital servo & filterless DAC

output power throughout laser life.

• Dynamic element matching DAC with minimal external

• DAC performance of -80dB THD+N and 90dB SNR

NUMBER NAME DESCRIPTION VERSION

CD audio decoder, digital servo & filterless DAC

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CD audio decoder, digital servo & filterless DAC

DC OFFSET COMPENSATION LASER

IREF BIAS D1-D4

Fig.1 Block diagram.

CD audio decoder, digital servo & filterless DAC

SYMBOL PIN DESCRIPTION

BUF_OUT_L 31 Audio buffer left output

CD audio decoder, digital servo & filterless DAC

SYMBOL PIN DESCRIPTION

CD audio decoder, digital servo & filterless DAC

7 FUNCTIONAL DESCRIPTION 7.2 Decoder part

CD audio decoder, digital servo & filterless DAC

High pass filter

7.2.2 DECODING SPEED AND CRYSTAL FREQUENCY

7.2.3 LOCK-TO-DISC MODE

in high-impedance, PDM mode (standby 1 and reset:

CD audio decoder, digital servo & filterless DAC

Table 1 Playback speeds

CRYSTAL FREQUENCY (MHz)

on the internal clock settings used.

but may be input via the V1 pin if selected by register C.

7.4 Data slicer and bit clock regenerator

CD audio decoder, digital servo & filterless DAC

The measurement time of the DC offset is regulated by

3. PLL, LPF The micro needs to be able to read the DC offset

cancellation function and are given in Table 3.

CD audio decoder, digital servo & filterless DAC

Table 3 Registers relating to DC offset cancellation

Fig.6 Serial data format for DC offset data

1: decoder reg 3 = XX10

1: shadow reg 7 = XX1X

FIFO (de-emphasis signal at V5) DAC_RP

CD audio decoder, digital servo & filterless DAC

7.6 Demodulator 7.7.3 V4 SUBCODE INTERFACE

7.6.2 EFM DEMODULATION

The 14-bit EFM data and subcode words are decoded

7.7 Subcode data processing

7.7.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)

Data from all the subcode channels (P-to-W) may be read

CD audio decoder, digital servo & filterless DAC

P-W P-W P-W

EIAJ 4-wire subcode interface

SF0 SF1 SF2 SF3 SF97 SF0 SF1

P-W P-W P-W

EIAJ 3-wire subcode interface

Fig.8 EIAJ subcode (CD graphics) interface format.

200/n µs 11.3/n 11.3/n µs min

Fig.9 Subcode format and timing on pin V4.

CD audio decoder, digital servo & filterless DAC

CDT_DATA CRC flag D0 D1 D2 D3 D126 D127

7.8 FIFO and error corrector AF