DATA SHEET

SPCA758A
MPEG Audio Decoder

Draft

Nov 07, 2002

Version 0.1

SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY
CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product
may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
 Draft
CD-Based MPEG Audio Decoder SPCA758A

Table of Contents
1. GENERAL DESCRIPTION................................................................................................................................................................... 3
Figure 1-1: CD-based MPEG Audio Player Systems....................................................................................................................... 3
2. FEATURES .......................................................................................................................................................................................... 4
3. BLOCK DIAGRAM............................................................................................................................................................................... 4
Figure 3-1: SPCA758A Block Diagram.................................................................................................................................................. 4
4. SIGNAL DESCRIPTIONS .................................................................................................................................................................... 5
4.1 PIN DESCRIPTION .......................................................................................................................................................................... 5
Figure 4-1: SPCA758A Signal Group Map .......................................................................................................................................... 8
4.2 PIN MAP ....................................................................................................................................................................................... 9
5. FUNCTIONAL DESCRIPTIONS......................................................................................................................................................... 10
Figure 5-1: PCM Interface clocking modes and waveform ................................................................................................................................ 12

6. ELECTRICAL SPECIFICATIONS ...................................................................................................................................................... 13

7. ADC APPLICATION CIRCUIT ........................................................................................................................................................... 14
Figure 7-1: Reference Circuit using ADC ............................................................................................................................................................ 14

8. PACKAGE INFORMATION ................................................................................................................................................................ 15

REVISION HISTORY............................................................................................................................................................................... 16
DISCLAIMER .......................................................................................................................................................................................... 16

© Sunplus Technology Co., Ltd. 2 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

1. GENERAL DESCRIPTION
The SPCA758A is a high performance, low power, single chip,
MPEG 1/2 layer 2/3 audio decoder. Superior integration
(including audio decoder, system MCU, SDRAM controller, and
PLL’s) makes the SPCA758A perfect for CD-based MP3 player
systems. The SPCA758A also contains a 10-bit 8/16 kHz
sampling rate audio ADC for voice recording applications.
The SPCA758A provides an ALL-IN-ONE solution that is ideally
optimized for CD-based portable MP3 players with voice recording
and playback functions. The built-in 8051-based MCU provides
an interface to the servo chips, LCD controller, and key inputs.
Encoded MPEG audio data stored in CD is sent to the SPCA758A
through a CDDSP interface which is programmable to fit different
CD servo chips. For CD shock resistance, the SPCA758A can
buffer up to 1000 seconds of MPEG audio bit stream or 90
seconds of CDDA data, dependent on the size of the external
SDRAM connected.
Decoded audio PCM data is output to an external DAC through a
programmable DAC interface such that most common audio
DAC’s can cooperate with the SPCA758A to meet different
customer requirements.
A high quality 10-bit 8/16 KHz sampling rate ADC is embedded for
voice recording. Based on the ADPCM algorithm, voice is
compressed to a low data rate of 32Kbps, while retaining a good
resolution of the original speech/audio.
The SPCA758A is designed for 2.5V(Core)/3.3V(I/O) applications
and the built-in PLL’s are able to synthesize the system clock and
the audio clocks from 6/16.9344 MHz crystal oscillator source.
The high performance SPCA758A signal processor can operate
with very low power dissipation, which makes the SPCA758A
extremely suitable for portable systems. The SPCA758A has
been designed with, not only the latest technology, but the full
service and support of Sunplus.
A common implementation utilizing the SPCA758A is presented
below:

LCD FM / AM Tuner

Normal / I2S
Audio DAC Speaker
Key Scan
Line Control SPCA758A
Voltage Detect Microphone
(8KHz 10bit)

3.3V DC_DC
Battery
CDdsp interface 2.5V Converter
DRAM
CD Kit

Figure 1-1: CD-based MPEG Audio Player Systems

© Sunplus Technology Co., Ltd. 3 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

2. FEATURES
■ Single chip MPEG audio decoder
— Conforming to MPEG1/MPEG2 audio layer2/31) — User selectable ESP methodology
— Extension to MPEG lower sampling rates — Buffers up to 1000 seconds of MPEG bit stream or 90
— Supports variable bit rates and free-format bitstream seconds of CDDA data
■ Digital sound control for both MP3 and CDDA ■ Supports ISO9660, UDF and Joliet formats
— Volume control ■ Built-in 8051-based MCU and 64KB internal program ROM
— Stereo/Mono channel select ■ MCU ICE interface to ease system firmware development
— 7-band sound equalizer, bass and treble control ■ Instead of using the embedded program ROM, external ROM
■ Internal auto-generated audio clock or E2PROM(up to 256KB) can be used as MCU program ROM,
— Supports sampling frequency 32, 44.1 and 48 KHz needs no low byte address latches.
■ Programmable audio DAC interface ■ 3 channel 8-bit ADC for peripheral controls
— Supports both normal and IIS audio DAC formats ■ High performance Digital Voice Recording
— Audio clock polarity programmable — Embedded AGC for dynamic sound receiving
— Internal auto-generated over-sampling clock for DAC — Embedded 10-bit 8/16 kHz sampling rate audio ADC
— Accepts external audio clock for sampling rate control — SACM_S3200 recording with 32 Kbit/sec
■ CDDSP interface ■ Device Parameter
— Directly inputs data from CD-kit — Supply voltage: 2.5 Volts for core; 3.3 Volts for IO
— Programmable interface for different CDDSP chips — IO interface: 5 volts tolerance, TTL compatible
— C3 EDC/ECC — Package: 128-pin LQFP
■ SDRAM interface — Power consumption: TBD
— Supports 1M, 4M, 8Mx16bits SDRAM’s
■ Embedded PLL
License Notice:
— Flexible reference crystal clock frequency: 6/12/24 MHz
1)
or 16.9344/33.8688 MHz MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and
THOMSON multimed.
■ Programmable ESP functions

3. BLOCK DIAGRAM
DATA
Control

MICP
MICN
SRAM
P3[5,4,2,1,0]
MICO
SRAM ROM P2[7:0]
AMPI
AMPO DSM ADC ROM
P1[7:0]
P0[7:0]
AGC
P0Al[7:0]
CMB System GPIO[6:0]
MCU
MPEG Audio Decoder
ROMWR_N
CD_LRCK
PSEN
CD_BCK
CD_C2P0 CDDSP TRAP
CD_DATA Voice Encoder/Decoder RESETB

ADDR[11:0]
PCM SAR
DRAM Controller PLL
ADC
DATA[15:0]
Buffer Clock Synthesizer
RASB

AUD_XCKIN
AUD_LRCK
AUD_DATA
CLOCK

AUD_BCK
AUD_XCK

XTALOUT
WEB

CASB

XTALIN

ADI[2:0]
CKE

CSB
BA0
BA1

Figure 3-1: SPCA758A Block Diagram

© Sunplus Technology Co., Ltd. 4 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

4. SIGNAL DESCRIPTIONS
4.1 PIN Description

No. Mnemonic Type Description Pad Type

1 MICO O AGC amplifier output

2 MICP I Positive input of AGC amplifier
3 MICN I Negative input of AGC amplifier
4 CMB O Reference voltage for common-mode bias
5 ADI0 I Input source 0 of SAR ADC
6 ADI1 I Input source 1 of SAR ADC
7 ADI2 I Input source 2 of SAR ADC
8 VSSADC ADC ground
9 VDD Digital core power
10 DRAMA4 I/O SDRAM Address bit 4 / I/O trap bit 4 CMOS 3-state output pad with input
11 DRAMA5 I/O SDRAM Address bit 5 / I/O trap bit 5 CMOS 3-state output pad with input
12 DRAMA6 I/O SDRAM Address bit 6 / I/O trap bit 6 CMOS 3-state output pad with input
13 DRAMA7 O SDRAM Address bit 7 CMOS 3-state output pad
14 DRAMA8 O SDRAM Address bit 8 CMOS 3-state output pad
15 DRAMA9 O SDRAM Address bit 9 CMOS 3-state output pad
16 DRAMA11 O SDRAM Address bit 11 CMOS 3-state output pad
17 DRAMCKE O SDRAM clock enable CMOS 3-state output pad
18 DRAMCLK O SDRAM system clock CMOS 3-state output pad
19 DRAMA3 I/O SDRAM Address bit 3 / I/O trap bit 3 CMOS 3-state output pad with input
20 DRAMA2 I/O SDRAM Address bit 2 / I/O trap bit 2 CMOS 3-state output pad with input
21 DRAMA1 I/O SDRAM Address bit 1 / I/O trap bit 1 CMOS 3-state output pad with input
22 DRAMA0 I/O SDRAM Address bit 0 / I/O trap bit 0 CMOS 3-state output pad with input
23 DRAMA10 O SDRAM Address bit 10 CMOS 3-state output pad
24 VDDIO Digital I/O power
25 VSS Digital ground
26 DRAMBA1 O SDRAM bank select address bit 1 CMOS 3-state output pad
27 DRAMBA0 O SDRAM bank select address bit 0 CMOS 3-state output pad
28 DRAMCSB I/O SDRAM chip select / I/O trap bit 7 CMOS 3-state output pad with input
29 DRAMRASB O SDRAM row address strobe CMOS 3-state output pad
30 DRAMCASB I/O SDRAM column address strobe / I/O trap bit 8 CMOS 3-state output pad with input
31 DRAMWEB O SDRAM write enable CMOS 3-state output pad
32 DRAMD7 I/O SDRAM data bit 7 CMOS 3-state output pad with input
33 DRAMD6 I/O SDRAM data bit 6 CMOS 3-state output pad with input
34 DRAMD5 I/O SDRAM data bit 5 CMOS 3-state output pad with input
35 DRAMD4 I/O SDRAM data bit 4 CMOS 3-state output pad with input
36 DRAMD3 I/O SDRAM data bit 3 CMOS 3-state output pad with input
37 DRAMD2 I/O SDRAM data bit 2 CMOS 3-state output pad with input
38 DRAMD1 I/O SDRAM data bit 1 CMOS 3-state output pad with input
39 DRAMD0 I/O SDRAM data bit 0 CMOS 3-state output pad with input
40 DRAMD8 I/O SDRAM data bit 8 CMOS 3-state output pad with input
41 DRAMD9 I/O SDRAM data bit 9 CMOS 3-state output pad with input

© Sunplus Technology Co., Ltd. 5 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

No. Mnemonic Type Description Pad Type

42 DRAMD10 I/O SDRAM data bit 10 CMOS 3-state output pad with input
43 DRAMD11 I/O SDRAM data bit 11 CMOS 3-state output pad with input
44 DRAMD12 I/O SDRAM data bit 12 CMOS 3-state output pad with input
45 DRAMD13 I/O SDRAM data bit 13 CMOS 3-state output pad with input
46 DRAMD14 I/O SDRAM data bit 14 CMOS 3-state output pad with input
47 DRAMD15 I/O SDRAM data bit 15 CMOS 3-state output pad with input
48 VDDIO Digital I/O power
49 VSS Digital ground
50 VDD Digital core power
51 CD_LRCK I CD left/right clock Schmitt trigger input pad
52 CD_DATA I CD serial data Schmitt trigger input pad
53 CD_C2PO I CD data error flag Schmitt trigger input pad
54 CD_BCLK I CD bit clock Schmitt trigger input pad
55 N.C.
56 AUD_XCKIN I Oversampling clock from external source Schmitt trigger input pad
57 N.C.
58 N.C.
59 N.C.
60 N.C.
61 N.C.
62 VSSPLL System PLL ground
63 VDDPLL PLL power
64 VSSAUD Audio PLL ground
65 XTALOUT O 6/12/24 or 16.9344/33.8688 MHz Oscillator Input
66 XTALIN I
67 VDD Digital core power
68 P10 I/O CPU port 1 bit 0. CMOS 3-state output pad with input
69 P11 I/O CPU port 1 bit 1. CMOS 3-state output pad with input
70 P12 I/O CPU port 1 bit 2. CMOS 3-state output pad with input
71 P13 I/O CPU port 1 bit 3. CMOS 3-state output pad with input
72 P14 I/O CPU port 1 bit 4. CMOS 3-state output pad with input
73 P15 I/O CPU port 1 bit 5. CMOS 3-state output pad with input
74 P16 I/O CPU port 1 bit 6. CMOS 3-state output pad with input
75 P17 I/O CPU port 1 bit 7. CMOS 3-state output pad with input
76 P30 I/O CPU port 3 bit 0. CMOS 3-state output pad with input
77 P31 I/O CPU port 3 bit 1. CMOS 3-state output pad with input
78 P32 I/O CPU port 3 bit 2. CMOS 3-state output pad with input
79 P34 I/O CPU port 3 bit 4. CMOS 3-state output pad with input
80 P35 I/O CPU port 3 bit 5. CMOS 3-state output pad with input
81 GPIO0 I/O General purpose I/O CMOS 3-state output pad with input
82 GPIO1 I/O General purpose I/O CMOS 3-state output pad with input
83 GPIO2 I/O General purpose I/O CMOS 3-state output pad with input
84 GPIO3 I/O General purpose I/O CMOS 3-state output pad with input
85 GPIO4 I/O General purpose I/O CMOS 3-state output pad with input

© Sunplus Technology Co., Ltd. 6 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

No. Mnemonic Type Description Pad Type

86 GPIO5 I/O General purpose I/O CMOS 3-state output pad with input
87 GPIO6 I/O General purpose I/O CMOS 3-state output pad with input
88 VDDIO Digital I/O power
89 VSS Digital ground
90 TRAP O I/O trap control CMOS 3-state output pad
91 P24 I/O CPU port 2, high byte address, bit 4. CMOS 3-state output pad with input
92 P27 I/O CPU port 2, high byte address, bit 7. CMOS 3-state output pad with input
93 ROMWR_N O External write pulse. This pin is used in the ISP CMOS 3-state output pad
(in-system-programming) function
94 P26 I/O CPU port 2, high byte address, bit 6. CMOS 3-state output pad with input
95 P25 I/O CPU port 2, high byte address, bit 5. CMOS 3-state output pad with input
96 P23 I/O CPU port 2, high byte address, bit 3. CMOS 3-state output pad with input
97 P21 I/O CPU port 2, high byte address, bit 1. CMOS 3-state output pad with input
98 P20 I/O CPU port 2, high byte address, bit 0. CMOS 3-state output pad with input
This bus (port2) is an output bus in the internal CPU
mode and an input bus in external CPU mode.
99 P0AL7 I/O CPU Low-byte address bit 7. CMOS 3-state output pad with input
100 P0AL6 I/O CPU Low-byte address bit 6. CMOS 3-state output pad with input
101 P0AL5 I/O CPU Low-byte address bit 5. CMOS 3-state output pad with input
102 P0AL4 I/O CPU Low-byte address bit 4. CMOS 3-state output pad with input
103 P0AL3 I/O CPU Low-byte address bit 3. CMOS 3-state output pad with input
104 P0AL2 I/O CPU Low-byte address bit 2. CMOS 3-state output pad with input
105 P0AL1 I/O CPU Low-byte address bit 1. CMOS 3-state output pad with input
106 P0AL0 I/O CPU Low-byte address bit 0. CMOS 3-state output pad with input
107 P22 I/O CPU port 2, high byte address, bit 2. CMOS 3-state output pad with input
108 VDDIO Digital I/O power
109 VSS Digital ground
110 VDD Digital core power
111 P00 I/O CPU port 0, address/data multiplex pin, bit 0. CMOS 3-state output pad with input
112 P01 I/O CPU port 0, address/data multiplex pin, bit 1. CMOS 3-state output pad with input
113 P02 I/O CPU port 0, address/data multiplex pin, bit 2. CMOS 3-state output pad with input
114 P03 I/O CPU port 0, address/data multiplex pin, bit 3. CMOS 3-state output pad with input
115 P04 I/O CPU port 0, address/data multiplex pin, bit 4. CMOS 3-state output pad with input
116 P05 I/O CPU port 0, address/data multiplex pin, bit 5. CMOS 3-state output pad with input
117 P06 I/O CPU port 0, address/data multiplex pin, bit 6. CMOS 3-state output pad with input
118 P07 I/O CPU port 0, address/data multiplex pin, bit 7. CMOS 3-state output pad with input
119 PSEN_N I/O Program space enable CMOS 3-state output pad with input
This pin is an output pin when the built-in CPU is
enabled. When external CPU is used, this pin is an
input pin.
120 AUD_BCK O Bit clock output to stereo audio DAC CMOS 3-state output pad
121 AUD_DATA O Serial data output to stereo audio DAC CMOS 3-state output pad
122 AUD_LRCK O Sample rate clock output to stereo audio DAC CMOS 3-state output pad
123 AUD_XCKOUT O Oversampling clock to external audio DAC CMOS 3-state output pad
124 RESET I System reset (active low) Schmitt trigger input pad

© Sunplus Technology Co., Ltd. 7 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

No. Mnemonic Type Description Pad Type

125 VDDADC ADC power

126 AMPI I Microphone amplifier input
127 AGC O AGC output voltage
128 AMPO O Microphone amplifier output
Note: N.C. pins are recommended tie to VSS

SDRAMADDR[11:0]
SDRAMDATA[15:0]
CKE AMPI
SDRAM/ CLK AMPO
IOTRAP BA1 ( IOTRAP[8:0] ) AGC
BA0 MICO
ADC
CSB MICP
RASB MICN
CASB CMB
WEB ADI[2:0]
VDDADC
TRAP VSSADC

P3[5:4],P32,P3[1:0]
P2[7:0]
VDD
P1[7:0]
MCU VSS
System
ROM P0[7:0]
P0AL[7:0]
SPCA758A RESET

ROMWR_N
PSEN

AUDXCKIN AUDBCK
CDBCLK AUDDATA
CD DAC
CDC2PO AUDLRCK
CDDIN AUDXCKOUT
CDLRCK

GPIO GPIO[6:0]

VSSSYSPLL
XTALIN VDDPLL PLL
Crystal
XTALOUT VSSAUDPLL

Figure 4-1: SPCA758A Signal Group Map

© Sunplus Technology Co., Ltd. 8 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

4.2 PIN Map

ROMWR_N

P16/SQCK
P17/SQDT

XTALOUT
P15/S0S1

XTALIN
VDDIO
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
TRAP

VDD
VSS

P10
P23
P25
P26
P27
P24

P35
P34
P32
P31
P30

P14
P13
P12
P11
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P21 97 64 VSSAUD
P20 98 63 VDDPLL
P0AL7 99 62 VSSPLL
P0AL6 100 61 NC
P0AL5 101 60 NC
P0AL4 102 59 NC
P0AL3 103 58 NC
P0AL2 104 57 NC
P0AL1 105 56 AUD_XCKIN
P0AL0 106 55 NC
P22 107 54 CD_BCLK
VDDIO 108 53 CD_C2PO
VSS 109 52 CD_DATA
VDD 110 51 CD_LRCK
P00
P01
P02
P03
111
112
113
114
SPCA758A 50
49
48
47
VDD
VSS
VDDIO
DRAMD15
P04
P05
115
116 LQFP 128 46
45
DRAMD14
DRAMD13
P06 117 44 DRAMD12
P07 118 43 DRAMD11
PSEN 119 42 DRAMD10
AUD_BCK 120 41 DRAMD9
AUD_DATA 121 40 DRAMD8
AUD_LRCK 122 39 DRAMD0
AUD_XCKOUT 123 38 DRAMD1
RESET 124 37 DRAMD2
VDDADC 125 36 DRAMD3
AMPI 126 35 DRAMD4
AGC 127 34 DRAMD5
AMPO 128 33 DRAMD6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
DRAMA4
DRAMA5
DRAMA6
DRAMA7
DRAMA8
DRAMA9
DRAMA11

DRAMA3
DRAMA2
DRAMA1
DRAMA0
DRAMA10

DRAMBA1
DRAMBA0
VSSADC
VDD

DRAMCLK

DRAMCSB
DRAMCKE

VSS

DRAMRASB
ADI0
ADI1
ADI2

DRAMD7
MICO

VDDIO
MICN
CMB
MICP

DRAMCASB
DRAMWEB

© Sunplus Technology Co., Ltd. 9 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

5. FUNCTIONAL DESCRIPTIONS
The SPCA758A is a single-chip CMOS microprocessor optimized for real-time MPEG audio decoding and speech/audio recording.

The 8051_based System MCU detects the user commands through general purpose programming IO’s and is in charge of the cooperation
of all the other functional units on chip to efficiently carry out MPEG audio decoding/playback or voice recording/decoding/playback
processes.

The SPCA758A contains a high performance DSP which decodes the encoded MPEG audio data according to the commands given by the
System MCU processor. The host processor monitors the status of decoding process. Refer to SPCA758A Programming Guide for
command definitions.

The encoded MPEG audio bitstream stored in the CD is sent to the SPCA758A through the programmable CDDSP interface. The
SPCA758A can manage external DRAM memory efficiently by using the SDRAM Control Interface to buffer up to 1000 seconds of MPEG
bitstream for CD shock proofing.

In the digital recorder mode, speech/audio is sampled at 8KHz by an on-chip DSM ADC into 10-bit digital words. After encoding by the
DSP, the datum is compressed into a data rate of 32Kbps. Encoded voice data could be decoded by the DSP for playback. Another
3-channel 8-bit SAR ADC can be used as analog control inputs, such as voltage detection and remote control.

Decoded audio PCM data is output to external DAC through a programmable normal/I2S PCM interface. This interface is compliant to
most common audio DAC’s.

The embedded PLL is capable of providing the system clock and the clocks for the external DAC derived from a 6/12/24 or
16.9344/33.8688 MHz crystal clock source.

! System MCU
The 8051-compatible MCU coordinates all the other devices on the SPCA758A and controls the CD servo chips through programmable

general-purpose IO pins. User commands are all interpreted by the MCU. The SPCA758A adopts an IO-trap mechanism to set some

configurations that must be determined immediately after the chip is powered-on. These configurations are not changed during the

operation of the SPCA758A. The following table lists the possible configurations.

Name Description
IO-trap[0] Extcpu 0: use internal CPU
1: use external CPU (or ICE)
IO-trap[1] Extrom 0: use internal ROM
1: use external ROM
Embedded ROM space is 64KB; using external ROM may extend to 256KB. The MCU can dynamically tune the clock frequencies for the

other components during operation to achieve optimized power consumption. In the suspend mode, the SPCA758A consumes extremely

low power.

! DSP
Powerful DSP is in charge of decoding the MPEG audio bitstream and encoding/decoding the voice signal in the digital voice recording

applications. The DSP operates according to the instructions stored in the embedded instruction ROM’s, working SRAM buffers are also

built in. The DSP reacts to the commands by the system MCU and reflects the processing status for the MCU to monitor.

© Sunplus Technology Co., Ltd. 10 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

! CDDSP interface
The CD Interface receives audio data from CD-kit. This interface consists of 4 signals, CD_C2PO, CD_LRCK, CD_BCK and CD_DATA.

The signal format of the CD Interface is programmable with DSP control register 0x3fD8.

Register Name Reg # Bits Description (Value set at initialization)

CD_CONFIG 0x3FD8 16 Sets Mode for reading CD input (R/W) (0x0843)

bit 0 = BCLK active edge (0 = falling, 1 = rising)

bit 1 = DATA LSB / MSB sent first
bit 2 = DATA Left / Right justify in container
bit 3 = CD data delayed w.r.t. LRCK
bit 4 = LRCK polarity
bit 5 = LRCK Pulse / Non-pulse mode
bit 6 = C2P0 Error location
bits 9:7 = Set data size from 16 to 24 bits
bits 12:11 = Set container size as either
16, 24 or 32 bits
bit 13 = CD raw data
bit 14 = CD swap byte
(0 = LSB first, 1 = MSB first)
(0 = right, 1 = left)
(0 = no delay, 1 = delay (I2S))
(0 =LRCK low is left, 1 =LRCK low is right)
(0 = non-pulse, 1 = pulse mode)
(0 = LSB error first, 1 = MSB error first)
000-16, 001-17, 010-18, 011-19,
100-20, 101-21, 110-22, 111-24
00-16, 01-24, 10-32
(0 =enable, 1= disable descramble & CRC)
(1 = swap bytes from CD before writing SRAM)

(Sony, Sanyo :0x0843, Philips :0x0043,

Panasonic: 0x1043, Toshiba: 0x0003)

! SDRAM control interface

The SPCA758A uses its SDRAM memory interface to exchange data with external SDRAM. The SDRAM could be used to buffer up to

1000 seconds of MPEG bitstream for CD shockproof. 1MX16, 4MX16 and 8MX16 SDRAM’s are supported. The clock frequency of the

SDRAM (pin 18 DRAMCLK ) is no more than 50MHz

! DSM ADC
The audio-band sigma-delta analog-to-digital converter suits the digital recorder application; it is 8KHz-sampling rate with 10-bit resolution.

The analog-to-digital conversion chain consists of an auto level control (ALC), microphone amplifier (M.A.), programmable gain amplifier

(PGA), analog oversampled modulator, and the decimation digital filter. The ALC is a limiter to limit the amplitude of microphone amplifier’

output. When we select the PGA gain, we must select the ALC level appropriate for the PGA gain. The PGA has gain step from 3dB to

18dB (3, 6, 9, 12, 15 & 18dB). The modulator is a sigma-delta feedback loop, which oversamples the signal at 1.024MHz and provides

second-order noise shaping. It performs the conversion of differential analog input signals to a pulse-density-modulated single-bit digital

output. When a maximum positive differential input voltage is applied at the input of the modulator, the resulting code at the output of the

modulator is all ones. The decimation digital filter consists of a comb filter and a half-band filter. The comb filter is a third-order comb

filter. Finally the encoder implements the half-band filter and data compression by using software.

! SAR ADC
The 3-channel ADC can sample analog inputs and transform it into 8-bit digital information to fit various applications, such as

remote control, voltage detection, etc.

© Sunplus Technology Co., Ltd. 11 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

! PCM Interface
The PCM Interface arranges the decoded audio data with specific formats to output to external audio DAC. There are 4 signals,

AUD_XCK, AUD_LRCK, AUD_BCK and AUD_DATA. The signal format of the PCM Interface is programmable to meet the requirements

of various DAC’s. The SPCA758A supports sampling rates (Fs, AUD_LRCK) of 32K, 44.1K and 48KHz, and AUD_BCK may be Fs*32 or

Fs*48. Some typical audio DAC formats are shown below:

Normal Mode:

AUD_BCK
AUD_LRCK
AUD_DATA 0 15 14 1 0 15 14 1 0 15 14

BCK = 32 x Fs

AUD_BCK
AUD_LRCK
AUD_DATA 0 15 14 1 0 15 14 1 0 15

BCK = 48 x Fs

I2S Mode:

AUD_BCK
AUD_LRCK
AUD_DATA 1 0 15 14 1 0 15 14 1 0 15

BCK = 32 x Fs

AUD_BCK
AUD_LRCK
AUD_DATA 0 1514 0 1514 0 1514

BCK = 48 x Fs

Figure 5-1: PCM Interface clocking modes and waveform

! PLL
The SPCA758A has two PLL’s built-in. To use the PLL’s, no other components are needed externally, except power supply. An

independent analog power is applied through pin 62 VSSPLL and pin 63 VDDPLL to supply power for the system PLL, which synthesizes

the overall system clocks. Another audio PLL, capable of providing the bit clock, frame clock and oversampling clock to the external DAC,

is powered through pin 63 VDDPLL and pin 64 VSSAUD. The clocks for the ADC's are also rooted from this audio PLL. Both PLL’s use

an input crystal clock ( pin 66 XTALIN ) as their reference clock. Possible choices of the reference clock include 6,12,24 MHz and

© Sunplus Technology Co., Ltd. 12 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

16.9344, 33.8688MHz.

6. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage VDD 0.0 ~ 3.6 V
Input Voltage VIN - 0.3 ~ VDD + 0.3 V
Operating Temperature TA 0 ~ 70 ºC
Storage Temperature TSTG -55 ~ 125 ºC

DC ELECTRICAL CHARACTERISTICS (TA = 25ºC, VDD = 3.3 V)

PARAMETER CONDITION MIN. TYP. MAX.

VDD IO Supply Voltage 3.0V 3.3V 3.6V
Vdd Digital Core Supply Voltage 2.3V 2.5V 2.7V
VDDadc ADC Supply Voltage 3.0V 3.3V 3.6V
VDDpll PLL Supply Voltage 2.3V 2.5V 2.7V
VIL Input Low Voltage 0.2VDD
VIH Input High Voltage 0.8VDD
VOH Output High Voltage IOH = -4mA 2.4V VDD
VOL Output Low Voltage IOL = 4mA 0.3V 0.6V
IDD IO Power Supply Current TBD
Idd Digital Core Power Supply Current TBD
IDDadc ADC Power Supply Current 2.7mA 3.0mA 3.3mA
IDDpll PLL Power Supply Current 1.6mA 1.8mA 2.0mA

ADC ELECTRICAL CHARACTERISTICS (TA = 25ºC, VDD = 3.3 V)

PARAMETER CONDITION MIN. TYP. MAX. UNIT

AMPO: MA gain = 0dB,
Input Voltage PGA gain = 6dB 0.5*VDD Vpp
ALC:
Limit voltage SA[1:0]=(0,0) 1.37 V
SA[1:0]=(0,1) 1.68 V
SA[1:0]=(1,X) 2.16 V
PGA: Default: 6dB
Gain Range 3 18 dB
Step Size 3 dB
Step Variation 0.3 dB
Voltage reference: (CMB)
Output voltage 0.36*VDD 0.4*VDD 0.44*VDD dB

© Sunplus Technology Co., Ltd. 13 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

ADC PATH CHARACTERISTICS

PARAMETER CONDITION MIN. TYP. MAX. UNIT

ADC: FIN = 1kHz,
PGA gain = 3dB
Signal to noise + distortion ratio (SNDR) 60 dB
AMPO is full swing
Without data compression

7. ADC APPLICATION CIRCUIT

AGC

MIC
470kΩ
POWER 4.7μF

1k Ω AVSS

10kΩ 0.01μF
MICP

220μF M
Microphone 0.01μF
MICN ALC

AVSS
10μF

0.1μF
Reference
AVSS
CMB Generator
1μF
MICO
Microphone
P.G.A.
Amplifier
A.D
AMPI
Converter
51kΩ 100kΩ (3,6,9,12,15
AMPO
&18dB)
390pF

Figure 7-1: Reference Circuit using ADC

© Sunplus Technology Co., Ltd. 14 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

8. PACKAGE INFORMATION
LQFP 128L Outline Dimensions

D
D1
D2

e
E E1 E2

A2 A1 A
L1

Symbol Min. Nom. Max.

D - 16 -
D1 - 14 -
D2 - 12.4 -
E - 16 -
E1 - 14 -
E2 - 12.4 -
e - 0.4 -
b 0.13 0.16 0.23
A - - 1.60
A1 0.05 - 0.15
A2 1.35 1.40 1.45
c 0.09 - 0.20
L1 - 1.0 -
Unit: millimeter

© Sunplus Technology Co., Ltd. 15 2002/12/5

Proprietary & Confidential Version: 0.1
 Draft
CD-Based MPEG Audio Decoder SPCA758A

REVISION HISTORY

Date Revision # Description Page

Oct. 15, 2002 0.1.0 First draft

DISCLAIMER

The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by
the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory
implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent
infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described
herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g.
military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for
such applications. Please note that application circuits illustrated in this document are for reference purposes only.

© Sunplus Technology Co., Ltd. 16 2002/12/5

Proprietary & Confidential Version: 0.1