TVS Diodes

Transient Voltage Suppressor Diodes

ESD3V3U4ULC
Ultra-low Capacitance ESD / Transient Protection Array

ESD3V3U4ULC

Data Sheet
Rev. 1.2, 2012-07-03 Final

Power Management & Multimarket

Edition 2012-07-03 Published by Infineon Technologies AG 81726 Munich, Germany 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

ESD3V3U4ULC

Revision History Revision 1.1, 2012-04-18 Page or Item 7 Subjects (major changes since previous revision) Figure 1 Rev. 1.2, 2012-07-03

Trademarks of Infineon Technologies AG AURIX, BlueMoon, COMNEON, C166, CROSSAVE, CanPAK, CIPOS, CoolMOS, CoolSET, CORECONTROL, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, EUPEC, FCOS, HITFET, HybridPACK, ISOFACE, IRF, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OptiMOS, ORIGA, PROFET, PRO-SIL, PRIMARION, PrimePACK, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SMARTi, SmartLEWIS, TEMPFET, thinQ!, TriCore, TRENCHSTOP, X-GOLD, XMM, X-PMU, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, PRIMECELL, REALVIEW, THUMB of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. muRata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Sattelite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update 2010-06-09

Final Data Sheet

Rev. 1.2, 2012-07-03

ESD3V3U4ULC

Ultra-low Capacitance ESD / Transient Protection Array

Ultra-low Capacitance ESD / Transient Protection Array

1.1

Features

ESD / transient protection of high speed data lines exceeding : IEC61000-4-2 (ESD) : 20 kV (air/contact) IEC61000-4-4 (EFT) : 2.5 kV (5/50ns) IEC61000-4-5 (Surge) : 3 A (8/20s) Maximum working voltage: VRWM = 3.3 V Ultra low capacitance CL = 0.4 pF I/O to GND (typical) Very low clamping voltage: VCL = 8 V at IPP = 16 A (typical) Very low dynamic resistance: RDYN = 0.19 (typical) TSLP-9-1 package with pad pitch 0.5 mm, optimized pad design to simplify PCB layout Pb-free and halogen free package (RoHS compliant)

1.2

Application Examples

USB 3.0, 10/100/1000 Ethernet, Firewire DVI, HDMI, S-ATA, DisplayPort Mobile HDMI Link, MDDI, MIPI, etc.

Product Description

Pin 9

Pin 8

Pin 7

Pin 6

Pin 1
I/O

Pin 2
I/O

Pin 4
I/O

Pin 5
I/O

GND

Pin 1

Pin 2

Pin 3

Pin 4

Pin 5

Pin 3 b) Schematic diagram

a) Pin configuration
Figure 1 Table 1 Type ESD3V3U4ULC Pin Configuration and Schematic Diagram Ordering Information Package TSLP-9-1 Configuration 4 lines, uni-directional

Marking code Z2

Final Data Sheet

Rev. 1.2, 2012-07-03

ESD3V3U4ULC

Characteristics

Characteristics

Table 2 Parameter

Maximum Rating at TA = 25 C, unless otherwise specified Symbol Min.

1) 2)

Values Typ. Max. 20 3 125 150 -40 -65

Unit kV A C C

ESD contact discharge Operating temperature

VESD IPP TOP Tstg

Peak pulse current (tp = 8/20 s)

Storage temperature 1)VESD according to IEC61000-4-2 2) IPP according to IEC61000-4-5

3.1

Electrical Characteristics at TA = 25 C, unless otherwise specified

VF IF VR IR

Forward voltage Forward current Reverse voltage Reverse current I PP

IF

RDYN V Trig VCL RDYN VHold V RWM

Dynamic resistance Triggering reverse voltage Clamping voltage Holding reverse voltage Reverse working voltage maximum Forward clamping voltage Triggering reverse current Holding reverse current Peak pulse current Reverse working current maximum

VTrig VR VCL

VHold

VRWM IRWM ITrig IHold VFC VF

VFC ITrig IHold IPP IRWM -I PP IR

RDYN

Diode_Charac teris tic _Curv e_with _s napbac k _Uni-direc tional .v s d

Figure 2 Table 3 Parameter

Definitions of electrical characteristics[1] DC Characteristics at TA = 25 C, unless otherwise specified Symbol Min. 1 Values Typ. Max. 3.3 50 V nA Unit Note / Test Condition I/O to GND

Reverse working voltage VRWM Reverse current

IR

VR = 3.3 V, I/O to GND

Final Data Sheet

Rev. 1.2, 2012-07-03

ESD3V3U4ULC

Characteristics

Table 4 Parameter

RF Characteristics at TA = 25 C, unless otherwise specified Symbol Min.

1)

Values Typ. 0.4 0.2 0.035 Max. 0.65 0.35

Unit pF pF pF

Note / Test Condition

Line capacitance

CL

VR = 0 V, f = 1 MHz, I/O to GND VR = 0 V, f = 1 MHz,

I/O to I/O

Channel capacitance matching between I/O to GND Channel capacitance matching between I/O to I/O

Ci/o-GND

VR = 0 V, f = 1 MHz, I/O to GND VR = 0 V, f = 1 MHz,

I/O to I/O

Ci/o-i/o

0.017

pF

1) Total capacitance line to ground

Table 5 Parameter

ESD Characteristics at TA = 25 C, unless otherwise specified Symbol Min.

1)

Values Typ. 8 11 6 9 0.19 0.23 Max.

Unit V V V V

Note / Test Condition

Clamping voltage [2]

VCL

IPP = 16 A, from I/O to GND IPP = 30 A, from I/O to GND IPP = 16 A, from GND to I/O IPP = 30 A, from GND to I/O
I/O to GND GND to I/O

Forward clamping voltage1) [2]

VFC

Dynamic resistance1) [2]

RDYN

1) Please refer to Application Note AN210. TLP parameter: Z0 = 50 , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between IPP1 = 10 A and IPP2 = 40 A.

Final Data Sheet

Rev. 1.2, 2012-07-03

ESD3V3U4ULC

Characteristics

3.2

Typical Characteristics at TA = 25 C, unless otherwise specified

10 10

-7

-8

IR [A]

10-9 10-10 10 10
-11

-12

2 VR [V]

Figure 3

Reverse curent, IR = (VR)

10

-6

10-7 IR [A]

10

-8

10

-9

25

50

75 TA [C]

100

125

150

Figure 4

Reverse current: IR = f(TA), VR = 3.3 V 7 Rev. 1.2, 2012-07-03

Final Data Sheet

ESD3V3U4ULC

Characteristics

0.8 0.7 0.6 CL [pF] 0.5 0.4 0.3 0.2

1MHz 1GHz

0.5

1.5 2 VR [V]

2.5

3.5

Figure 5

Line capacitance: CL = f(VR), f = 1MHz, from I/O to GND

50 40 30 20 10 0

ESD3V3U4ULC RDYN RDYN=0.19

25 20 15 10 5 0

10 VTLP [V]

15

20

Figure 6

Clamping voltage VTLP = f(ITLP), from I/O to GND Note: [2]

Final Data Sheet

Rev. 1.2, 2012-07-03

Equivalent VIEC [kV]

ITLP [A]

ESD3V3U4ULC

Characteristics

50 40 30 20 10 0

ESD3V3U4ULC RDYN RDYN=0.23

25 20 15 10 5 0

10 VTLP [V]

15

20

Figure 7

Forward clamping voltage VTLP = f(ITLP), from GND to I/O Note: [2]

Note: TLP parameter: Z0 = 50 , tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between IPP1 = 10 A and IPP2 = 40 A. The equivalent stress level VIEC according IEC 61000-4-2 (R = 330 , C = 150 pF) is calculated at the broad peak of the IEC waveform at t = 30 ns with 2 A / kV

Final Data Sheet

Rev. 1.2, 2012-07-03

Equivalent VIEC [kV]

ITLP [A]

ESD3V3U4ULC

Application Information

Application Information

To design USB3.0 link for best system level ESD performance and error free Signal Integrity is mandatory. To bring both requirements together, the ESD protection devices has to provide excellent ESD and a very low device capacitance. The Infineon ESD3V3U4ULC in array configuration, combined with a clear and straight forward full through layout fulfills these requirements in the best way.

TVS ESD diodes

TX+ SuperSpeed Data IN + TXUSB3.0: SS-Hub e.g. PC TXmated connector RX+ SuperSpeed Data OUT + RX+ RXUSB3.0 cable SS transmission channel TXmated connector RX+ TXRXRXUSB3.0: SS-Device e.g. storage TX+ TX+ RX+ RX+ SuperSpeed Data OUT

TX+ + SuperSpeed Data IN

TVS ESD diodes

Figure 8

USB3.0 structure with ESD protection devices [3]

Final Data Sheet

10

Rev. 1.2, 2012-07-03

ESD3V3U4ULC

Ordering Information Scheme

Ordering Information Scheme

ESD

0P1

RF

- XX YY
Package XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP For R adio Frequency Applications Line Capacitance C L in pF: (i.e.: 0P1 = 0.1pF)

ESD 5V3 U n U - XX YY
Package or Application XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP S = SOT363 U = SC74 XX = Application family: LC = Low Clamp HDMI U ni- / B i-directional or R ail to Rail protection N umber of protected lines (i.e.: 1 = 1 line; 4 = 4 lines) Capacitance: Standard (>10pF), Low (<10pF), U ltra-low (<1pF) Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V)
Figure 9 Ordering information scheme

Final Data Sheet

11

Rev. 1.2, 2012-07-03

ESD3V3U4ULC

Package Information

Package Information

6.1

TSLP-9-1 (mm)

Top view
0.31+0.01 -0.02 0.05 MAX.

Bottom view
(0.03)
(0.05)

0.59
5 6

8 x 0.2 0.025 1)
0.3 0.2 0.3 0.3 0.2

10.035

0.05 A B

4 x 0.5 = 2

0.4 0.025 1)

0.5

4 3 2

0.94 0.025 1)
8

0.05 A B

0.05 A B

Pin 1 marking
0.05 A B

8 x 0.35 0.025 1)

1) Dimension applies to plated terminals

Figure 10

TSLP-9-1: Package overview

1
0.2

1
0.2

0.3

0.3

0.2

2.3

0.2

0.3

2.3

0.2

0.3

0.3

0.38 0.38 0.24

0.38 0.38 0.24

Copper

Solder mask

Stencil apertures
TSLP-9-1-FP V01

Figure 11

TSLP-9-1: Footprint
4 0.5

2.3

Pin 1 marking

1.6
TSLP-9-1-TP V03

Figure 12

TSLP-9-1: Packing

1234567

Type code Data code (YYWW)

Pin 1 marking
TSLP-9-1-MK V02

Figure 13

TSLP-9-1: Marking

Final Data Sheet

12

0.3

0.2

0.3

2.3 0.035
TSLP-9-1-PO V02

Rev. 1.2, 2012-07-03

ESD3V3U4ULC

References

References
[1] [2] [3] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN:0-7923-7647-1 Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology Infineon Technologie AG - Application Note AN240: Effective ESD Protection for USB3.0, combined with perfect Signal Intergrity.

Final Data Sheet

13

Rev. 1.2, 2012-07-03

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG