VHDL Fundamentals

Roveena Rebello NITK, Surathkal

1 Bit Equality Comparator

library ieee; use ieee.std_logic_1164.all; entity compare1 is port(A,B: in std_logic; AeqB: out std_logic); end compare1; architecture behavior of compare1 is begin process(A,B) begin AeqB<=0; if A=B then AeqB<=1; end if; end process; end behavior;
Inputs A 0 0 1 B 0 1 0 Output AeqB 1 0 0

If the default assignment statement is removed:

process(A,B) begin if A=B then AeqB<=1; end if; end process; Implied memory: remember or store the value

E.g.: Heater Thermostat

entity thermostat is port(desired_temp, actual_temp: in integer; heater_on: out boolean); end entity; architecture temp of thermostat is begin controller: process(desired_temp, actual_temp) begin if actual_temp<(desired_temp-2) then heater_on<=true; elsif actual_temp>(desired_temp+2) then heater_on<=false; end if; end process; end temp;

 If behavior is to depend on the value of a single expression, we can use case statement General form: CASE expression IS WHEN constant_value1=> statement1; WHEN constant_value2=> statement1; WHEN OTHERS=> statement3; END CASE;

CASE Statement

8:1 Multiplexer using case staement

library ieee; use ieee.std_logic_1164.all; entity mux8 is port(X: in std_logic_vector(7 downto 0); sel: in bit_vector(1 downto 0); y: out std_logic); end mux8; architecture multiplexer of mux8 is begin process(X,sel) begin case sel is when 000=> y<=X(0); when 001=> y<=X(1); when 010=> y<=X(2); when 011=> y<=X(3); when 100=> y<=X(4); when 101=> y<=X(5); when 110=> y<=X(6); when 111=> y<=X(7); end case; end process; end multiplexer;

3 to 8 decoder using case statement

library ieee; use ieee.std_logic_1164.all; entity decoder1 is port(a: in integer range 0 to 7; y: out std_logic_vector(7 downto 0)); end dec3to8; architecture dec3to8 of decoder1 is begin process(a) begin case a is when 0=> y<=00000001; when 1=> y <=00000010; when 2=> y <=00000100; when 3=> y <=00001000; when 4=> y <=00010000; when 5=> y <=00100000; when 6=> y <=01000000; when 7=> y <=10000000; end case; end process; end dec3to8;

3-8 decoder
library ieee; use ieee.std_logic_1164.all; entity decoder2 is port(a: in integer range 0 to 7; y: out std_logic_vector(7 downto 0)); end decoder2; architecture dec3to8 of decoder2 is begin process(a) begin y<="00000000"; y(a)<='1'; end process; end dec3to8;

WAIT Statement
process cannot have sensititvity list when WAIT statement is employed 3 types: 1.syntax (WAIT UNTIL) WAIT UNTIL signal_condition ; E.g.: WAIT UNTIL A=B; WAIT UNTIL clkevent and clk=1; 2. syntax (WAIT ON) WAIT ON signal1,signal2,; E.g.: WAIT ON clk,rst; 3. syntax (WAIT FOR) WAIT FOR time_expression; E.g.: WAIT FOR 5ns;

Possible modes for signals that are entity ports

Mode
IN OUT

Purpose
Used for a signal that is an input to an entity Used for a signal that is an output from an entity. The value of the signal cannot be used inside the entity. This means that in an assignment statement, the signal can appear only to the left of the <= operator Used for a signal that is both an input to an entity and an output from the entity Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement, the signal can appear both on the left and right sides of the <= operator

INOUT

BUFFER

Entity with GENERICS

Using generate statement: instantiate 4 copies of 1-bit adder To make the code more general we can use GENERIC statement

E.g.: n-bit full adder

library ieee; use ieee.std_logic_1164.all; entity fulladd is port(Cin,x,y: in std_logic; Sum, Cout: out std_logic); end fulladd; architecture logic_func of fulladd is begin Sum<= x xor y xor Cin; Cout<=(x and y) or (y and Cin) or (Cin and x); end logic_func;

library ieee; use ieee.std_logic_1164.all; entity adder_n is generic(n: integer:=4); port(Cin: in std_logic; X, Y:in std_logic_vector(n-1 downto 0); S: out std_logic_vector(n-1 downto 0); Cout: out std_logic); end adder_n; architecture structure of adder_n is component fulladd port(Cin,x,y: in std_logic; Sum, Cout: out std_logic); end component; signal c: std_logic_vector(0 to n); begin c(0)<=Cin; Add: for i in 0 to n-1 generate Add_n: fulladd port map(C(i),X(i), Y(i), S(i), C(i+1)); end generate; Cout<=C(n); end structure;

8:1 multiplexer using generic statement

library ieee; use ieee.std_logic_1164.all; entity mux_m is generic(m: integer:=8); port(X:in std_logic_vector(m-1 downto 0); sel: in integer range 0 to m-1; y: out std_logic); end mux_m; architecture structure of mux_m is begin process(sel,X) begin y<=X(sel); end process; end structure;

16:1 multiplexer using generic statement

library ieee; use ieee.std_logic_1164.all; entity mux_m is generic(m: integer:=16); port(X:in std_logic_vector(m-1 downto 0); sel: in integer range 0 to m-1; y: out std_logic); end mux_m; architecture structure of mux_m is begin process(sel,X) begin y<=X(sel); end process; end structure;

Propagation Delay
E.g.: C<= A and B after 5ns; E<= C or D after 5ns; Concurrent: Statements evaluated any time a signal on the right side of assignment operator changes

Creating waveform
E.g.: CLK<= not CLK after 10ns; Generates a clock waveform with a period of 20ns

Variables, Signals and Constants

Variables: Used for local storage in processes, procedures and functions variable list_of_variable_names: type_name [:= initial_value]; Must be declared within the process in which they are used They are local to that process
Signals: Must be declared outside of a process Signals declared at the start of an architecture can be used anywhere within that architecture signal list_of_signal_names: type_name [:= initial_value];

Constants: constant constant _name: type_name:= constant _value; Constants declared at the start of an architecture can be used anywhere within that architecture Constants declared within a process are local to that process
Signal updation using signal assignment statement: signal _name:= expression [after dealy]; Signal is scheduled to change after the delay If no delay specified then the signal is scheduled to be updated after a delta delay Variable updation using variable assignment statement: variable_name:= expression; Variable is instantaneously updated with no delay, not even a delta delay

Process using variables

entity test1 is end test1;
architecture var of test is signal trigger, sum: integer:=0; begin process variable var1: integer:=1; variable var2: integer:=2; variable var3: integer:=3; begin wait on trigger; var1:= var2+var3; var2:= var1; var3:= var2; sum<=var1+var2+var3; end process; end var;

If trigger changes at time t=10, var1,var2, var3 are updated instantly and sum computed with new variable values

var1=2+3 var2=5 var3=5 sum=5+5+5=15 at time 10+delta since sum is a signal

Process using signals

entity test2 is end test2;
architecture sig of test is signal trigger, sum: integer:=0; signal sig1: integer:=1; signal sig2: integer:=2; signal sig3: integer:=3; begin process begin wait on trigger; sig1:= sig2+sig3; sig2:= sig1; sig3:= sig2; sum<=sig1+sig2+sig3; end process; end sig; If trigger changes at time t=10, sig1, sig2, sig3 and sum are computed at time= 10, but the signals are not updated until time 10+delta. Old values of sig1 and sig2 are used to compute sig2 and sig3

At time= 10+delta, sig1=5 sig2=1 sig3=2 sum=5+1+2=6

Arrays
First declare an array type and then declare an array object type SHORT_WORD is array(15 downto 0) of bit Declares an array of type SHORT_WORD having an integer index with a range from 15 downto 0 with each element in the array of type bit signal data_word:SHORT_WORD; variable alt_word: SHORT_WORD:=0101010101010101; constant one_word: SHORT_WORD:= (others=>1); Can access each bit of the array E.g.: alt_word(0) Can specify a portion of the array E.g.: alt_word(5 downto 0) General form for array type and array object declaration:
type array_type_name is array index_range of element_type; signal array_name: array_type_name [:=initial_value];

 Two-dimensional arrays type matrix4x3 is array (1 to 4, 1 to 3) of integer;

variable matrixA: matrix4x3:=((1,2,3),(4,5,6),(7,8,9),(10,11,12));

1 2 3 4 5 6 7 8 9 10 11 12 matrixA(3,2) refers to the element in 3rd row and 2nd column Unconstrained array type: Dimension of the array may be undefined
type intvec is array(natural range <> ) of integer

matrixA initialised to

Range must be specified when the array object is declared

signal intvec5: intvec(1 to 5) := (3,2,6,8,1);

 Two-dimensional array with unconstrained row and column index range type matrix is array( natural range <>, natural range <>) of integer;

Prime Number Detector

Dataflow model Structural model Behavioral model

Prime Number Detector using selected signal assignment (N is 4 bits)

entity prime is port(N: in std_logic_vector(7 downto 0); y: out std_logic); end prime; architecture detector of prime is begin with N select y <= 1 when 0001| 0010| 0011| 0101| 1011| 1101, 0 when others; end detector;

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