Switching Circuits & Logic Design

Jie-Hong Roland Jiang Department of Electrical Engineering National Taiwan University Fall 2009
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18 Circuits for Arithmetic Operations

http://www.nature.com/nature/journal/v414/n6866/fig_tab/414883a_F1.html

Outline
How to use a sequential circuit to control a sequence of operations in a digital system Serial adder with accumulator Design of a parallel multiplier

Serial Adder with Accumulator Operation

4-bit example
x3 x2 x1 x0 s0 x3 x2 x1 s1 s0 x3 x2

y3

y2

y1

y0

Full Adder

s0 c1

y0

y3

y2

y1

Full Adder

s1 c2

y1

y0

y3

y2

Full Adder

s2 c3

c0=0

c1

c2

(a) At time t0

(b) At time t1
final sum

(c) At time t2

s2

s1

s0

x3

y2

y1

y0

y3

Full Adder

s3 c4

s3

s2

s1

s0

y3

y2

y1

y0

Full Adder

unused unused

c3

c4

(d) At time t3

(e) At time t4

Clear D F/F before next use 4

Serial Adder with Accumulator Operation

4-bit example
X t0 t1 t2 t3 t4 0101 +0111 1100 Y Ci 0 1 1 1 0 Si 0 0 1 1 Ci+ 1 1 1 0 Si
Full Adder

(x3x2x1x0) (y3y2y1y0)

0101 0111 0010 1011 0001 1101 1000 1110 1100 0111

X/S

(1) (0)

Y
Ci

Ci+

Serial Adder with Accumulator

Block diagram
Accumulator St (start signal)
SI Sh

x3

x2

x1

x0

xi

si

Control Sh Circuit

SI Sh

y3

y2

y1

y0

yi ci

Full Adder
ci+1

Addend Register (cyclic shift) Clock Serial Adder

Q Q'

D CK CE

SI: serial input St: start signal Sh: shift signal

control signals
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Serial Adder with Accumulator Control Circuit Design

State graph and state table
St'/0

-/Sh

S0

St/Sh

Next State St = 0 S0 S1 S2 S3 S0 S2 S3 S0 1 S1 S2 S3 S0 0 1 1 1

Sh St = 0 1 1 1 1 1

S3
-/Sh

S1 S2
-/Sh

Shift 4 times after St is activated

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Serial Adder with Accumulator Control Circuit Design

Derivation of control circuit equations
Transition table
AB S0 S1 S2 S3 00 01 10 11 A+B+ St = 0 00 10 11 00 1 01 10 11 00 St 0 AB 00 0 01 1 11 0 10 1 A+ DA=A'B+AB' =AB St 0 AB 00 0 01 0 11 0 10 1 St 0 AB 00 0 01 1 11 1 10 1

1 0 1 0 1

1 1 0 0 1 B+

1 1 1 1 1 Sh

State Assignment

DB=StB'+AB'

Sh=St+A+B

Serial Adder with Accumulator Typical Serial Processing Unit

Typical serial processing unit with n-bit shift registers
Sh St

Shift Register Combinational Circuit Shift Register

Control

If St is 1 for only one clock time St resets to 0 automatically

If St remains 1 until after the shifting is completed Make sure St resets to 0 before next start
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Design of a Parallel Multiplier

Design a parallel adder for positive binary numbers
Require only shifting and adding Add two binary numbers at a time
Multiplicand Multiplier 1101 1011 1101 11010 100111 000000 100111 1101000 10001111 (13) (11)

Partial Products

Product

(143)
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Design of a Parallel Multiplier Parallel Binary Multiplier

Block diagram
Load Ad Sh

Product (8 bits) ACC (8+1 bits)

C O N T R O L

Shift direction

Clk
Done St M

C4

4-Bit Adder

Multiplier (initial storage)

Product and multiplier share registers

Multiplicand

Load: load multiplier to ACC[0:3] and clear ACC[4:8] Ad: add signal (to store adder outputs in ACC[4:7] and C4 in ACC[8]) Sh: shift the ACC contents one place to the right M: current multiplier bit

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Design of a Parallel Multiplier Parallel Binary Multiplier

Operation example
{product, multiplier} 0 1 1 M (11) (13) 000 011 1 0 1 M initial contents of product register 0 0 0 0 0 1 (add multiplicand because M = 1) 11010 after addition 011011 after shift 001101 (add multiplicand because M = 1) after addition after shift (skip addition because M = 0) after shift (add multiplicand because M = 1) after addition after shift (final answer) 0 0 1 0 0 1 1 1 1 M 11010000 100011111 010001111 (143)
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11010000 100111101 0 1 0 0 1 1 1 1 0 M

Dividing line between product and multiplier

Design of a Parallel Multiplier Control Circuit Design

Method 1 (direct implementation)
Load Ad Sh
initial state

C O N T R O L

Done St M

Repeating 1-bit multiplication: S1S2: M=1, add S2S3: right shift S1S3: M=0, right shift without adding
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Design of a Parallel Multiplier Control Circuit Design

Method 2 (use counter, fewer states)
Introduce signal K for counting completion
1-bit multiplication

St M Clk

Add-Shift Control K Counter

Done Load Ad Sh

KM': MSB of multiplier is 0, shift and goto S3 K: addition finished for MSB, shift and goto S3

How many states in total (including add-shift control and counter)?

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Design of a Parallel Multiplier Control Circuit Design

Method 2 (contd)
Operation example for 11011011
Time t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 State S0 S0 S1 S2 S1 S2 S1 S1 S2 S3 Counter 00 00 00 00 01 01 10 11 11 00 Product Register 000000000 000000000 000001011 011011011 001101101 100111101 010011110 001001111 100011111 010001111 St 0 1 0 0 0 0 0 0 0 0 M 0 0 1 1 1 1 0 1 1 1 K 0 0 0 0 0 0 0 1 1 0 Load 0 1 0 0 0 0 0 0 0 0 Ad 0 0 1 0 1 0 0 1 0 0 Sh 0 0 0 1 0 1 1 0 1 0 Done 0 0 0 0 0 0 0 0 0 1
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