DSD LAB MANUAL

Experiment No.:1 Aim: To design all gates using VHDL. Software Required: Active HDL VHDL Code:1) VHDL code for AND gate
library ieee; use ieee.std_logic_1164.all; entity gate_and is port (a, b: in std_logic; z : out std_logic); end gate_and; architecture archi of gate_and is begin process (a, b, z) begin if a=0 and b=0then z <=0 ; elsif a=0 and b=1then z <=0 ; elsif (a=1 and b=0then z <=0 ; else a=1 and b=1then z <=1 ; end if; end process; end archi;

2) VHDL Code for OR gate: library ieee; use ieee.std_logic_1164.all; entity gate_or is

port (a, b: in std_logic; z : out std_logic); end gate_or; architecture archi of gate_or is begin process (a, b, z) begin if a=0 and b=0then z <=0 ; elsif a=0 and b=1then z <=1 ; elsif (a=1 and b=0then z <=1 ; else a=1 and b=1then z <=1 ; end if; end process; end archi; 3) VHDL code for NAND gate: library ieee; use ieee.std_logic_1164.all; entity gate_nand is port (a, b: in std_logic; z : out std_logic); end gate_nand; architecture archi of gate_nand is begin process (a, b, z) begin if a=0 and b=0then z <=1 ; elsif a=0 and b=1then z <=1 ;

elsif (a=1 and b=0then z <=1 ; else a=1 and b=1then z <=0 ; end if; end process; end archi; 4)VHDL code for NOR gate: library ieee; use ieee.std_logic_1164.all; entity gate_nor is port (a, b: in std_logic; z : out std_logic); end gate_nor; architecture archi of gate_nor is begin process (a, b, z) begin if a=0 and b=0then z <=1 ; elsif a=0 and b=1then z <=0 ; elsif (a=1 and b=0then z <=0 ; else a=1 and b=1then z <=0 ; end if; end process; end archi; Result: Designing of AND, OR, NAND and NOR gates has been done.

Experiment No.:2 Aim: To design the following circuit and check the waveforms using VHDL. a) Half Adder b) Full Adder Software Required: Active HDL VHDL CODE for HALF ADDER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end half_adder; architecture Behavioral of half_adder is begin sum <= a xor b ; carry <= a and b; end Behavioral;

2) VHDL CODE for Full ADDER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder is

Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end half_adder; architecture Behavioral of half_adder is begin sum <= a xor b xor c; carry <= (a and b) or (b and c) or (c and a); end Behavioral;

Experiment No.:3 Aim: To design the following circuit and check the waveforms using VHDL. a) Half Subtractor b) Full Subtractor Software Required: Active HDL VHDL CODE for HALF subtractor: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_sub is Port ( a : in std_logic; b : in std_logic; diff : out std_logic; borrow : out std_logic); end half_sub; architecture Behavioral of half_sub is begin diff <= a xor b ; borrow <= a and (not b); end Behavioral; 2) VHDL CODE for Full subtractor: library ieee; use ieee.std_logic_1164.all; entity flsub_select is port(a:in bit_vector(2 downto 0); s:out bit_vector(1 downto 0));

end flsub_select; architecture beh of flsub_select is begin with a select s<=("00") when "000", ("11") when "001", ("11") when "010", ("01") when "011", ("10") when "100", ("00") when "101", ("00") when "110", ("11") when "111"; end beh;

Experiment No.:4 Aim: Write VHDL code for multiplexer and check the waveforms. Software required: Active HDL VHDL code for 4x1 mux:
library ieee; use ieee.std_logic_1164.all; entity mux is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_logic); end mux; architecture archi of mux is begin process (a, b, c, d, s) begin if (s = "00") then o <= a; elsif (s = "01") then o <= b; elsif (s = "10") then o <= c; else o <= d; end if; end process; end archi;

Experiment No.:5 Aim: Write VHDL code for Demultiplexer and check the waveforms. Software required: Active HDL VHDL code for 1x4 demux:

library ieee; use ieee.std_logic_1164.all; entity demux is port (I : in std_logic; s : in std_logic_vector (1 downto 0); y: out std_logic_vector(0 to 3)); end demux; architecture archi of demux is begin process (I,s) begin if(s=00)then y<=1000; elseif(s=01)then y<=0100; elseif(s=10)then y<=0010; elseif(s=01)then y<=0001; end if; end process; end archi;

Experiment No.:6 Aim: Write VHDL code for priority encoder and check the waveforms. Software required: Active HDL VHDL code for 8:3 priority encoder
library ieee; use ieee.std_logic_1164.all;

entity priority is port ( sel : in std_logic_vector (7 downto 0); code :out std_logic_vector (2 downto 0)); end priority; architecture archi of priority is begin code <= "000" when sel(0) = '1' else "001" when sel(1) = '1' else "010" when sel(2) = '1' else "011" when sel(3) = '1' else "100" when sel(4) = '1' else "101" when sel(5) = '1' else "110" when sel(6) = '1' else "111" when sel(7) = '1' else "---"; end archi;

Experiment No.:7 Aim: Write VHDL code for decoder and check the waveforms. Software required: Active HDL VHDL code for a 1-of-8 decoder.: Data flow model:
library ieee; use ieee.std_logic_1164.all;

entity dec is port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0)); end dec; architecture archi of dec is begin res <= "00000001" when sel = "000" else "00000010" when sel = "001" else "00000100" when sel = "010" else "00001000" when sel = "011" else "00010000" when sel = "100" else "00100000" when sel = "101" else "01000000" when sel = "110" else "10000000"; end archi;

Experiment No.:8 Aim: Write VHDL code for comparator and check the waveforms. Software required: Active HDL VHDL code for comparator

Behavioral model: library ieee; use ieee.std_logic_1164.all; entity comp is port (A,B: in std_logic_vector (0 to 3); agtb,aeqb,aitb: out std_logic_); end comp; architecture archi of comp is begin process(A,B) begin if(A>B)then agtb<=1; aeqb<=0; altb<=0; else if(A<B)then agtb<=0; aeqb<=0; altb<=1;

else if(A=B)then agtb<=0; aeqb<=1; altb<=0; end if; end process; end archi;

Experiment No.:9 Aim: Write VHDL code for shift register and check the waveforms. Software required: Active HDL VHDL code for Shift Register
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity test_shift is generic ( width : integer := 17 ); port ( clk : in std_ulogic; reset : in std_ulogic; load : in std_ulogic; en : in std_ulogic; inp : in std_logic_vector ( width downto 0 ); outp : out std_ulogic ); end test_shift;

architecture rtl of test_shift is signal shift_reg : unsigned ( width downto 0 ); begin

outp <= shift_reg (shift_reg'high);

shifter : process ( clk, reset ) begin

if ( reset = '0' ) then shift_reg <= (others => '0'); elsif rising_edge ( clk ) then if (load = '1' ) then shift_reg <= unsigned (inp); elsif ( en = '1' ) then shift_reg <= rotate_left ( shift_reg, 1 ); end if; end if; end process shifter;

end rtl;