Fabrication of metaloxidesemiconductor devices with extreme ultraviolet lithography

K. B. Nguyen,a) G. F. Cardinale, D. A. Tichenor, G. D. Kubiak, K. Berger, A. K. Ray-Chaudhuri, Y. Perras, S. J. Haney, R. Nissen, K. Krenz, and R. H. Stulen
Sandia National Laboratories, P.O. Box 969, MS 9409, Livermore, California 94551

H. Fujioka, C. Hu, and J. Bokor

University of California, Berkeley, Cory Hall, Berkeley, California 94720

D. M. Tennant and L. A. Fetter

Bell Laboratories/Lucent Technologies, Holmdel, New Jersey 07733 and Murray Hill, New Jersey 07974

Received 14 June 1996; accepted 30 August 1996 This article reports results from the successful fabrication of metaloxidesemiconductor MOS devices with extreme ultraviolet lithography. n -type MOS transistors with gate lengths of 0.1 m were fabricated and demonstrated good device characteristics. The alignment strategy, mask layout, mask fabrication, and device characteristics will be reported. 1996 American Vacuum Society.

I. INTRODUCTION In recent years, many studies have been carried out to explore metaloxidesemiconductor MOS device performance at 0.1 m gate length.14 In these earlier experiments, the critical gate levels were patterned by electron-beam lithography, x-ray lithography, or optical lithography with resist ashing. This article reports results from the rst successful fabrication of short-channel MOS devices with extreme ultraviolet lithography EUVL. This device fabrication experiment was performed to demonstrate both the capability of EUVL and its compatibility with MOS fabrication processes. The EUV exposures were performed with the Sandia EUVL laboratory tool, the EUVL system with a neardiffraction-limited imaging system and an overlay capability.5 In the following sections, the details of the alignment strategy, mask layout, mask fabrication, and device characteristics will be reported. II. DEVICE LAYOUT AND FABRICATION PROCESS The devices fabricated were n -type NMOS transistors and capacitors Fig. 1. Short-channel transistors with small gate length differences 0.075, 0.1, 0.11, 0.12, up to 0.18 m were included to quantify the lithographic performance achievable with the EUVL laboratory tool. The larger transistors with gate lengths of up to 20 m and the 5050 m2 capacitors were included for process monitoring. The active areas were dened by local oxidation of silicon LOCOS isolation. The threshold voltage was adjusted with a boron implantation at 30 keV 51012/cm2. Since only discrete devices were fabricated in this experiment, a blanket boron punch-through stop was used to simplify the process 80 keV, 31012/cm2. Three different gate oxide thicknesses were used in this experiment: 25, 40, and 55 . The oxide lms were grown by thermal oxidation, and their
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thicknesses measured by ellipsometry. The gate electrodes were made of 150 nm thick in situ doped n -polysilicon deposited by low-pressure chemical vapor deposition LPCVD. The gate level was patterned with EUV lithography using a trilayer resist process that is described in more detail in a later section. The lightly doped drain LDD structures were formed with 100 nm thick low-temperature oxide LTO spacers. Sourcedrain extensions were created with a low-energy arsenic implant 10 keV, 31013/cm2, and deep junctions by an arsenic implantation at 50 KeV 21015/cm2. After the sourcedrain implantations, the wafers were annealed in N2 environment at 800 C for 20 min. The contacts were dened in a 500 nm thick LTO layer with reactive ion etching RIE. After arsenic contact implantation 50 keV, 21015/cm2, an

Electronic mail: knguyen@ca.sandia.gov J. Vac. Sci. Technol. B 14(6), Nov/Dec 1996

FIG. 1. Layout of the NMOS devices fabricated with EUVL gate level patterning. The gate lengths are indicated. Each eld contains 24 devices, 23 transistors, and one 5050 m2 capacitor. 1996 American Vacuum Society 4188

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FIG. 2. Outline of the alignment procedure. a Line scans are taken of the captured alignment images to obtain the raw alignment data b. After some signal processing, the processed data c are used to obtain the error signals in x , y , rotation, and magnication. These signals are then used to drive the wafer stage to the alignment position. Magnication is adjusted with the six-axis mask stage.

additional annealing step at 800 C for 5 min was performed. The metal lines and test pads were dened in 1 m thick aluminum. Five lithography steps were used to fabricate these NMOS devices. The active areas, the EUV alignment marks, the contacts, and the metal lines and test pads were patterned with i -line lithography, while the critical gate level was patterned with EUV lithography. Since the LOCOS birds beak would degrade alignment mark delity, the EUV alignment marks were patterned in a separate lithography step after the gate oxide growth and the polysilicon deposition. All process steps, except for the ion implantations and the EUV gate level lithography, were performed at the Microfabrication Facilities at the University of California at Berkeley. III. EUV LITHOGRAPHY MASK AND EXPOSURE TOOL EUVL gate level patterning was performed with the EUVL laboratory tool designed and assembled at Sandia National Laboratories.5,6 It is an EUV exposure system with a near-diffraction-limited imaging capability, an accurate stage, and an integrated through-the-lens alignment system. The major components of the tool include a 10 reduction Schwarzschild camera with a numerical aperture of 0.08 operating at 13.4 nm, a laser plasma source, a magnetically levitated stage, and an electrostatic chuck. Other subsystems are a grazing-incidence optical system to maintain focus, and alignment for overlay. The a through-the-lens optical moire exposure eld of the system is 400 m in diameter. Coarse mask-to-wafer alignment was performed in a prealign station
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equipped with a microscope and a micrometer stage. After coarse alignment, the wafers were transferred into the exposure chamber using a manual wafer transfer system. Fine through-the-lens alignment was performed with the moire alignment system.6 The alignment procedure is illustrated in Fig. 2. First, line scans of the captured images of the alignment marks are taken to obtain the alignment signals. From these signals, misalignment errors in x , y , and rotation, are

FIG. 3. A reective mask used in this experiment and a schematic of its cross section. The Ge/hard-baked-resist absorber stack is patterned above the Mo/Si reective coating using a process developed by Tennant et al.7 The coating were removed in the areas below the alignment marks to increase the alignment signal from the mask.

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FIG. 4. a A 0.1 m gate pattern printed over 500 LOCOS topography, b a topographical plot of the transition region between active and eld oxide, showing the 500 topography and the resist coverage of the step. Adequate linewidth control was achieved with 700 thick SAL-601 imaging layer.

obtained and used to drive the wafer stage to the alignment position. Magnication error is adjusted with the six-axis mask stage. This alignment system has demonstrated a sensitivity of 15 nm 3. The hardware and the alignment algorithm are described in more details by Nguyen et al.6 The reective masks used in this experiment were fabricated on 2 in. optical ats using a process developed by Tennant et al.7 A photograph of a mask that contains six exposure elds and a schematic of its cross section is shown in Fig. 3. Each mask consisted of a Ge/hard-baked-resist HBR absorber stack patterned above a Mo/Si reective coating. The masks were patterned with electron-beam lithography using ZEP520 positive resist. The pattern was transferred into the absorber stack by RIE with CF3Br for the Ge layer and with O2 for the hard-baked resist. In order to maximize the alignment signals from the masks, the alignment marks were patterned over areas where the Mo/Si coating had been removed. These areas were dened by an e-beam patterning step, followed by a SF6/O2 RIE to remove the exposed Mo/Si coating. The alignment marks are visible in the photograph in Fig. 3. IV. TRILAYER RESIST PROCESS A trilayer resist process was used to transfer the resist patterns printed by EUVL into a LTO hard mask that served as the etch mask for the poly-Si gates. The trilayer stack comprises an imaging layer, a plasma-enhanced chemical vapor deposition PECVD oxide pattern transfer layer, and a 0.4 m thick hard-baked planarizing resist. The imaging resist was a Shipley SAL-601, a chemically amplied negative resist with sensitivity of 3 mJ/cm2 at 13.4 nm.8 The resist process included a postexposure bake at 105 C for 2 min, followed by an 8 min development in a Shipley MF-322. Topographical coverage with a thin imaging layer was an important consideration in optimizing this process. Due to LOCOS isolation, a 2000 step was created between the
J. Vac. Sci. Technol. B, Vol. 14, No. 6, Nov/Dec 1996

FIG. 5. Outline of the trilayer resist process. a The trilayer stack consisted of a SAL-601 imaging layer, a PECVD oxide pattern transfer layer, and a 0.4 m thick planarizing resist, after EUV exposure. b The resist image is transferred into the trilayer stack by CHF3/CF4/Ar RIE followed by an O2 RIE. d The trilayer stack is used in etching the LTO hardmask. Following the removal of the trilayer stack, the LTO mask is used to pattern the polysilicon gates e.

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FIG. 6. The a 0.1 m and b 0.12 m gate patterns as transferred into the trilayer stack.

active and eld oxide region. Even with 0.4 m planarizing resist, a 500 step remained. However, as shown in Fig. 4, sufcient linewidth control over topography was achieved with this process. The trilayer pattern transfer process is illustrated in Fig. 5. The EUV resist pattern in SAL-601 was transferred into the PECVD oxide by RIE with a CHF3/CF4/Ar gas mixture. The oxide layer, in turn, served as the etch mask for the O2 RIE of the planarizing resist. The 0.1 and 0.12 m gate lines as transferred into the 0.4 m thick HBR layer are shown in Fig. 6. Despite some resist sidewall erosion, the pattern was transferred with sufcient resolution to preserve the critical dimension of the gates. The trilayer stack was then used to pattern the LTO hardmask. Following a resist strip to remove the planarizing resist, the polysilicon gates were patterned, with the LTO etch mask, in a Cl2/He plasma. The hardmask was used instead of photoresist because it yielded a more controllable poly-Si etch process. The gate dimensions were measured with atomic force microscopy after EUVL exposure and with scanning electron microscopy after trilayer etch to ascertain that the desired critical dimension CD was obtained. Cross-sectional transmission electron microscopy TEM is being carried out to quantify the critical dimension CD and edge prole of the polysilicon gates.

voltage V t of 0.56 V. These performance characteristics are consistent with published results for other 0.1 m NMOS transistors.14 The threshold voltage and saturated drain current, at V d of 1.5 V and V g of 1.7 V, for 12 transistors, two at each gate length, are shown in Fig. 9. The gate lengths for these devices ranged from 0.1 to 0.15 m. As expected, the drive

V. DEVICE CHARACTERISTICS Transistors with gate lengths from 0.1 to 20 m have been successfully fabricated with EUVL. Figure 7 shows families of I V characteristics obtained at room temperature for devices with 0.12 and 0.18 m gate lengths. The gate widths were 5 m drawn, and 3 m effective due to the LOCOS encroachment. The gate oxide lms for these devices were 55 thick. Figure 8 shows the I V characteristics for a 0.1 m gate length device, with its subthreshold characteristic in the inset. The 0.1 m gate length device shown here has a subthreshold swing of 90 mV/decade, a saturated transconductance of 250 mS/mm, and a threshold
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FIG. 7. Device characteristics for NMOS transistors with 0.12 and 0.18 m gates. For these devices, the gate oxide was 55 thick, and the polysilicon gate was 1500 thick.

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FIG. 8. Device characteristics for an NMOS transistor with 0.1 m gate. The gate oxide and polysilicon gate thicknesses are 55 and 1500 , respectively. The subthreshold characteristic is shown in the inset. For this device, the subthreshold swing was 90 mV/decade and V t was 0.56 V.

current increased with decreasing gate length. Some V t fall off was also observed. The device characteristics shown here were selected from a large number of I V curves and are only representative examples of the device performance obtained in this lot. A more complete device performance evaluation is in progress, and the results will be presented at a later date.

VI. CONCLUSIONS The work reported in this article is a successful fabrication of MOS transistors with EUVL. NMOS transistors with 0.1 m gate length, with satisfactory I V characteristics, were fabricated by integrating EUVL with a standard NMOS process. A simple trilayer resist process was developed using a commercially available imaging resist. This work demonstrated both the successful integration of the Sandia EUVL laboratory tool and the basic compatibility of EUVL with MOS device fabrication processes.

FIG. 9. Device parameters as a function of gate length, a I dsat and b V t . As expected, I dsat increased with decreasing gate length. Some V t falloff is also observed. J. Vac. Sci. Technol. B, Vol. 14, No. 6, Nov/Dec 1996

G. A. Sai-Halasz et al., IEEE Electron. Device Lett. EDL-8, 463 1987. K. F. Lee et al., in IEDM Conference Digest IEEE, New York, 1993. 3 C. M. Reeves et al., J. Vac. Sci. Technol. B 10, 2917 1992. 4 I. Y. Yang et al., J. Vac. Sci. Technol. A 12, 4051 1994. 5 D. A. Tichenor et al., in Extreme Ultraviolet Lithography Optical Society of America, Boston, MA, 1996. 6 K. B. Nguyen et al., in Electron-Beam, X-Ray, EUV and Ion-Beam Submicrometer Lithographies for Manufacturing VI SPIE, Santa Clara, CA, 1996. 7 D. M. Tennant et al., J. Vac. Sci. Technol. B 9, 3176 1991. 8 G. D. Kubiak et al., Appl. Opt. 32, 7036 1993.
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