A&D ,p 1

Decoder Encode De-MUX Multiplexer

n X m m 2 ; one o/p line will enable for diff i/p n X m n 2 ; at time one i/p line only encoded. 1 X m m= 2 ; E is no.of enable pins. n X 1 n= 2 ; E is no.of enable pins. F = AB I 0 + AB I 1 + AB I 2 + AB I 3
JK FF Q(t) 0 0 1 X J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t)* Q(t+1)=TQ+TQ Q(t+1)=D T FF (toggle) T 0 1 Q(t+1) Q(t) Q(t) D FF (dela y) MOSFET - NAND for +ve logic Emitter coupled logic (ECL) NOR for +ve logic D 0 1 Q(t+1) 0 1 Adv:as the load is realised by the MOSFET itself the package density . Fanout bcoz high i/p resistance. a)Open collector TTL: Adv: used to drive LEDs, Lamps Used in commen bus system Dis adv:over all speed is less b) Toten pole TTL:adv: swiching speed is high,bcoz =RC is reduced, emitter follwer o/p resistance(R) is Differential Amplifier: (high i/p R, low o/p R) One transister will draw more ct.(power disipation Ct mode logic: No swiching cts less disipation. Adv:both NOR, OR gate are available. Wired OR logic, swiching speed .Fanout Dis.adv:power disipation as the transistors are always in active region. Poor noice margin. Dis adv: Swiching speed c) Tristate TTL:adv: tristate (0, 1, high impedence state), in high impedence state power disipation is 0.
E E m

CMOS INVERTER for +ve logic Diode Transistor Logic (DTL)-NAND for +ve logic Transistor transistor logic (TTL) NAND for +ve logic

SR FF S 0 0 1 1 R 0 1 0 1

T depends on previous sta te

O/p = i/p

Q(t+1)=S+RQ(t)

Q(t+1)=JQ+KQ

Ri ng Counter f/N As table Mul ti Vibra tor Squa re wa ve genera tor

Johnson f/2N Bi s table Multi vibra tor

Ri pple f/2n Mono s table Pulse genera tor

Modules f/N Schmi tt tri gger Squa ring ckt, flip flop

1 bi t memory element(flip flop)

Res olution/step si ze = VR/2N Bi na ry wei ghted Resis ter DAC R-2R ladder DAC

DAC N No.of s teps (n)= [2 -1] N Full s cale o/p=[2 -1] x(S) :. (S) is Step size %Resolution = (S)/F s cale o/p=1/[2N -1]x100 Dis adv: If the si ze of DAC size of Resistance value become la rge Adv: Better linea rty, It requi res onl y two diff types of resis wi th R, 2R ADC Converti on time= [2N-1] x T Where T is Clock period Dis adv: In the s teady s tate i f the i/p Vt , i t cant tra ck the i/p In above ADC repla ce counter wi th updown counter Replace counter with Succssi ve approxima tion Dis adv: for N-bit flash type ADC no.of requi red compera tors 2N-1 More accurate

Res olution/step si ze = V/(2N-1); V is range of i /p vol ta ge eg:-V/2 to V/2 Counter type ADC Tra cking type ADC Succssi ve approxi mati on ADC Convertion ti me= N x T Flash type ADC (pa rallel ADC) Fastest ADC Dual slope ADC (Integra ting ADC)

DTL TTL ECL MOS CMOS Fan out 8 10 25 20 >50 Prop.delay (nsec) 30 10 4 300 70 Power dissipation(mw) 8 10 40 0.2 1 0.01 Noise margin (mV) 700 400 200 150 300 HTL(high Tr eshold logic)--noise margin ,use near Industries tristate logic have 3 states 0, 1, high impedance state. NMOS is faster than PMOS

Adv: less power consumption. More fanout.

A&D ,p 2 Mi cro prossor: 8085 16 add.lines (A0-A15 8 da ta lines(D 0 - D 7) f= 3.072 Mhz clock period T =1/f =320nsec 8-bi t regis ter--7 16-bi t register--3 B BC C D DE E H HL L ACC PSW=ACC8+Fla g.Reg 8(prog s tatusword) AC X P X Ins truction Types : 1.Da ta transfer 2.Arthemeti c 3.logi c 4.M/C Related I/O 5.Additi onal

Fla g Register S Z

Cy

Set Interrupt Mask (SIM) SOD SDE X Priori ty Hi gh Least

R 7.5

MSE

M 7.5

M 6.5 Masking NMI Maskable Maskable Maskable Maskable

M 5.5

TRAP RST 7.5 RST 6.5 RST 5.5 INTR

Vector Add 0024 H 003C H 0034 H 002C H NVI ( Non-vector int )

Rea d Interrupt Mask SID I7 I6 Source R, R.P

I5

I.E

I 7.5

I 6.5

I 5.5

1.Regis ter

Des tina tion R, R.P

2.Di rect 3.Reg Indi rect 4.Immediate 5.Impli cit

R/M

M/R

8/16 bi t add Acc

R, R.P, Memory Acc

Example MOV C,A ADD R XCHG HL,DE LDA 5000 LHLD 8250 LDAX B BCA MVI C,32 32C LXI B,1111 1111BC DAR, RLC, RAC, CMA

A&D ,p 3

BJT (bipolar jection Transister) 1.Bipolar 2. High power 3.Low speed(w.r.toperating freq) High Speed(w.r.t Swithching i/p) 4. Noice margin 5. Fanout 6.Fanin 7.package densty 8. gain 9. BW Diode [+, -] V/Vt I = I S [e -1] I S -Reverse sat Ct VT - 26mv = KT/q non-identity const, no dimention

FET (Field effect Transistor) 1.uniploar 2. Low power 3. High speed Low Speed 4. Noice margin 5. Fanout 6.Fanin 7.package densty 8. gain 9. BW FET [G, D, S] 2 I D = IDS [1-(VGS/VP)] I D VGS Vt controlled

BJT [B, E, C] I C = I B + (1+) I CB Ic I B Ct Controlled

Ri Ro AI AV = AI x (Ro/Ri) Phase shift b/w i/p&o/p Vt Applications

CB Low (100 High 450 K = I C/I E 1 Low High >1500 0 or 360 High freq. Ckts RF = /* +1+

CE Medium750 Medium45K = I C/I B High (50-500) Medium 500 180 For Audio freq. = /*1 - +

CC High (750 K) Low (25 ) =I E/IB High (51-501) Low <1 0 or 360 For impdance matching = +1 = 1/1 -

Ideal op-amp cha racteris ti cs 1. i/p i mp = o/p i mp =0 hence vol ta ge a mplifier 2.gain = - 3. BW = 4. slew ra te = 5. CMRR (common mode rejection ra tio =A d/Ac) should be high = Schmi tt tri gger (a special type of bistable MV) Squa ring ckt:(any a rbi ta ry w/f converted into an uns ym squa re wa ve) Sili con Transistor (N-P-N) V = 0.5 V VBE(act) = 0.6 V VBE(sat) = 0.6 V Germanium Transistor (N-P-N) V = 0.1 V VBE(act) = 0.2 V VBE(sat) = 0.3 V