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Single Electron Transistor Instructor: Pei-Wen Li

Dept. of E. E. NCU
1
Single-Electron Transistors
Reference book:
Single Charge Tunneling Coulomb Blockade
Phenomena in Nanostructures
By Hermann Grabert and Michel H. Devoret, 1992
Referred Journal Review Papers:
Correlated discrete transfer of single electrons in ultrasmall tunnel juntions
By K. K. Likharev, IBM J. Res. Develop. Vol.32, p.144, 1989
Single-Electron Devices and Their Applications
By K. K. Likharev, Proceedings of the IEEE, vol.87, p.606, 1999
Single-Electron Memory for Gita-to Tera Bit Storage
By K. Yano et al., Proceedings of the IEEE, vol.87, p.633, 1999
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
2
Contents
Single Electron Phenomena: A General Introduction
Single Electron Transistor
Fabrication and Analysis
Applications
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
3
Single Electron Phenomena: A General Introduction
.Scaling prospects for various
bit-addressable memories.
DRAM is expected to be bottlenecked at
the generation of 64 Gbit integration (70
nm technology) due to the problems with
the storage capacitor scaling.
Nonvolatile memory is going to be the
mainstream for 64Gbit-16Tbit memory.
SET/FET would be feasible starting from
~ 3 nm minimum feature sizes.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
4
SET Evolution
The manipulation of single electrons was demonstrated in the seminal
experiments by Millikan at the very beginning of 20 century.
Single Electron Device: in which the addition or substraction of a small number
of electrons to/from an electrode can be controlled with one-electron precision
using the charging effect.
They are not interesting not only as new physical phenomena in nanostructures but also
because they offer new operating principles for future ICs.
Application: Memory, switch, Thermal meter
Advantages:
Good stability: is the strong incentive to explore the possibility of the devices.
atomic scale physical dimension ULSI possible
Ultralow power operation: simply because they use very small number of electrons to
accomplish basic operation.
Fast operation: only a few electrons (<100) are transferred, therefore, the charge/discharge
process might be faster than those of conventional devices. (100,000 electrons)
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
5
Schematic of Single Electron Devices
A quantum dot is weakly coupled by tunnel barriers to two electron reserviors.
Oxide
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
6
A General Introduction
Recall that the motion of electrons in an infinite potential well is in a standing
waveform. That means that the energy of the particle in the infinite potential
well is quantized. That is, the energy of the particle can only have particular
discrete values.
integer positive a is n where

2
2
2 2 2
ma
n
E E
n
h
= =
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
7
Charging Energy
Let a small conductor (island) be initially electroneutral, i.e., have exactly as
many (m) electrons as it has protons in its crystal lattice. In this state the island
does not generate any appreciable electric field beyond its borders, and a weak
external force may bring in an additional electron from outside. Now the net
charge of the island is (-e), and the resulting E field repulses the following
electrons which might be added.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
8
Charging Energy
The charging energy of the island is E
C
, where C is the capacitance of the island:
When the size of the island becomes comparable with the de Broglie
wavelength of the electron inside the islandenergy quantization
The energy scale of the charging effects is given by a more general notion, the
electron addition energy (E
a
). In most cases of interest, E
a
could be
approximated by
Here E
k
is the quantum kinetic energy of the addition electron; for a degenerate
electron gas E
k
= 1/g(
F
)V, where V is the island volume and g(
F
) is the density
of states on the Fermi surface.
C
e
E
C
2
=
k C a
E E E + =
( )
m
k
mW
n
E
N
2 2
2 2
2
2
h h
+ =

Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
9
Electron Transfer in an quantum dot
The transport of electrons through the quantum dots is an interplay of resonant
tunneling and Coulomb blockade effects.
In the absence of charging effect, a conductance peak due to resonant tunneling
occurs when the Fermi energy E
F
in the source lines up with one of the energy
levels in the dot.
However, this condition is modified by the charging effect. The energy level
is renormalized by the charging effect
That is, the renormalized level spacing is enhanced above the
bare level spacing by the charging energy.
level bare the is where ,
2
1

2
*
n n N
E
C
e
N E E
|
.
|

\
|
+

2
C
e
E E + =
level energy bare the is where ,
2
2
2 2 2
n n F
E
ma
n
E E
h
= =
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
10
Single-electron tunneling through a quantum dot
The energy levels, E
N
, are modified by the charging effect. That is the
charging energy regulatesthe level spacing.
The spin degeneracy is lifted by the charging energy.
C
e
E E
2
*
+ =
Bare Energy level
Normalized Energy level
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
11
Single-electron tunneling through a quantum dot
(a) , with N referring to the lowest unoccupied level in
the dot.
(b) An electron has tunneled into the dot,
) 1 (
2
2
+ = + N e E
C
e
E
F N

) (
2
2
N e E
C
e
E
F N
+ =
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
12
Addition Energy, Kinetic Energy
For 100-nm-scale devices, E
a
is dominated
by the charging energy E
c
and is of the
order of 1 meV (~10 K). Since the thermal
fluctuations suppress most single-electron
effects unless
these device have to be operated in the
sub-1-K range. Unpractical!
If the island size is below ~ 10 nm, E
a
approaches 100 meV, and some single
electron effects become visible at RT.
However, digital SE devices require
even higher values of E
a
to avoid thermally
induced random tunneling events, so that
minimum feature size of SET has to be
smaller than ~ 1nm. RT operation
E
a
= E
C
+ E
T k E
B a
10
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
13
Single Electron Transistor
The resulting SET device is reminiscent of a usual MOSFET, but with a small
conducting island embedded between two tunnel barriers, instead of the usual inversion
channel.
The expression of the electrostatic energy W of this SET is
n
1
and n
2
are the number of electrons passed through the tunnel barriers one and two,
respectively, so that n = n
1
- n
2
, while the total island capacitance C
total
is now a sum of
C
0
, C
1
, C
2
, and whatever stray capacitance the island may have. The external charge Q
e
= C
0
V
g
is just a convenient way to present the effect of the gate voltage V
g
.
| | const C C n C n eV C Q ne W
total total e
+ + = / 2 / ) (
1 2 2 1
2
V
g
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
14
Single Electron Transistor (SET)
Operation principle:
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
15
I
d
-V
d
Characteristics
I
d
-V
d
is a function of V
g
.
Coulomb Blockade Threshold Voltage V
th.
Coulomb gap
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
16
Coulomb Gap
Large bias (V
ds
) I
d
-V
ds
measurements
generally probe the excitation
spectrum of the dot. The conductance
peaks are associated with the excited
electron states in the QD, appearing
whenever such an excitation is aligned
with the Fermi level of one of the S/D
leads.
The Coulomb-blockade gap is
manifested by the flat region of the I
d
-
V
ds
curve spanning V
ds
~ 0V. At the
edge of the gap, the large peak in
differential conductance on either side
marks the threshold voltage above
which electrons can tunnel into the dot.
( )
s d
ds
C C
e
V gap Coulomb
+
= =
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
17
Coulomb Staircase
Unlike the Coulomb suppression of current in the neighborhood of V
ds
= 0 V
(Coulomb gap), the staircase is not a universal feature of the Coulomb blockade.
Rather, it is a special result of having very different tunneling rates through the
two tunneling barriers.
Coulomb staircase
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
18
Coulomb Staircase
Increasing V
ds
, the quasi-fermi
level on Source lead is raised by
the bias potential; initially no
current flows because electrons at
the quasi-fermi level do not yet
have enough energy to overcome
the charging energy of the QD.
Eventually, V
ds
reaches the point
at which an electron can tunnel
from the Source lead onto the
QD. current flow and a peak
in G is observed.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
19
Physics of Coulomb Staircase
Increasing gate voltage V
g
attracts more and more electrons to the island. The
discreteness of electron transfer through low-transparency barriers necessarily
makes this increase step like.
When one tunnel barrier is significantly more transmitting than the other tunnel
barrier, the I-V behavior of the dot can exhibit the namely Coulomb staircase
behavior, that is a stepwise curve.
What is surprising is that even such a simple device allows a reliable
addition/subtractionof single electrons to/from an island with an enormous
(and unknown) number of background electrons, of the order of one million in
typical low-temperature experiments with 100-nm-scale aluminum islands.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
20
I
d
-V
g
Characteristics
Coulomb-Blockade Oscillation in I
d
-V
g
and conductance-V
g
, where conductance
d
d
V
I
G =
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
21
Conductance Positions
The gate-voltage position of the conductance peaks, corresponding to charge-
degeneracy points, are determined at very low temperatures by the conditions
E(N) = E(N+1), which leads to e
N+1
= (N+1/2)e
2
/C +
N+1
.
(Recall that ,
where
i
represents the energy of the i
th
eigenstate relative to the Fermi level in
the QD and the summation is over the set of occupied states.)
The spacing between conductance peaks ,
where E
a
is the single-electron addition energy,
is the Coulomb charging energy and
is the quantized level separation.
The gate-voltage position of the conductance peaks contains information about
the single-particle energies. (addition energy, charging energy, and quantized
level separation)
( )

+ =
N
i
Ne
C
Ne
N E
2
) (
2
e
E
C
e
e
E
V
dot
a
g


+ = =
dot
C
e

E
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
22
Conductance Positions
In principle, unless the single-particle levels
I
are equally spaced, the
conductance peaks are not exactly periodic in V
g
. This is true as long as kT <<
E, for which peaks are narrow enough to resolve the contribution of .
However, as long as the charging energy is larger than the level spacing, as is
often the case in the planar QDs that are a few hundred nm in size, the
deviations from periodicity are relatively small.
g
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
23
Temperature Behavior of Conductance Peaks
At low temperatures, the heights of successive peaks in V
g
vary non-monotonically and
adjacent peaks are separated by broad minima.
when kT << E, the conductance of any particular peak is entirely determined by the tunneling
rates
i
l
and
i
r
of a specific single particle state i. Large-amplitude peaks are associated with
states that are more strongly coupled to the source or drain leads; low-amplitude peaks with
weakly coupled states.
As the temperature is increased, all the peaks are broaden; their amplitudes decrease in
some cases and increase in other cases; in certain cases (the peak shown furthest to the
right), the amplitude first decreases then increases as the temperature is raised.
As temperature is increased and kT ~ E , each conductance peak is influenced by contributions of
tunneling through several discrete energy states, although still within the constraint of one electron at a time.
The monotonic increase in peak amplitudes at high temperatures simply reflects the trend towards more
strongly coupled levels at higher V
g
.
The coefficient can be determined from the temperature dependence of the peaks full width at half-
maximum: FWHM = 3.5kT/(e)
2
.
Eventually, at the highest temperature, peak overlap significantly and the amplitude of
successive peaks in V
g
increases monotonically.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
24
Rhombus Shapes in the Contour Plot of differential
conductance
G< 0
Fine
structure
S
1
V
g
/ V
d
=C
d
/C
g
S
2
V
g
/ V
d
=C
s
/C
g
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
25
Device Parameters Extracted from the Rhombus Shapes
The electronic structure in the QD could be extracted from the contour plot of
the differential conductance as a function of V
g
and V
d
.
The ratio of the gate-dot (C
g
), drain-dot (C
d
), and source-dot (C
s
) capacitances
can be calculated from the slope S
1
and S
2
.
C
g
: C
d
: C
s
= 1: S
1
: S
2
Then the gain modulation C
g
/C
total
, C
total
= C
g
+ C
d
+ C
s
The addition energy E
a
= V
g
.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
26
Electronic Structure extracted from I-V
Addition Energy
Charging Energy
Energy level spacing
Dot diameter
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
27
Minimum tunneling resistance for single-electron
charging
Implicit in the formulation of the Coulomb-blockade model is the condition that the
number of electrons localized in the dot island, N, is a well-defined integer. This is to say,
well defined in the classical sense, as opposed to a quantum definition which describes N
in terms of an average value <N>, which is not necessarily an integer, and time-averaged
fluctuations <N
2
>.
The Coulomb-blockade model requires that <N
2
> << 1. Clearly, if the tunnel barriers
are not present, or are insufficiently opaque, nothing will constrain a quantized
electronic charge to be confined within a certain volume. A general view is that there is a
minimum resistance which the barriers must exceed in order to have <N
2
> << 1, and
this resistance is of the order of the quantum resistance R
K
= h/e
2
= 25,813 .
The condition <N
2
> << 1 requires that the time that an electron resides on the dot, , be
much greater than , the quantum uncertainty in this time. The current I cannot exceed
e/ since no more than one extra electron resides on the dot at any instant. The energy
uncertainty of the electron, E, is no larger than the applied voltage, hence the condition
that << translates into macroscopic variables using I e/, E h and E < eV
ds
.
Doing so gives the minimum tunneling resistance condition, R
K
= V
ds
/I h/e
2
.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
28
Co-tunneling
Even if the minimum resistance criterion is met and single-electron charging
effects are manifested, small quantum fluctuations, or uncertainties, in N are not
entirely ruled out. In the classical Coulomb-blockade model there is then a fixed
number of electrons N on the QD and at T= 0 the charge on the QD does not
fluctuate.
However, the fact that very small quantum fluctuation in N may be present
corresponds to electrons momentarily tunneling onto the QD, with an energy
deficit on the scale of the classical Coulomb charging energy.
Essentially, the tunneling electron resides on the QD in a virtual charge state for
a sufficiently brief interval such that the energy uncertainty of this state is larger
than its classical energy deficit, subsequently tunneling out. This process has
been referred to as co-tunneling or macroscopic quantum tunneling of charge.
The rational behind is that the total charge of the system (a macroscopic
variable) undergoes a transition through a classically forbidden intermediate
state, in apparent violation of the Coulomb blockade.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
29
Elastic co-tunneling
The tunneling of an electron into a certain energy state and the tunneling of an
electron from the same state out of the dot. The end result of the two tunneling
events is that the state of the QD is unchanged, and as such, this is referred to as
elastic co-tunneling, which contributes a linear term to the I-V curve.
where is the average energy separation between eigenstates in the QD and E
1
(E
2
) is the charging energy associated with adding (removing) a single electron
to (from) the dot. Note, in particular, that the resulting conductance scales
roughly as the ratio between the level spacing and the Coulomb gap U e
2
/C.
The case of elastic co-tunneling depends, in principle, on the geometry of the
QD. This is because the electron involved has to couple to both leads; thus in a
sense it must traverse the dot in a virtual state.
V
E E
e
h
I
el
|
|
.
|

\
|
+

=
2 1
2 2
2 1
1 1
8

Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
30
Inelastic co-tunneling
It corresponds to an electron tunnels into a certain state in the dot and a second
electron, from a different state, tunnels out of the dot. The state of the dot is
modified, leaving an electron-hole excitation. The resulting current is nonlinear
in V
ds
and temperature-dependent. The case of inelastic co-tunneling gives the
following well-known form
( ) V
eV
kT
E E
e
h
I
inel
(
(

|
.
|

\
|
+
|
|
.
|

\
|
+

=
2
2
2
2 1
2
2 1
2
1 1
6


Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
31
Cotunneling
The distinction is made between these two processes because their relative
contributions to the total net cotunneling current depend on the density of states
in the QD.
In metal QDs, in which the density of states is large, the elastic component of
co-tunneling is usually overwhelmed by the inelastic component.
In semiconductor QDs, in which the density of states is much smaller than in
metals, both elastic and inelastic terms can contribute to the co-tunneling
current.
In practice, co-tunneling is expected to modify the classical picture of single-
electron charging in the form of excess current in the region of the Coulomb-
blockade gap, in the case of I-V
ds
measurements, or excess tunneling current
between conductance peaks in low-bias measurements.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
32
Fabrication
To apply SETs for low power ICs, (i) room-temp operation; (ii) uniformity and
(iii) compatible with the LSI processes are required.
Task:
For room temperature operation, the quantum dot diameter should be less than 10
nm, which corresponds to the total capacitance about 1 aF.
E-beam lithography:
High cost and the following etching process is not easy to control
Scanning probe microscopy (SPM) to place Au atoms in nanostructure.
Only applicable in specific substrate
Metal/Superconductor SET
Semiconductor SET
Epitaxial growth quantum dots (self-assembled) or 2DEG with side gate (depletion)
E-beam + dry etching
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
33
Fabrication
In addition to advanced e-beam lithography technology, matured and
controllable fabrication processes are needed to form small quantum dots (<10
nm).
Various approaches to achieve room-temp operation:
Oxidation
Isotropic/anisotropic wet etch
Scanning tunneling microscope nano-oxidation process
Side-gate
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
34
Self-aligned Floating Dot gate (1997)
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
35
Si quantum dot formed by 2D oxidation
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
36
Double-dot charge transport in SET/SHT
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
37
Ge implantation/Ge Segregation
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
38
Application
Major application fields:
Memory
Digital-data-storage
Precision Measurement
Memory >> Logic
We can use SE devices only in a memory cell, whereas keep using conventional
CMOS technology in the peripheral circuitry.
Memory cell technology has continuously changed, including the emergence of
flash memory technology and ferroelectric-film memory technology.
The way of storing information is rapidly changing from the old regime, relying on
papers and other analog electronic means, to the digital regime in the multimedia era.
New needs of storing information are different from the older specifications in
bandwidth, storage capacity, power consumption.
Fundamental difficulty in a logic functional unit since SE devices generally have
poor current-drive capability.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
39
Application-Data Storage System
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
40
Quantum Information- Qubit
Developing a quantum computer is a basic endeavor in science
and technology.
The advantage of Si-based quantum computer is
Low cost
Large scale integration
Contrast to classical bits, ,0> or ,1> , a quantum computer consists
of Qubits, which could be represented by a superposition of ,0>
or ,1> , i.e.,
,0> + ,1> (where
2
+
2
=1)
This huge parallelism makes it possible to solve some of the most
difficult problems, such as integer factorization.
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
41
Quantum Computer Roadmap: development status
After NTT Technical Review, June 2003
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
42
Roadmap of Quantum Computer
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
43
Quantum Computer Roadmap:
status of solid-state QC
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
44
Si-based Key Devices for QC
Source
Drain
Island
Si
Figure 1. Schematic diagram for a single electron transistor and a
coupled quantum dots.

(singlet) |0> |1>


|0> |1>
(quantum bit).


Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
45
Accomplishments in NCU
Atomic-scale Ge QDs formed by thermal oxidation of SiGe-on-insulator.
20 min.
25 min.
Ge precipitation
Buried Oxide
Single Electron Transistor Instructor: Pei-Wen Li
Dept. of E. E. NCU
46
Room-Temperature Characterization of Ge SETs
Peak-to-valley current ratio (PVCR) of
1.92 is observed at room temperature
Clear offsets and plateaus are seen for
gate voltages corresponding to the drain
current valleys, while linear relations are
obtained for gate voltages corresponding
to the drain current peaks.

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