CSE140: Components and Design Techniques for Digital Systems Boolean algebra & logic circuits

Tajana Simunic Rosing

Boolean algebra g
Boolean Algebra
B={ {0, , 1} } Variables represent 0 or 1 only Operators return 0 or 1 only Basic operators
is logical AND: a AND b returns 1 only when both a=1 and b=1 + is logical OR: a OR b returns 1 if either (or both) a=1 or b=1 is logical NOT: NOT a returns the opposite of a (1 if a=0 a=0, 0 if a=1)

All algebraic axioms hold

a 0 0 1 1 x y F b 0 1 0 1 OR 0 1 1 1 x y F a 0 0 1 1 b 0 1 0 1 AND 0 0 0 1 a 0 1 NOT 1 0

OR

AND x

NOT F

Axioms and theorems of Boolean algebra g

identity 1. X + 0 = X null 2. X + 1 = 1 idempotency: 3. X + X = X involution: 4. (X) = X complementarity: 5. X + X = 1 commutativity: y 6. X + Y = Y + X associativity: 7. ( (X + Y) )+Z=X+( (Y + Z) ) 1D. X 1 = X 2D. X 0 = 0 3D. X X = X

5D. X X = 0 6D. X Y = Y X 7D. ( (X Y) )Z=X( (Y Z) )

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Axioms and theorems of Boolean algebra (contd)

distributivity: 8. X (Y + Z) = (X Y) + (X Z) Z) uniting: 9. X Y + X Y = X absorption: 10. X + X Y = X 11. (X + Y) Y = X Y factoring: 12. (X + Y) (X + Z) = X Z + X Y concensus: 13. (X Y) + (Y Z) + (X Z) = X Y + X Z 8D. X + (Y Z) = (X + Y) (X +

9D. (X + Y) (X + Y) = X 10D. X (X + Y) = X 11D. (X Y) + Y = X + Y 12D. X Y + X Z = (X + Z) (X + Y) 13D. (X + Y) (Y + Z) (X + Z) = (X + Y) (X + Z)

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Axioms and theorems of Boolean algebra (contd)

de Morgans: g 14. (X + Y + ...) = X Y ...14D. (X Y ...) = X + Y + ... generalized li d d de M Morgans: 15. f(X1,X2,...,Xn,0,1,+,) = f(X1,X2,...,Xn,1,0,,+) establishes relationship between and +

Axioms and theorems of Boolean algebra (contd)

Duality
a dual of a Boolean expression is derived by replacing by +, + by , 0 by 1, and 1 by 0, and leaving variables unchanged any theorem that can be proven is thus also proven for its dual! a meta-theorem (a theorem about theorems)

duality: 16. X + Y + ... X Y ... generalized duality: 17. f (X1,X2,...,Xn,0,1,+,) f(X1,X2,...,Xn,1,0,,+) Different Diff t th than d deMorgans M L Law
this is a statement about theorems this is not a way to manipulate (re-write) expressions
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Proving g theorems
Using the axioms of Boolean algebra:
e.g., g , prove p the theorem:
distributivity (8) p y (5) ( ) complementarity identity (1D)

X Y + X Y = X
X Y + X Y X (Y ( + Y) ) X (1) = X (Y + Y) = X( (1) ) = X9

e.g., prove the theorem:

identity (1D) distributivity (8) identity (2) identity (1D)

X+XY
X X X X + XY 1 + XY (1 + Y) (1)

= X
= = = = X X X X 1 + XY (1 + Y) (1) 9
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Proving g theorems example p

Prove the following using the laws of Boolean algebra:
( (X Y) ) + (Y ( Z) ) + (X ( Z) ) = X Y + X Z

(X Y) + (Y Z) + (X Z) identity complementarity distributivity commutativity factoring null identity (X Y) + (1) (Y Z) + (X Z) (X Y) + (X + X) (Y Z) + (X Z) (X Y) + (X Y Z) + (X Y Z) + (X Z) (X Y) + (X Y Z) + (X Y Z) + (X Z) (X Y) (1 + Z) + (X Z) (1 + Y) (X Y) (1) + (X Z) (1) (X Y) + (X Z) 9
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Proving g theorems (p (perfect induction) )

Using perfect induction (complete truth table):
e.g., g , de Morgans: g

(X + Y) = X Y NOR is equivalent to AND with inputs complemented

X 0 0 1 1 X 0 0 1 1

Y 0 1 0 1 Y 0 1 0 1

X X 1 1 0 0 X 1 1 0 0

Y Y 1 0 1 0 Y 1 0 1 0

(X + Y) Y) X X Y Y

(X Y) = X + Y NAND is equivalent to OR with inputs complemented

(X Y)

X + Y

Example p that Applies pp Boolean Algebra g Properties p

Want automatic door opener circuit (e.g., for grocery store)
Output: f=1 opens door Inputs:
p=1: person detected h=1: h 1 switch it h f forcing i h hold ld open c=1: key forcing closed

Found inexpensive chip that computes:

f = chp + chp + chp

Can we use it?

Want open door when

h=1 and c=0, , or h=0 and p=1 and c=0

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CSE140: Components and Design Techniques for Digital Systems Combinational circuit building blocks: Building gates from transistors
Tajana Simunic Rosing

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Inverter delay

NOT x F x 0 1 1 F 1 0 1 1 1 1

Delay: estimate using Rn & Cg; RP=2Rn

F = x

0 0 0

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Basic CMOS gates

NOT x x F x 0 1 1 F 1 0 y x 0 0 1 1 y 0 1 0 1 F 1 0 0 0 F x F x 0 0 1 1 y 0 1 0 1 F 1 1 1 0 y x 0 NOR y 1 x y F x F y NAND 1

x 0

F = x

Implement logic operators using transistors

Call those implementations logic gates
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AND/OR gates g
OR/AND are harder to make than NOR/NAND
OR x y x 0 0 1 1 1 y x F F= x or y y x 0 y 0 x 0 0 F 1 x 1 y F=x & y y 0 1 0 1 F 0 1 1 1 F x y x 0 0 1 1 y 0 1 0 1 F 0 0 0 1 1 F AND

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Completeness p of NAND
Any logic function can be implemented using just NAND gates. Likewise for NOR. Why? g y
Need AND, OR and NOT

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XOR/XNOR Gates
XOR XNOR

x 0 0 1 1 y 0 1 0 1 F 0 1 1 0 x 0 0 1 1 y 0 1 0 1 F 1 0 0 1

XOR = xy + xy = ( xy + xy) (Exclusive OR) XNOR = (xy + xy) = xy + xy (Exclusive OR)

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Number of Possible Boolean Functions

# of possible functions of 2 variables:
22 rows in truth table, 2 choices for each 2 2(2 ) = 24 = 16 possible ibl f functions ti
a 0 0 1 1 b 0 1 0 1 F 0 or 1 0 or 1 0 or 1 0 or 1 2 choices 2 choices 2 choices 2 choices

N variables
2N rows N 2(2 ) possible functions

24 = 16 possible functions p f3
0 0 1 1

Cost

a
0 0 1 1

b
0 1 0 1

f0
0 0 0 0

f1
0 0 0 1

f2
0 0 1 0

f4
0 1 0 0

f5
0 1 0 1

f6
0 1 1 0

f7
0 1 1 1

f8
1 0 0 0

f9
1 0 0 1

f10 f11 f12 f13 f14 f15

1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

aX XOR b

aN NOR b

a XN NOR b

a (F12) and b (F10): require 2 transistors for an inverter (not gate) a nor b (F4) and a nand b (F14): require 4 transistors a or b (F7) and a and b (F1): require 6 transistors a = b (F9) and a b (F6): require 12 transistors

a NA AND b

aA AND b

a OR b

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Circuits for binary y addition

Half adder (add 2 1-bit numbers)
Sum = Cout =
Ai 0 0 1 1 Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Bi 0 1 0 1 Sum 0 1 1 1 Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 Cout 0 0 0 1 0 1 1 1

Full adder ( (carry-in y to cascade for multi-bit adders) )

Sum = Cout =

A B Cin A B Cin A B Cout S

Sum 0 1 1 0 1 0 0 1

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Example: p 4-bit binary y adder

Inputs: A, B, Carry-in Outputs: Sum, Sum Carry-out Carry out
A B Cin S Cout Cout Cin A B S A B S A B S A B S A B S

a3 b3 a b ci F A co co s s3

a2 b2 a b ci F A co s s2 (a)

a1 b1 a b ci A F co s s1

a0 b0 ci a b ci A F co s s0

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Choosing different realizations of a function

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Z 0 1 0 1 0 1 1 0 Which is the best realization and why? Reduce number of levels of gates
fewer level of gates implies reduced signal propagation delays minimum delay configuration typically requires more gates fewer inputs implies smaller and thus faster gates; fan-in can be limited fewer gates f t means smaller ll circuits i it directly influences manufacturing costs

Reduce number of inputs

Reduce number of gates

two-level realization

Exploring tradeoffs between increased circuit delay and size

tools to generate different solutions logic minimization: reduce number of gates and complexity logic optimization: reduction while trading off against dela delay 20

multi-level realization XOR gate

DeMorgan g and CMOS

Use it to figure out P & NMOS parts of gates

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Rules for making gg gates

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Another way y of making g CMOS g gates

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CMOS Example p

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Another example p

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One more example p

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CMOS Example
The rules:
NMOS connects to GND, , PMOS to power p supply pp y Vdd Duality of NMOS and PMOS Rp ~ 2 Rn => PMOS in series is much slower than NMOS in series

Implement Z using sing CMOS CMOS: Z = (A + BC)

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Another CMOS Example

Implement F using CMOS: F=A*(B+C)

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Summary y
What we covered thus far:
Number representations p Switches, MOS transistors, Logic gates Boolean algebra Supplement: NMOS and PMOS transistor characteristics

What is next:
Combinational logic:
Representations Minimization Implementations

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